I2C slave controller, slave device and electronic control system

Abstract

The utility model discloses an I2C slave controller, an electronic device and an electronic control system, and the I2C slave controller comprises a counting module which is used for recording the number of transmitted bytes generated during an I2C message period; the byte configuration module is used for configuring the total number of bytes of data required by communication with the host equipment at the time; the processor is connected with the counting module and the byte configuration module, and the processor is used for transmitting communication data between the I2C slave controller and the host equipment until the number of transmitted bytes recorded by the counting module reaches the total number of data bytes, and then communication with the host equipment is terminated. By adopting the I2C slave controller, the problem of byte transmission limitation of the I2C slave controller during an I2C message period due to cache limitation can be effectively solved, the complexity of software design is avoided, and the manufacturing cost is lower.

Description

TECHNICAL FIELD

[0001] The utility model relates to I2C slave controller technical field especially is I2C slave controller, slave device and electronic control system. BACKGROUND

[0002] At present, the buffer of the existing I2C (Inter-Integrated Circuit) slave controller is generally only 4 bytes and 8 bytes, and the data that can be received during the transmission of an I2C message is only 4 bytes and 8 bytes. However, when the I2C slave controller transmits a large amount of data with the host device, multiple I2C messages need to be constructed, and a layer of transmission protocol also needs to be customized in the software layer to realize the transmission of a large amount of data, which increases the software design pressure and reduces the data transmission efficiency. SUMMARY

[0003] The utility model discloses at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide an I2C slave controller. The use of the I2C slave controller can effectively solve the problem of byte transmission limitation of the I2C slave controller during an I2C message due to buffer limitation, avoid the complexity of software design, and reduce the manufacturing cost.

[0004] A second purpose of the utility model is to provide an I2C slave controller.

[0005] A third purpose of the utility model is to provide an electronic device.

[0006] A fourth purpose of the utility model is to provide an electronic control system.

[0007] To solve the above problems, the utility model provides an I2C slave controller in the first aspect of embodiment, the I2C slave controller carries out data transmission with the host device, and the I2C slave controller comprises: a counting module, the counting module is used to record the number of transmitted bytes during an I2C message; a processor, the processor is connected with the counting module and the byte configuration module, and the processor is used to transmit the communication data between the I2C slave controller and the host device, and terminate the communication with the host device after the number of transmitted bytes recorded by the counting module reaches the total number of data bytes.

[0008] The I2C slave controller according to the utility model, based on adding counting module and byte configuration module in the hardware structure of the I2C slave controller, judges whether the I2C slave controller stops sending or receiving data through the transmitted byte number recorded by the counting module and the total byte number of data configured by the byte configuration module, so that the I2C slave controller can only be controlled to stop transmitting or receiving data after the transmitted byte number reaches the total byte number of data, and the total byte number of data is greater than the maximum register cache, thereby realizing the transmission of a large amount of data between the host device and the I2C slave controller. Therefore, compared with the existing I2C slave controller which can realize the transmission of a large amount of data by customizing a layer of transmission protocol in the software layer, the total byte number of data transmitted by the I2C slave controller during an I2C message is adjusted by the byte configuration module in the application, so that on the basis of limited I2C slave controller cache, the problem of byte transmission limitation of the I2C slave controller during an I2C message caused by cache limitation can be effectively solved, the data transmission efficiency is improved, the complexity of software design is avoided, and the manufacturing cost is lower.

[0009] In some embodiments, further comprising: a register connected with the processor, used for storing the communication data.

[0010] In some embodiments, further comprising: a timing module connected with the processor, used for managing the clock signal of the I2C slave controller during data transmission.

[0011] In some embodiments, further comprising: an address management module connected with the processor, used for configuring address information of the I2C slave controller.

[0012] In some embodiments, the register comprises: a data receiving register connected with the processor, used for buffering the communication data sent by the host device; and a data sending register connected with the processor, used for buffering the communication data sent to the host device.

[0013] In some embodiments, the processor comprises: a slave processor, used for generating a data transmission state according to the transmitted byte number recorded by the counting module and the total byte number of data, and controlling the communication between the I2C slave controller and the host device according to the data transmission state; and a master processor, used for continuing to read or stopping reading the communication data stored in the register according to the data transmission state, or continuing to write or stopping writing the communication data into the register according to the data transmission state.

[0014] In some embodiments, further comprising: a state transmission module connected with the processor, the state transmission module being configured to send a data transmission incomplete state to the host device when the number of transmitted bytes recorded by the counting module reaches the total number of data bytes, and send a data transmission complete state to the host device after the number of transmitted bytes recorded by the counting module reaches the total number of data bytes.

[0015] In some embodiments, the timing module is connected with the host device through a clock line and a data line, the clock line being configured to transmit a clock signal provided by the host device, and the data line being configured to transmit communication data sent by the host device.

[0016] The second aspect embodiment of the utility model provides a slave device, comprising the I2C slave controller of the above embodiment.

[0017] According to the slave device of the utility model, the I2C slave controller of the above embodiment can effectively solve the problem of byte transmission limitation of the I2C slave controller during an I2C message due to cache limitation, avoid the complexity of software design, and lower the manufacturing cost.

[0018] The third aspect embodiment of the utility model provides an electronic control system, comprising: at least one slave device as described in the above embodiment; a host device configured to perform data transmission with the slave device.

[0019] According to the electronic control system of the utility model, the slave device of the above embodiment can effectively solve the problem of byte transmission limitation of the I2C slave controller during an I2C message due to cache limitation, avoid the complexity of software design, and lower the manufacturing cost.

[0020] Additional aspects and advantages of the utility model will be partially given in the following description, some will become obvious from the following description, or be understood through the practice of the utility model. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and / or additional aspects and advantages of the utility model will become apparent and more readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 is a structural block diagram of the I2C slave controller according to an embodiment of the utility model;

[0023] Figure 2 is a structural schematic diagram of the I2C slave controller according to an embodiment of the utility model;

[0024] Figure 3is a schematic diagram of data transmission of an I2C slave controller and a host device according to an embodiment of the present application;

[0025] Figure 4 is a flow chart of an I2C slave controller data receiving process according to an embodiment of the present application;

[0026] Figure 5 is a flow chart of an I2C slave controller data sending process according to an embodiment of the present application;

[0027] Figure 6 is a structural block diagram of a slave device according to an embodiment of the present application;

[0028] Figure 7 is a structural block diagram of an electronic control system according to an embodiment of the present application.

[0029] Reference signs:

[0030] Electronic control system 1000; Host device 300; Slave device 200; I2C slave controller 100;

[0031] Register 1; Counting module 2; Processor 3; Byte configuration module 4; Timing module 5; Address management module 6; Data receiving register 11; Data sending register 12; Slave processor 31; Master processor 32; State transmission module 7. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary, and the embodiments of the present application are described in detail below.

[0033] At present, in order to control the chip area, the size of the cache opened by each peripheral in the SOC chip needs to be carefully considered. The I2C slave controller is also the same, the I2C slave controller can only process byte level data transmission, and the amount of data transmitted is usually 1 byte to 8 bytes. However, in actual application, the amount of data transmitted is Kbyte or even Mbyte level, which is far more than the cache size of the I2C slave controller, so it is difficult to cope with when a large amount of data needs to be transmitted in the application scenario. On the one hand, the size of the cache inside the I2C slave controller cannot be increased indefinitely, which will expand the chip area and increase the manufacturing cost; on the other hand, due to the limited number of transmission bytes that the I2C slave controller can process, when the transmission is beyond the limit, a set of protocols need to be formulated at the software level, thereby increasing the complexity of software design.

[0034] Therefore, how to realize efficient transmission based on limited cache is a difficulty in the design of the I2C slave controller.

[0035] In order to solve the above problems, the utility model discloses first aspect embodiment provides a kind of I2C slave controller, using the I2C slave controller can effectively solve the problem that I2C slave controller is caused by cache limit during one I2C message byte transmission limit, avoid the complexity of software design, and lower manufacturing cost.

[0036] In embodiments, the I2C slave controller 100 performs data transmission with the host device 300, that is, the host device 300 reads data of the I2C slave controller 100 or writes data to the I2C slave controller 100.

[0037] The following refers to Figure 1 The I2C slave controller 100 according to the embodiments of the utility model is described as follows, as shown in Figure 1 The I2C slave controller 100 includes a byte configuration module 4, a counting module 2 and a processor 3.

[0038] The counting module 2 is configured to record the number of transmitted bytes during one I2C message, and the hardware structure of the counting module is a register. The processor 3 is connected with the counting module 2 and the byte configuration module 4. The processor 3 is configured to transmit communication data between the I2C slave controller and the host device until the number of transmitted bytes recorded by the counting module 2 reaches the total number of data bytes, and then terminate the communication with the host device 300.

[0039] The total number of data bytes can be the number of bytes set according to actual transmission requirements during one IC message. The total number of data bytes can be the total number of bytes received or transmitted by the I2C slave controller 100. The total number of data bytes can be greater than the number of bytes buffered by the I2C slave controller 100. For example, the total number of data bytes can be 10 bytes, 20 bytes, 50 bytes or other user-defined number of bytes, and no limitation is made in this regard. The total number of data bytes can also be less than the number of bytes buffered by the I2C slave controller 100. The I2C bus is a simple bidirectional two-wire synchronous serial bus, and the I2C protocol is a protocol that allows multiple I2C slave controllers 100 and one host device 300 to communicate. The byte configuration module is configured with the total number of data bytes before the I2C slave controller performs data transmission with the host device.

[0040] Specifically, when the I2C slave controller 100 transmits data with the host device 300, the data amount specified in the transmission protocol needs to be transmitted. In the transmission protocol, based on the I2C slave controller 100 buffer limit, the data amount transmitted during an I2C message is 4 bytes and 8 bytes of the I2C slave controller 100 buffer. If the host device 300 wants to transmit data greater than the I2C slave controller 100 buffer, the I2C slave controller 100 can only read 4 bytes and 8 bytes, and cannot confirm whether the remaining data is the data transmitted by the host device 300. At this time, a layer of transmission protocol needs to be formulated again by the upper software. In order to solve this problem, the counting module 2 and the byte configuration module 4 are added in the hardware structure of the I2C slave controller 100. The total data byte amount required for the host device 300 to communicate with the I2C slave controller 100 is configured in the byte configuration module 4. Thus, when the I2C slave controller 100 transmits data with the host device 300, the transmitted byte amount recorded by the counting module 2 and the total data byte amount are used to control the data transmission between the host device 300 and the I2C slave controller 100 to stop, so that a layer of transmission protocol does not need to be formulated again by the upper software to define the data amount between them. Moreover, the total data byte amount is greater than the maximum buffer of the I2C slave controller 100, so that the transmission of a large amount of data between the host device 300 and the I2C slave controller 100 is realized. Based on this, when the host device 300 transmits data with the I2C slave controller 100 during an I2C message, for example, the host device 300 sends data to the I2C slave controller 100 during an I2C message, and the I2C slave controller 100 sends data to the host device 300 during an I2C message, whether the communication between the host device 300 and the I2C slave controller 100, i.e., the data transmission, is completed is determined by judging whether the transmitted byte amount recorded by the counting module 2 reaches the total data byte amount. That is, after the transmitted byte amount recorded by the counting module 2 reaches the total data byte amount, the communication with the host device 300 is terminated, and the communication data corresponding to the total data byte amount is realized. Thus, compared with the existing I2C slave controller 100 which can realize large data transmission only by reconfiguring a layer of transmission protocol in the software layer, the total data byte amount transmitted by the I2C slave controller during an I2C message is adjusted by the byte configuration module 4 in the present application, so that on the basis of the limited buffer of the I2C slave controller 100, the problem of byte transmission limit of the I2C slave controller 100 during an I2C message caused by the buffer limit can be effectively solved, the data transmission efficiency is improved, and a layer of transmission protocol does not need to be formulated again by the upper software to define the data amount transmitted by them, avoiding the complexity of software design and reducing the manufacturing cost.

[0041] The I2C slave controller 100 according to the utility model, based on increasing counting module 2 and byte configuration module 4 in the hardware structure of I2C slave controller 100, judge whether I2C slave controller 100 stops sending or receiving data through the data total byte number configured by byte configuration module 4 and the number of transmitted bytes recorded by counting module 2, so that I2C slave controller 100 can only stop transmitting or receiving data after the number of transmitted bytes reaches the data total byte number, and the data total byte number is greater than the maximum register cache, thereby realizing the transmission of a large amount of data between host device 300 and I2C slave controller 100. Therefore, compared with the existing I2C slave controller 100, which can realize large data transmission by customizing a layer of transmission protocol in the software layer, the application adjusts the data total byte number transmitted by I2C slave controller 100 during an I2C message through byte configuration module 4, thereby effectively solving the problem of byte transmission limitation of I2C slave controller 100 during an I2C message due to cache limitation on the basis of limited I2C slave controller 100 cache, improving data transmission efficiency, avoiding the complexity of software design, and reducing manufacturing cost.

[0042] In some embodiments, as shown in Figure 2 The I2C slave controller 100 further comprises a register 1.

[0043] The register 1 is connected with the processor 3 and is used for storing communication data. The register 1 is a register for caching communication data.

[0044] For example, when the host device 300 transmits data to the I2C slave controller 100 during an IC message, the register 1 first buffers the data corresponding to the maximum storage byte number of the register 1, the counting module 2 records the transmitted byte number as the sum of the last recorded transmitted byte number and the maximum storage byte number, and then the processor 3 of the I2C slave controller 100 reads the communication data corresponding to the maximum storage byte number of the register 1 from the register 1, until the transmitted byte number recorded by the counting module reaches the total data byte number, the communication with the host device 300 is terminated, that is, the I2C slave controller 100 stops receiving the data transmitted by the host device 300; the total data byte number transmitted by the I2C slave controller 100 to the host device 300 is set in advance in the I2C slave controller 100, when the I2C slave controller 100 transmits data to the host device 300 during an IC message, the processor 3 of the I2C slave controller 100 delivers the data of the I2C slave controller 100 to the register 1, after the register 1 buffers the data corresponding to the maximum storage byte number of the register 1, the counting module 2 records the transmitted byte number as the sum of the last recorded transmitted byte number and the maximum storage byte number, and then the I2C slave controller 100 reads the communication data corresponding to the maximum storage byte number from the register 1, until the transmitted byte number recorded by the counting module reaches the total data byte number, the communication with the host device 300 is terminated, that is, the I2C slave controller 100 stops transmitting data to the host device 300. Thus, the data transmission of multiple byte numbers between the host device 300 and the I2C slave controller 100 is realized.

[0045] In some embodiments, as shown in Figure 2 The I2C slave controller 100 further comprises a timing module 5.

[0046] The timing module 5 is connected with the processor 3, and is used for managing the clock signal of the I2C slave controller 100 during data transmission. The clock signal is used for indicating the reading and writing of the communication data. The timing module 5 is used for sampling or generating the clock signal of the I2C slave controller 100 during data transmission, and feeding back the clock signal to the processor 3. The hardware structure of the timing module is a register.

[0047] In some embodiments, as shown in Figure 2 The I2C slave controller 100 further comprises an address management module 6.

[0048] The address management module 6 is connected with the processor 3, and is used for configuring the address information of the I2C slave controller 100. The address information is the unique address of the I2C slave controller 100 in the I2C communication. Based on this, each I2C slave controller 100 has a unique address on the I2C bus, so as to facilitate the host device 300 to identify the I2C slave controller 100 and communicate. The hardware structure of the address management module is a register.

[0049] Specifically, the processor 3 reads the address information of the I2C slave controller 100, and then determines whether the host device 300 reads the data of the I2C slave controller 100 according to the address information.

[0050] For example, as shown in Figure 3 When the host device 300 initiates communication, it first sends a start signal, and then sends the address information of the I2C slave controller 100, read or write, and the I2C slave controller 100 determines that the host device 300 wants to write communication data to the I2C slave controller 100 according to the address information. After receiving the first communication data, the I2C slave controller 100 sends an acknowledgement character, and after receiving the nth communication data, it sends an end signal, where n is greater than the number of bytes cached by the I2C slave controller 100, and n can be 10 bytes or 20 bytes.

[0051] In some embodiments, as shown in Figure 2 The register includes a data receiving register 11 and a data sending register 12.

[0052] The data receiving register 11 is connected to the processor 3 and is used to cache the communication data sent by the host device 300. When the processor 3 of the I2C slave controller 100 receives the communication data sent by the host device 300, it sends the communication data to the data receiving register 11, and the data receiving register 11 caches the communication data. The data sending register 12 is connected to the processor 3 and is used to cache the communication data sent to the host device 300. When the I2C slave controller 100 sends the communication data to the host device 300, the processor 3 reads the communication data cached in the data sending register 12.

[0053] In some embodiments, the processor 3 includes a slave processor 31 and a master processor 32.

[0054] The slave processor 31 is configured to generate a data transmission state according to the number of transmitted bytes recorded by the counting module 2 and the total number of data bytes, wherein if the number of transmitted bytes does not reach the total number of data bytes, it indicates that the data transmission is not completed, and the data transmission state is a data transmission incomplete state; if the number of transmitted bytes reaches the total number of data bytes, it indicates that the data transmission is completed, and the data transmission state is a data transmission completed state; and the communication between the I2C slave controller 100 and the host device 300 is controlled according to the data transmission state, wherein if the data transmission state is the data transmission completed state, the communication between the I2C slave controller 100 and the host device 300 is stopped; and if the data transmission state is the data transmission incomplete state, the communication between the I2C slave controller 100 and the host device 300 is continued; the master processor 32 is configured to continue reading or stop reading the communication data stored in the register 1 according to the data transmission state, or continue writing or stop writing the communication data into the register 1 according to the data transmission state, wherein in the case that the I2C slave controller 100 is receiving the communication data, if the data transmission state is the data transmission completed state, the reading of the communication data stored in the register 1 is stopped; and if the data transmission state is the data transmission incomplete state, the reading of the communication data stored in the register 1 is continued; in the case that the I2C slave controller 100 is transmitting the communication data, if the data transmission state is the data transmission completed state, the writing of the communication data into the register 1 is stopped; and if the data transmission state is the data transmission incomplete state, the writing of the communication data into the register 1 is continued.

[0055] In some embodiments, as shown in FIG. 1, the I2C slave controller 100 further comprises a state transmission module 7. Figure 2

[0056] The state transmission module 7 is connected with the processor 3, and the state transmission module 7 is configured to send a data transmission incomplete state to the host device 300 when the number of transmitted bytes recorded by the counting module 2 does not reach the total number of data bytes, and send a data transmission completed state to the host device 300 when the number of transmitted bytes recorded by the counting module 2 reaches the total number of data bytes. The hardware structure of the state transmission module is a register.

[0057] ​Exemplarily, the I2C slave controller 100 sets the total data bytes transmitted by the host device 300 to the I2C slave controller 100 in advance, based on which, when the I2C slave controller 100 is in the case of receiving communication data, the slave processor 31 of the I2C slave controller 100 judges according to the address information that the host device 300 needs to write the communication data into the I2C slave controller 100 corresponding to the address information, if so, the slave processor 31 pushes the communication data to the data receiving register 11 when receiving the communication data sent by the host device 300, the data receiving register 11 caches the data corresponding to the maximum storage bytes, then the counting module 2 records the transmitted bytes as the sum of the last recorded transmitted bytes and the maximum storage bytes, at this time, the counting module 2 judges whether the communication data is transmitted according to the transmitted bytes and the total data bytes of the byte configuration module 4, and transmits the information to the slave processor 31 and generates the corresponding data transmission state, the slave processor 31 forwards the data transmission state to the state transmission module 7, that is, when the transmitted bytes recorded by the counting module 2 does not reach the total data bytes, the state transmission module 7 sends the data transmission incomplete state to the master processor 32, the master processor 32 reads the communication data corresponding to the maximum storage bytes from the data receiving register 11 according to the data transmission incomplete state, at the same time, the slave processor 31 continues to transmit the communication data of the host device 300 to the data receiving register 11 according to the transmission incomplete state, and so on, when the transmitted bytes recorded by the counting module 2 reaches the total data bytes, the state transmission module 7 sends the data transmission complete state to the master processor 32, the master processor 32 stops reading the communication data from the data receiving register 11 according to the data transmission complete state, thereby, the data transmission between the host device 300 and the I2C slave controller 100 is terminated.

[0058] Alternatively, the I2C slave controller 100 sets the total data bytes to be transmitted by the I2C slave controller 100 to the host device 300 in advance, and based on this, when the I2C slave controller 100 is in the state of transmitting communication data, the slave processor 31 of the I2C slave controller 100 determines whether the host device 300 reads the communication data of the I2C slave controller 100 corresponding to the address information according to the address information, and if so, the master processor 32 of the I2C slave controller 100 delivers the communication data of the I2C slave controller 100 to the data transmission register 12, the data transmission register 12 caches the data corresponding to the maximum storage bytes of the data transmission register 12, and then the slave processor reads the communication data corresponding to the maximum storage bytes from the data transmission register 12 and pushes the communication data corresponding to the maximum storage bytes to the I2C bus, after the communication data is successfully pushed, the counting module 2 records the total transmitted bytes as the sum of the last recorded transmitted bytes and the maximum storage bytes, at this time, the counting module 2 determines whether the communication data is transmitted according to the total transmitted bytes and the total data bytes of the byte configuration module 4, and transmits the information to the slave processor 31 and generates the corresponding data transmission state, the slave processor 31 determines whether to continue to send communication data to the host device 300 according to the data transmission state, if the data transmission state is the data transmission incomplete state or the data transmission complete state, the slave processor 31 forwards the data transmission state to the state transmission module 7, and the state transmission module 7 sends the data transmission state to the master processor 32, that is, when the total transmitted bytes recorded by the counting module 2 does not reach the total data bytes, the state transmission module 7 sends the data transmission incomplete state to the master processor 32, the master processor 32 continues to write communication data to the data transmission register 12 according to the data transmission incomplete state, and the slave processor continues to transmit communication data to the host device 300 according to the data transmission incomplete state, and the cycle continues, when the total transmitted bytes recorded by the counting module 2 reaches the total data bytes, the state transmission module 7 sends the data transmission complete state to the master processor 32, the master processor 32 stops writing communication data to the data transmission register 12 according to the data transmission complete state, and the slave processor stops transmitting communication data to the host device 300 according to the data transmission complete state. Thus, the data transmission between the host device 300 and the I2C slave controller 100 is terminated.

[0059] Thus, the transmission of a large amount of data between the host device 300 and the I2C slave controller 100 is realized, thereby effectively solving the problem of byte transmission limitation of the I2C slave controller 100 during an I2C message due to cache limitation, improving data transmission efficiency, avoiding the complexity of software design, and reducing manufacturing cost.

[0060] Reference will now be made to Figure 4The I2C data receiving process from the controller according to an embodiment of the present invention is described below.

[0061] In step S1, the timing module feeds back the clock signal of the sampled I2C bus to the slave processor.

[0062] Step S2: The slave processor determines whether the host device writes communication data to the I2C slave controller corresponding to the address information based on the address information.

[0063] Step S3: The slave processor pushes the communication data sent by the host device to the data receive register.

[0064] Step S4: The counting module records the number of bytes transmitted.

[0065] In step S5, the counting module determines the data transmission result based on the number of bytes transmitted and the total number of bytes in the byte configuration module.

[0066] Step S6: The slave controller generates a data transmission status based on the data transmission result.

[0067] Step S7: The main controller reads the communication data in the data receiving register according to the data transmission status.

[0068] Step S8: The slave controller determines whether to transmit communication data to the data receiving register based on the data transmission status.

[0069] The following is for reference. Figure 5 The I2C slave controller data transmission process of this utility model embodiment is described in detail below.

[0070] In step S9, the timing module feeds back the clock signal and address information of the sampled I2C bus to the slave processor.

[0071] Step S10: The slave processor determines whether the host device should read the communication data of the I2C slave controller corresponding to the address information based on the address information.

[0072] In step S11, the slave processor pushes the I2C communication data from the controller buffered in the data transmission register to the host device.

[0073] Step S12: The counting module records the number of bytes transmitted.

[0074] In step S13, the counting module determines the data transmission result based on the number of bytes recorded as transmitted and the total number of bytes of data in the byte configuration module.

[0075] Step S14: The slave controller generates a data transmission status based on the data transmission result.

[0076] Step S15, the master controller determines whether to write the communication data into the data sending register according to the data transmission state.

[0077] Step S16, the slave controller determines whether to transmit the communication data to the host device according to the data transmission state.

[0078] Therefore, the number of transmitted bytes recorded by the counting module 2 in the application is used to determine whether the data transmission between the host device 300 and the I2C slave controller 100 is completed, and the data amount corresponding to the total number of transmitted bytes is used, so that on the basis of the limited cache of the I2C slave controller 100, the problem of byte transmission limitation of the I2C slave controller 100 during an I2C message caused by cache limitation can be effectively solved, the data transmission efficiency is improved, the complexity of software design is avoided, and the manufacturing cost is lower.

[0079] In some embodiments, the timing module is connected with the host device 300 through a clock line and a data line, the clock line is used to transmit the clock signal provided by the host device 300, and the data line is used to transmit the communication data sent by the host device 300.

[0080] The second aspect embodiment of the utility model provides a slave device 200, as shown in the figure, comprising the I2C slave controller 100 of the above embodiment. Figure 6

[0081] According to the slave device of the utility model, the I2C slave controller 100 of the above embodiment can effectively solve the problem of byte transmission limitation of the I2C slave controller 100 during an I2C message caused by cache limitation, avoid the complexity of software design, and lower the manufacturing cost.

[0082] The third aspect embodiment of the utility model provides an electronic control system 1000, as shown in the figure, the electronic control system 1000 comprises at least one slave device 200 and host device 300 of the above embodiment. Figure 7

[0083] Among them, the host device 300 is used for carrying out data transmission with the slave device.The party that initiates the operation actively is the host device 300, and the other party is the slave device.For the slave device, there are eeprom (Electrically Erasable Programmable read only memory), gyroscope and led (Light Emitting Diode) control chip and the like.

[0084] ​​According to the electronic control system, the slave equipment of the above embodiment can effectively solve the problem of byte transmission limitation of the I2C slave controller 100 during an I2C message caused by cache limitation, avoid the complexity of software design, and lower the manufacturing cost.

[0085] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the utility model. In the specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example.

[0086] Although the embodiments of the utility model have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the utility model, and the scope of the utility model is defined by the claims and their equivalents.

Claims

1. An I2C slave controller, characterized by, The I2C slave controller is used for data transmission with a host device, and comprises: a counting module, configured to record the number of transmitted bytes during an I2C message; a byte configuration module, configured to configure the total number of data bytes required for communication with the host device; a processor, connected with the counting module and the byte configuration module, configured to transmit communication data between the I2C slave controller and the host device until the number of transmitted bytes recorded by the counting module reaches the total number of data bytes.

2. The I2C slave controller according to claim 1, characterized in that, Further comprising: a register, connected with the processor, configured to store the communication data.

3. The I2C slave controller of claim 1, wherein, Further comprising: a timing module, connected with the processor, configured to manage the clock signal of the I2C slave controller during data transmission.

4. The I2C slave controller of claim 1, wherein, Further comprising: an address management module, connected with the processor, configured to configure address information of the I2C slave controller.

5. The I2C slave controller of claim 2, wherein, The register comprises: a data receiving register, connected with the processor, configured to buffer the communication data sent by the host device; a data sending register, connected with the processor, configured to buffer the communication data sent to the host device.

6. The I2C slave controller of claim 2, wherein, The processor comprises: a slave processor, configured to generate a data transmission state according to the number of transmitted bytes recorded by the counting module and the total number of data bytes, and control the communication between the I2C slave controller and the host device according to the data transmission state; a master processor, configured to continue reading or stop reading the communication data stored in the register according to the data transmission state, or continue writing or stop writing the communication data into the register according to the data transmission state.

7. The I2C slave controller according to claim 6, characterized in that, Further comprising: a state transmission module, connected with the processor, configured to send an unfinished data transmission state to the master processor when the number of transmitted bytes recorded by the counting module does not reach the total number of data bytes, and send a completed data transmission state to the master processor when the number of transmitted bytes recorded by the counting module reaches the total number of data bytes.

8. The I2C slave controller of claim 3, wherein, The timing module is connected with the host device through a clock line and a data line, the clock line is used for transmitting the clock signal provided by the host device, and the data line is used for transmitting the communication data sent by the host device.

9. A slave device, comprising: The I2C slave controller of any one of claims 1-8 is included.

10. An electronic control system characterized by, Further comprising: at least one slave device of claim 9; a host device, configured to perform data transmission with the slave device.

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