Low-voltage-drop large-current chip packaging structure
By introducing a thick copper redistribution metal layer and an etched frame into the FC-LGA package structure, the problems of increased current and high voltage drop in high-integration chip packaging are solved, realizing a chip packaging structure with low voltage drop and high current, which is suitable for high-density, high-speed large-scale integrated circuit chips.
Patent Information
- Application Number
- CN202423142967.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-19
AI Technical Summary
The existing FC-LGA packaging structure cannot meet the requirements of high current and low voltage drop in highly integrated chip packaging, especially at 7-nanometer or 5-nanometer process nodes, the packaging substrate cannot meet the requirements of increased total current and increased total power consumption.
A thick copper redistribution metal layer and an etched frame are used to replace the traditional ETS substrate. The thick copper redistribution metal layer is formed by multi-layer electroplating, which increases the effective area of the power and ground channels and reduces the thickness of the dielectric layer. At the same time, the etched frame is used to optimize the current carrying capacity, and the molding compound layer is only exposed on the back of the chip and the back of the frame.
A low-voltage-drop, high-current chip packaging structure has been achieved, which improves current carrying capacity and optimizes voltage drop, meeting the packaging requirements of high-density, high-speed, large-scale integrated circuit chips.
Smart Images
Figure CN223680121U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a low voltage drop large current chip packaging structure belongs to semiconductor packaging technical field. BACKGROUND
[0002] The current FC-LGA packaging (Flip Chip Land Grid Array, packaging format of flip chip land grid array packaging) is an advanced packaging technology that pastes the chip in the form of flip on the substrate. This packaging method inverts the chip and connects it to the packaging substrate (ETS substrate), and fixes the packaging to the substrate through the spherical solder points, referring to Figure 1 , the bare chip back, the chip packaging has high heat dissipation, large current, low voltage drop and the like, and is mainly used in the field of high-density, high-speed, multi-functional large-scale integrated circuit chip packaging. This packaging format, called flip chip land grid array, is also one of the main packaging formats of graphic acceleration chips.
[0003] With the improvement of the process node of the wafer, from the 14 nanometer process node to the more advanced 7 nanometer or 5 nanometer process, it means that the size of the packaged chip is further reduced, and the integration of the chip is higher and higher, resulting in an increase in the total current of the chip packaging structure, an increase in the total power consumption, and a higher requirement for the total voltage drop. The existing packaging substrate (ETS substrate) cannot meet the above packaging requirements. CONTENT OF THE UTILITY MODEL
[0004] In order to overcome the shortcomings of the existing packaging process, the utility model provides a low voltage drop large current chip packaging structure to meet market demand.
[0005] The technical scheme of the utility model is as follows:
[0006] The utility model provides a low voltage drop large current chip packaging structure, it includes chip monomer, the chip monomer includes chip monomer front and opposite chip monomer back, the chip monomer front is equipped with chip pad, it still includes etching frame and thick copper rewiring metal layer,
[0007] The thick copper rewiring metal layer includes a plurality of metal layers and a dielectric layer embedded between the metal layers, and the thickness of each layer of the metal layer is the superposition of the thickness of more than three electroplated metal layers.
[0008] The thick copper rewewire metal layer is arranged on the chip monomer front and fully covers the chip monomer front, one side of the thick copper rewiring metal layer is electrically connected with the chip pad of the chip monomer, and the other side of the thick copper rewiring metal layer is provided with a plurality of I / O interfaces, and the I / O interface is provided with a metal bump.
[0009] The etching frame includes an etching frame front and an opposite etching frame back,
[0010] The metal bumps are fixed with the base island and the pin of the front surface of the etching frame by solder respectively;
[0011] The plastic sealing material is used to seal the chip monomer, the etching frame and the thick copper re-routed metal layer as a whole to form a plastic sealing material layer, and the plastic sealing material layer only exposes the back surface of the chip monomer and the back surface of the etching frame.
[0012] As an implementable mode, the thickness of the metal layer of the thick copper re-routed metal layer is greater than or equal to 30 microns.
[0013] As an implementable mode, the dielectric layer of the thick copper re-routed metal layer is provided with a dielectric layer opening 231, and the metal layers adjacent to each other are electrically connected through the dielectric layer opening.
[0014] As an implementable mode, the size L of the dielectric layer opening is greater than or equal to 25 microns.
[0015] As an implementable mode, a passivation layer is arranged between the chip monomer and the thick copper re-routed metal layer.
[0016] As an implementable mode, the density of the metal bumps reaches a high-density level.
[0017] As an implementable mode, the base island is arranged at the center of the etching frame, and the pins are arranged around the base island.
[0018] Beneficial effects
[0019] The utility model discloses a low-voltage-drop large-current chip packaging structure, which uses a re-routed metal process to design a thick copper re-routed metal layer, and the multi-layer RDLs can be connected through a large-area copper plating mode, thereby increasing the effective area of the power supply ground channel, greatly reducing the thickness of the dielectric layer, and reducing the effective length of the power supply ground channel.
[0020] The etching frame in the lead frame is used to replace the ETS substrate, thereby greatly increasing the current flow capacity and optimizing the voltage drop. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 It is a schematic diagram of an existing FC-LGA packaging structure.
[0022] Figure 2 It is a sectional view of the low-voltage-drop large-current chip packaging structure of the utility model.
[0023] Figure 3 It is Figure 2 It is a front surface schematic diagram of the etching frame.
[0024] Figure 4 It isFigure 2 Schematic diagram of the back of the etching frame;
[0025] wherein,
[0026] Chip monomer 100
[0027] Chip monomer front 101
[0028] Chip monomer back 103
[0029] Metal bump 130
[0030] Solder layer 133
[0031] Thick copper re-wiring metal layer 200
[0032] Metal layer 210
[0033] Dielectric layer 230
[0034] Dielectric layer opening 231
[0035] Etching frame 300
[0036] Etching frame front 301
[0037] Etching frame back 303
[0038] Base island 310
[0039] Pin 330
[0040] Plastic sealing material layer 400. DETAILED DESCRIPTION
[0041] The application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related utility model, and not limited to the utility model. In addition, it should be noted that, for ease of description, only the parts related to the utility model are shown in the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0042] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific embodiments of the utility model will be described in detail below in conjunction with the drawings.
[0043] The utility model provides a kind of low-voltage drop large current chip packaging structure, such as Figures 2 to 4As shown, it comprises a chip monomer 100, an etching frame 300 and a thick copper redistribution metal layer 200. The chip monomer 100 comprises a chip monomer front surface 101 and an opposite chip monomer back surface 103, and the chip monomer front surface 101 is provided with chip pads. The metal layer thickness of the conventional redistribution metal layer is: 3 microns, 5 microns, 7 microns and 10 microns, which is relatively thin; and the dielectric layer thickness is within 10 microns.
[0044] The thick copper redistribution metal layer 200 of the utility model comprises a plurality of metal layers 210 and dielectric layers 230 embedded between the metal layers 210, and the dielectric layers 230 are provided with dielectric layer openings 231, and the upper and lower adjacent metal layers 210 are electrically connected through the dielectric layer openings 231. Figure 2 Each metal layer 210 of the thick copper redistribution metal layer 200 of the utility model is formed by multiple electroplating, and the metal layer 210 is formed by stacking three or more normal electroplating metal thicknesses. Generally, the thickness of the metal layer 210 is greater than or equal to 30 microns. The thickness of the dielectric layer 230 is the thickness of the normal redistribution metal layer, i.e. the thickness of the dielectric layer 230 is within 5-10 microns.
[0045] The thick copper redistribution metal layer 200 is arranged on the chip monomer front surface 101 and fully covers the front surface of the chip monomer 100. One side of the thick copper redistribution metal layer 200 is electrically connected through the chip pads of the chip monomer 100 (the chip pads are not shown in the figure). Between the chip monomer 100 and the thick copper redistribution metal layer 200, a passivation layer (the passivation layer is not shown in the figure) is further arranged. The other side of the thick copper redistribution metal layer 200 is provided with a plurality of I / O interfaces (the I / O interfaces are not shown in the figure), and the I / O interfaces are provided with metal bumps 130. With the improvement of the process node of the wafer, the density of the metal bumps 130 can reach a high density level, for example, the diameter of the commonly used cylindrical metal bump 13 can be reduced to 50 microns, and the minimum spacing can be reduced to 100 microns, which greatly improves the electrical properties of the metal bumps 130. Figure 2 Figure 2 Figure 2
[0046] The etching frame 300 is a process of a lead frame, and its characteristic is that it can make the required line shape according to the rules and requirements. For example, Figure 3 and Figure 4 As shown, the base island 310 and the lead 330 are processed from the same thickness of copper sheet, and the base island 310 and the lead 330 are located on the same etching frame 300. Generally, the base island 310 is located in the center of the etching frame 300, and the lead 330 is arranged around the base island 310.
[0047] The metal bumps 130 are respectively and vertically fixedly connected with the base island 310 and the lead 330 of the etching frame front surface 301 through solder,Figure 2 The middle solder forms a solder layer 133. One part of the metal bump 130 is in electrical connection with the base island 310 of the etching frame, and the other part of the metal bump 130 is in electrical connection with the pin 330 arranged on both sides or around the base island 310, as shown in Figure 3 and Figure 4 .
[0048] Figure 1 The ETS substrate in the prior art is a processing technology of a substrate, a layer of metal and a layer of dielectric layer or insulating layer are alternately stacked to form a multilayer circuit by electroplating, and the industry requires that the number of layers is more than three, and the total thickness of the dielectric layer is more than 25 microns.
[0049] The dielectric layer 230 of the utility model is preferably one layer or two layers, and the total thickness is within 10 microns, the dielectric layer thickness is greatly reduced, and the effective length of the power ground channel is reduced. At the same time, the size L of the dielectric layer opening 231 is greater than or equal to 25 microns, Figure 2 The 2 thick copper redistribution metal layers 200 shown in the utility model can be connected by a large-area copper plating mode, and the effective area of the power ground channel is increased. At the same time, the lead frame, the current capacity is greatly increased, and the pressure drop is optimized.
[0050] The utility model provides a kind of low-voltage drop large current chip packaging structure, further comprising plastic sealing material layer 400. Plastic sealing material integrally plastic seals chip monomer 100, etching frame 300 and thick copper redistribution metal layer 200, including the gap between metal bump 130 and the gap of etching frame 300. Only expose chip monomer back surface 103 and etching frame back surface 303, satisfy that chip packaging has high heat dissipation, large current, low voltage drop and the like characteristics.
[0051] The above is only the preferred specific embodiment of the utility model, but the protection scope of the utility model is not limited to this, any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the embodiment of the utility model, which should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be limited by the protection scope of claim.
Claims
1. A low-dropout high-current chip package structure comprising a chip monobloc (100) comprising a chip monobloc front face (101) and an opposite chip monobloc back face (103), the chip monobloc front face (101) being provided with chip pads, characterized in that, It also includes an etching frame (300) and a thick copper redistribution metal layer (200), the thick copper redistribution metal layer (200) includes several metal layers (210) and a medium layer (230) embedded between the metal layers (210), each layer of the metal layer (210) is more than three times the thickness of the electroplated metal layer; The thick copper redistribution metal layer (200) is arranged on the front surface (101) of the chip monomer, and fully covers the front surface (101) of the chip monomer, one side of the thick copper redistribution metal layer (200) is electrically connected with the chip pad of the chip monomer (100), and the other side of the thick copper redistribution metal layer (200) is provided with a plurality of I / O interfaces, and the I / O interface is provided with a metal bump (130); The etching frame (300) includes an etching frame front surface (301) and an opposite etching frame back surface (303), and the metal bump (130) is fixedly connected with the base island (310) and the pin (330) of the etching frame front surface (301) through solder respectively; It also includes plastic sealing material, the plastic sealing material seals the chip monomer (100), the etching frame (300) and the thick copper redistribution metal layer (200) as a whole to form a plastic sealing material layer (400), and the plastic sealing material layer (400) only exposes the chip monomer back surface (103) and the etching frame back surface (303).
2. The low-dropout high-current chip package structure of claim 1, wherein, The thickness of the metal layer (210) of the thick copper redistribution metal layer (200) is greater than or equal to 30 microns.
3. The low-dropout high-current chip package structure of claim 1, wherein, The chip monomer (100) and the thick copper redistribution metal layer (200) are provided with a passivation layer.
4. The low-dropout high-current chip package structure of any one of claims 1-3, wherein, The medium layer (230) of the thick copper redistribution metal layer (200) is provided with a medium layer opening (231), and the metal layer (210) adjacent to the upper and lower metal layers is electrically connected through the medium layer opening (231).
5. The low-dropout high-current chip package structure of claim 4, wherein, The size L of the medium layer opening (231) is greater than or equal to 25 microns.
6. The low-dropout high-current chip package structure of claim 1, wherein, The density of the metal bump (130) reaches a high density level.
7. The low-dropout high-current chip package structure of claim 1, wherein, The base island (310) is arranged at the center of the etching frame (300), and the pin (330) is arranged around the base island (310).