High electrostatic field effect transistor

Abstract

The utility model relates to the technical field of semiconductor devices, in particular to a high-electrostatic field effect transistor which comprises a semiconductor substrate, a source electrode and a drain electrode are arranged on the semiconductor substrate and located at different positions of the semiconductor substrate, a grid electrode is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are located at different positions of the semiconductor substrate. A plurality of gate oxide layers are arranged between the gate and the semiconductor substrate, the gate and the semiconductor substrate are isolated through the gate oxide layers, the gate oxide layers comprise at least two oxide layers, the oxide layer far away from the semiconductor substrate serves as an initial layer, and the oxide layer far away from the semiconductor substrate serves as a secondary layer. The thickness of each oxidation layer is increased layer by layer, at least one oxidation layer has the characteristics of high breakdown voltage and low leakage current, and the anti-static capacity of the semiconductor device is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a high electrostatic field effect transistor. BACKGROUND

[0002] As an important semiconductor device, field effect transistor (FET) is widely used in electronic components, integrated circuits and power electronic devices. With the continuous progress of electronic technology, the requirement of modern electronic products for electrostatic immunity is getting higher and higher. Electrostatic discharge (ESD) is a common source of electrical interference, which may cause irreversible damage to electronic components, especially to high-precision semiconductor devices, and electrostatic damage is particularly serious.

[0003] The existing FET device adopts a single-layer gate oxide layer to isolate the gate from the source / drain, but this structure often fails to effectively eliminate the influence of static electricity on the device when facing high-intensity static electricity. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the problem that the existing field effect transistor cannot effectively eliminate the influence of static electricity on the device when facing high-intensity static electricity, the present application provides a high electrostatic field effect transistor.

[0005] A high electrostatic field effect transistor comprises a semiconductor substrate, a source and a drain are arranged on the semiconductor substrate, the source and the drain are located at different positions of the semiconductor substrate, a gate is arranged between the source and the drain, a multi-layer gate oxide layer is arranged between the gate and the semiconductor substrate, the gate is isolated from the semiconductor substrate by the multi-layer gate oxide layer, the multi-layer gate oxide layer comprises at least two layers of oxide layers, and the oxide layer farthest from the semiconductor substrate is the starting layer, the thickness of each layer of oxide layers increases layer by layer, and at least one layer of oxide layers has higher breakdown voltage and lower leakage current characteristics.

[0006] Preferably, each layer of oxide layers of the multi-layer gate oxide layer is made of different materials.

[0007] Preferably, the multi-layer gate oxide layer comprises two layers of oxide layers, and the two layers of oxide layers are a silicon dioxide layer formed of silicon dioxide and a silicon nitride layer formed of silicon nitride, respectively.

[0008] Preferably, the multi-layer gate oxide layer comprises three layers of oxide layers, and the three layers of oxide layers are a silicon dioxide layer formed of silicon dioxide, a silicon nitride layer formed of silicon nitride and a titanium oxide layer formed of titanium oxide, respectively.

[0009] Preferably, the semiconductor is a P-type silicon substrate.

[0010] Preferably, the P-type silicon substrate is provided with symmetrical N-type regions at both ends of the upper surface, a first aluminum electrode and a second aluminum electrode are respectively arranged above the two N-type regions, the source electrode is arranged on the first aluminum electrode, the drain electrode is arranged on the second aluminum electrode, the multilayer gate oxide layer is arranged on the upper surface of the P-type silicon substrate and between the first aluminum electrode and the second aluminum electrode, a third aluminum electrode is arranged on the upper surface of the multilayer gate oxide layer, and the gate electrode is arranged on the third aluminum electrode.

[0011] Preferably, the fourth aluminum electrode is arranged on the lower surface of the semiconductor substrate, and a substrate lead wire is arranged on the fourth aluminum electrode.

[0012] The beneficial technical effects of the present application are as follows: the multilayer gate oxide layer can effectively increase the antistatic ability of the device. When a high-voltage static electric field acts on the device through the gate electrode, the multiple oxide layers can form a layer-by-layer voltage division effect, reducing the electric field strength of a single oxide layer and avoiding the occurrence of breakdown phenomenon. In addition, by selecting a high-breakdown-voltage material, the antistatic ability of the gate electrode can be further improved. After the multilayer gate oxide layer is adopted, the field effect transistor can maintain a stable working state in a high-voltage environment, effectively preventing electrostatic discharge from damaging the device, and improving the reliability and durability of the device in a complex environment. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A structure diagram of a high-static field effect transistor according to Embodiment 1.

[0014] Figure 2 A structure diagram of a high-static field effect transistor according to Embodiment 2.

[0015] The drawings show that: 1, semiconductor substrate; 2, N-type region; 3, first aluminum electrode; 4, second aluminum electrode; 5, source electrode; 6, drain electrode; 7, silicon dioxide layer; 8, silicon nitride layer; 9, third electrode; 10, gate electrode; 11, fourth aluminum electrode; 12, substrate lead wire; 13, titanium oxide layer. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0017] Embodiment 1

[0018] Reference Figure 1A high static field effect transistor, comprising a semiconductor substrate 1, the semiconductor substrate 1 is a P-type silicon substrate, symmetric N-type regions 2 are arranged on the upper surface of the semiconductor substrate 1, the N-type regions 2 are formed by diffusing or ion implanting an appropriate amount of N-type dopants (such as phosphorus or arsenic) into the P-type silicon semiconductor substrate 1, the P-type silicon substrate is a P-type silicon wafer, a first aluminum electrode 3 and a second aluminum electrode 4 are arranged above the N-type regions 2 respectively, a source 5 is arranged on the first aluminum electrode 3, a drain 6 is arranged on the second aluminum electrode 4, a multilayer gate oxide layer is arranged on the upper surface of the semiconductor substrate 1, and the multilayer gate oxide layer is between the first aluminum electrode 3 and the second aluminum electrode 4, a third aluminum electrode is arranged on the upper surface of the multilayer gate oxide layer, and a gate 10 is arranged on the third aluminum electrode, the multilayer gate oxide layer comprises two layers of oxide layers, the two layers of oxide layers are a silicon dioxide layer 7 formed by silicon dioxide and a silicon nitride layer 8 formed by silicon nitride, the silicon nitride layer 8 is close to the semiconductor substrate 1 and has a thickness of 50 nm, and the silicon dioxide layer 7 is away from the semiconductor substrate 1 and has a thickness of 20 nm.

[0019] With reference to Figure 1 Further, the first aluminum electrode 3 and the second aluminum electrode 4 are formed by sputtering aluminum from a target material to the surface of the semiconductor substrate 1 through ion bombardment, and the third aluminum electrode is formed by sputtering aluminum from a target material to the silicon dioxide layer 7 through ion bombardment, the aluminum electrode is a contact part of the source 5, the drain 6 and the gate 10 of the field effect transistor, in the field effect transistor, the source 5 is a place where current flows in, and the drain 6 is a place where current flows out. The role of the aluminum electrode is to provide a low-resistance contact area for the flow of electrons (or holes) in the field effect transistor and the transmission of current.

[0020] With reference to Figure 1 Further, a fourth aluminum electrode 11 is arranged on the lower surface of the semiconductor substrate 1, a substrate lead 12 is arranged on the fourth aluminum electrode 11, the fourth aluminum electrode 11 is also formed by sputtering aluminum from a target material to the surface of the semiconductor substrate 1 through ion bombardment, the substrate lead 12 is a copper-plated metal wire with good conductivity, and the fourth aluminum electrode 11 and the substrate lead 12 are connected with the ground wire of an external circuit to provide a stable reference voltage. At the same time, the aluminum electrode can also provide electrical isolation for the device to avoid interference of other electrodes or structures of the device by external electric field or noise.

[0021] Embodiment 2

[0022] With reference to Figure 2Example 2 differs from Example 1 in that the multi-layer gate oxide layer comprises three layers of oxide, namely a silicon dioxide layer 7 formed of silicon dioxide and a silicon nitride layer 8 and a titanium oxide layer 13 formed of silicon nitride and titanium oxide respectively, the titanium oxide layer 13 being proximate to the semiconductor substrate 1 and having a thickness of 70 nm, the silicon nitride layer 8 being above the titanium oxide layer 13 and having a thickness of 30 nm, and the silicon dioxide layer 7 being above the silicon nitride layer 8 and having a thickness of 15 nm.

[0023] The principle of Examples 1 and 2 is that by designing a multi-layer gate oxide layer, the anti-static capability of the device can be effectively increased. When a high-voltage static electric field acts on the device through the gate 10, the multiple layers of oxide can form the effect of layer-by-layer voltage division, reducing the electric field intensity of a single layer of oxide and avoiding the occurrence of breakdown phenomenon. In addition, by selecting a high-breakdown-voltage material, the anti-static capability of the gate 10 can be further improved. After the multi-layer gate oxide layer is adopted, the field effect transistor can maintain a stable working state in a high-voltage environment, effectively preventing electrostatic discharge from damaging the device, and improving the reliability and durability of the device in a complex environment.

[0024] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-static field effect transistor, characterized by: The semiconductor substrate is provided with a source and a drain at different positions of the semiconductor substrate, a gate is provided between the source and the drain, a multilayer gate oxide layer is provided between the gate and the semiconductor substrate, the gate is separated from the semiconductor substrate by the multilayer gate oxide layer, the multilayer gate oxide layer comprises at least two layers of oxide layers, and the oxide layer far from the semiconductor substrate is the starting layer, the thickness of each layer of the oxide layer increases layer by layer, and at least one layer of oxide layer has higher breakdown voltage and lower leakage current characteristics.

2. A high-gate field effect transistor according to claim 1, wherein: Each layer of the multilayer gate oxide layer is made of different materials.

3. A high-gate field effect transistor according to claim 2, wherein: The multilayer gate oxide layer comprises two layers of oxide layers, and the two layers of oxide layers are respectively a silicon dioxide layer formed of silicon dioxide and a silicon nitride layer formed of silicon nitride.

4. A high-gate field effect transistor according to claim 2, wherein: The multilayer gate oxide layer comprises three layers of oxide layers, and the three layers of oxide layers are respectively a silicon dioxide layer formed of silicon dioxide, a silicon nitride layer formed of silicon nitride, and a titanium oxide layer formed of titanium oxide.

5. A high electrostatic field-effect transistor according to claim 1, characterized in that: The semiconductor is a P-type silicon substrate.

6. A high-gate field effect transistor according to claim 5, wherein: The P-type silicon substrate is provided with symmetrical N-type regions at both ends of the upper surface, a first aluminum electrode and a second aluminum electrode are respectively provided above the two N-type regions, the source is provided on the first aluminum electrode, the drain is provided on the second aluminum electrode, the multilayer gate oxide layer is provided on the upper surface of the P-type silicon substrate and between the first aluminum electrode and the second aluminum electrode, a third aluminum electrode is provided on the upper surface of the multilayer gate oxide layer, and the gate is provided on the third aluminum electrode.

7. A high-gate field effect transistor according to claim 6, wherein: The lower surface of the semiconductor substrate is provided with a fourth aluminum electrode, and a substrate lead is provided on the fourth aluminum electrode.

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