BCD device
By introducing well regions and dielectric layer structures with opposite doping types into BCD devices, the hot carrier injection effect is reduced, the reliability of the devices is improved, and compatibility and cost-effectiveness with BCD processes are maintained.
Patent Information
- Application Number
- CN202423318230.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing BCD devices lack reliability under complex operating conditions, especially in terms of hot carrier injection (HCI) effect.
By introducing a first well region and a second well region with opposite doping types into the BCD device, and setting a first dielectric layer and a first gate electrode layer on the first well region, the third part of the first gate electrode layer is raised by the first dielectric layer, thereby reducing the surface electric field of the first well region and reducing the hot carrier injection effect.
It effectively reduces the hot carrier injection effect of BCD devices, improves device reliability, and the fabrication process is compatible with BCD technology, resulting in lower costs.
Smart Images
Figure CN223694221U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor technical field especially relates to a BCD device. BACKGROUND
[0002] BCD (Bipolar-CMOS-DMOS) process is a commonly used process for power integrated circuits. This process can integrate multiple different types of device structures on the same wafer through a production process, including resistors, capacitors, diodes, transistors, and various MOS devices, making power integrated circuit design more flexible, increasing integration, and significantly reducing costs.
[0003] The BCD device can include an LDMOS (Lateral Double Diffused MOS) structure. This structure is compatible with Bipolar and CMOS processes and has high voltage resistance and large current output capabilities, making it a very important device structure in BCD devices. To meet the increasingly complex working conditions and stringent verification, the reliability of the LDMOS structure must be further optimized. SUMMARY
[0004] The utility model discloses a BCD device for improving the reliability of the existing BCD device.
[0005] To achieve the above purpose, the utility model provides a BCD device, including:
[0006] The substrate is perpendicular to the first direction, and the second direction is perpendicular to the first direction.
[0007] The first well region and the second well region of opposite doping types extend downward from the substrate surface, and the first well region and the second well region are separated from each other in the second direction.
[0008] At least one ohmic contact region extends downward from the surface of the first well region.
[0009] The first dielectric layer is located on part of the first well region.
[0010] The first gate oxide layer is located outside the ohmic contact region and sequentially covers part of the top surface of the first well region, the substrate between the first well region and the second well region, and part of the top surface of the second well region. The second end of the first gate electrode layer is located on part of the top surface of the first well region, and the first gate oxide layer has a distance from the first dielectric layer in the second direction.
[0011] The first gate electrode layer comprises a first portion, a second portion and a third portion, the first portion is located on the first gate oxide layer, the third portion is located on the first dielectric layer, the second portion connects the first portion and the second portion, and the height of the third portion from the substrate surface in the first direction is greater than the height of the first portion from the substrate surface in the first direction.
[0012] Optionally, the first dielectric layer is located at least on the top surface of the first gate electrode layer and the top surface of the first well region.
[0013] Optionally, the semiconductor device further comprises:
[0014] The first isolation structure extends from the top surface of the substrate into the first well region, and the first dielectric layer is located on part of the top surface of the first isolation structure.
[0015] Optionally, the top surface of the first isolation structure is flush with the top surface of the substrate, or the top surface of the first isolation structure is higher than the top surface of the substrate.
[0016] Optionally, the first isolation structure is a field oxide layer or a trench isolation structure.
[0017] Optionally, the thickness of the first isolation structure is
[0018] Optionally, the first isolation structure has a first end portion and a second end portion, the first end portion of the first isolation structure is adjacent to the second end portion of the first gate electrode layer, the first dielectric layer is located on part of the first isolation structure between the first end portion of the first isolation structure and the second end portion of the first isolation structure, and the first gate electrode layer successively covers the top surface of the first gate oxide layer, the first dielectric layer and at least part of the top surface of the first dielectric layer.
[0019] Optionally, the first isolation structure has a first end portion and a second end portion, the first end portion of the first isolation structure is adjacent to the second end portion of the first gate electrode layer, the first dielectric layer extends from part of the first isolation structure between the first end portion of the first isolation structure and the second end portion of the first isolation structure to cover part of the top surface of the first gate oxide layer, and the first gate electrode layer covers the remaining top surface of the first gate oxide layer and at least part of the top surface of the first dielectric layer.
[0020] Optionally, the edge of the first dielectric layer is located within the edge of the first well region.
[0021] Optionally, the first isolation structure has a first end portion and a second end portion, the first end portion of the first isolation structure is adjacent to the second end portion of the first gate electrode layer, the first dielectric layer extends from a region between the first end portion of the first isolation structure and the second end portion of the first isolation structure to completely cover a top surface of the first gate oxide layer, and the first gate electrode layer covers at least a portion of a top surface of the first dielectric layer.
[0022] Optionally, the first dielectric layer covers a portion of a top surface of the first gate oxide layer, and the first gate electrode layer covers a remaining top surface of the first gate oxide layer and at least a portion of a top surface of the first dielectric layer.
[0023] Optionally, an edge of the first dielectric layer is located within an edge of the first well region.
[0024] Optionally, the first dielectric layer completely covers a top surface of the first gate oxide layer, and the first gate electrode layer covers at least a portion of a top surface of the first dielectric layer.
[0025] Optionally, the first dielectric layer is a nitride layer or the first dielectric layer is a stack of a nitride layer and an oxide layer.
[0026] Optionally, a thickness of the first dielectric layer is
[0027] Optionally, the ohmic contact region includes a first ohmic contact region, a second ohmic contact region, and a third ohmic contact region.
[0028] The first ohmic contact region and the second ohmic contact region extend from a top surface of the substrate into the second well region and abut each other, a doping type of the first ohmic contact region and the second well region is the same, a doping type of the second ohmic contact region is the same as that of the first well region, and the first ohmic contact region and the second ohmic contact region are located on one side of the first gate oxide layer.
[0029] The third ohmic contact region extends from the top surface of the substrate into the first well region, a doping type of the third ohmic contact region is the same as that of the first well region, and the third ohmic contact region is located on another side of the first gate oxide layer.
[0030] an insulating layer covering the first ohmic contact region, the second ohmic contact region, the first gate electrode layer, the third ohmic contact region, the first gate electrode layer and the first dielectric layer being located below the insulating layer, the insulating layer having openings leading to the first interconnection structure, the second interconnection structure, the third interconnection structure and the fourth interconnection structure, the first interconnection structure, the second interconnection structure and the third interconnection structure being respectively interconnected with the first ohmic contact region, the second ohmic contact region and the third ohmic contact region, and the fourth interconnection structure being interconnected with the first gate electrode layer.
[0031] Optionally, the semiconductor device further comprises:
[0032] a third well region extending from the top surface of the substrate into the substrate, the third well region having the same doping type as the second well region;
[0033] a second gate oxide layer covering a portion of the top surface of the third well region;
[0034] a second dielectric layer covering at least a portion of the top surface of the second gate oxide layer; and
[0035] a second gate electrode layer covering at least the second dielectric layer.
[0036] Optionally, the second dielectric layer covers an edge region of the top surface of the second gate oxide layer, and the second gate electrode layer covers the top surface of the second dielectric layer and a remaining region of the top surface of the second gate oxide layer.
[0037] Optionally, the second dielectric layer completely covers the top surface of the second gate oxide layer, and the second gate electrode layer completely covers the top surface of the second dielectric layer.
[0038] Optionally, the second dielectric layer is a nitride layer or a stack of a nitride layer and an oxide layer.
[0039] Optionally, the second dielectric layer has a thickness of 10-100 nm.
[0040] Optionally, the ohmic contact regions comprise a fourth ohmic contact region, a fifth ohmic contact region and a sixth ohmic contact region, the fourth ohmic contact region, the fifth ohmic contact region and the sixth ohmic contact region extending from the top surface of the substrate into the third well region, the fourth ohmic contact region and the fifth ohmic contact region being located on one side of the second gate oxide layer, the sixth ohmic contact region being located on the other side of the second gate oxide layer, the fourth ohmic contact region having the same doping type as the third well region, and the fifth ohmic contact region and the sixth ohmic contact region having opposite doping types to the third well region.
[0041] an insulating layer covering the fourth ohmic contact region, the fifth ohmic contact region, the second gate electrode layer and the sixth ohmic contact region, the second gate electrode layer and the second dielectric being under the insulating layer, the insulating layer having a fifth interconnection structure, a sixth interconnection structure, a seventh interconnection structure and an eighth interconnection structure therein, the fifth interconnection structure, the sixth interconnection structure and the seventh interconnection structure being interconnected with the fourth ohmic contact region, the fifth ohmic contact region and the sixth ohmic contact region respectively, the eighth interconnection structure being interconnected with the second gate electrode layer.
[0042] Optionally, further comprising:
[0043] a fourth well region extending from the top surface of the substrate into the substrate, the fourth well region being of the same doping type as the second well region;
[0044] a third gate oxide layer covering a portion of the top surface of the fourth well region;
[0045] a third dielectric layer covering the third gate oxide layer; and
[0046] a third gate electrode layer covering at least a portion of the top surface of the third dielectric layer.
[0047] Optionally, the third dielectric layer completely covers the top surface of the third gate oxide layer, and the third gate electrode layer completely covers the third dielectric layer.
[0048] Optionally, further comprising:
[0049] a second isolation structure and a third isolation structure extending from the top surface of the substrate into the fourth well region and being located on two sides of the third gate oxide layer respectively.
[0050] Optionally, the top surfaces of the second isolation structure and the third isolation structure are flush with the top surface of the substrate, or the top surfaces of the second isolation structure and the third isolation structure are higher than the top surface of the substrate.
[0051] Optionally, the second isolation structure and the third isolation structure are field oxide layers or trench isolation structures.
[0052] Optionally, the third dielectric layer is a nitride layer or a stack of a nitride layer and an oxide layer.
[0053] Optionally, the third dielectric layer has a thickness of 10-100 nm.
[0054] Optionally, the ohmic contact region comprises a seventh ohmic contact region and an eighth ohmic contact region, the seventh ohmic contact region and the eighth ohmic contact region extend from the top surface of the substrate into the fourth well region, the seventh ohmic contact region and the eighth ohmic contact region are located on two sides of the third gate oxide layer respectively, and the seventh ohmic contact region and the eighth ohmic contact region are of the same doping type as the fourth well region;
[0055] An insulating layer covers the seventh ohmic contact region, the third gate electrode layer and the eighth ohmic contact region, the third dielectric layer and the third gate oxide layer are below the insulating layer, the insulating layer has a ninth interconnection structure, a tenth interconnection structure and an eleventh interconnection structure, the ninth interconnection structure and the tenth interconnection structure are interconnected with the seventh ohmic contact region and the eighth ohmic contact region respectively, and the eleventh interconnection structure is interconnected with the third gate electrode layer.
[0056] Optionally, the working voltage of the BCD device is 45V-120V.
[0057] In the BCD device provided by the utility model, a substrate, a first well region and a second well region with opposite doping types, at least one ohmic contact region, a first dielectric layer on part of the first well region, a first gate oxide layer and a first gate electrode layer are included. The first gate oxide layer is located outside the ohmic contact region and successively covers part of the top surface of the first well region, the substrate between the first well region and the second well region and part of the top surface of the second well region, the second end of the first gate electrode layer is located on part of the top surface of the part of the first well region, and the first gate oxide layer and the first dielectric layer have a distance in the second direction. The first gate electrode layer comprises a first part, a second part and a third part, the first part is located on the first gate oxide layer, the third part is located on the first dielectric layer, the second part connects the first part and the second part, and the height of the third part from the substrate surface in the first direction is greater than the height of the first part from the substrate surface in the first direction. The third part of the first gate electrode layer is lifted by the first dielectric layer, so that the surface electric field of the first well region is reduced, the HCI (hot carrier injection) effect is reduced, the reliability of the BCD device is improved, the preparation of the first dielectric layer is compatible with the BCD process, and the preparation cost is also low. BRIEF DESCRIPTION OF DRAWINGS
[0058] Figure 1 The structure schematic diagram of the BCD device provided by the embodiment one of the utility model;
[0059] Figure 2 The structure schematic diagram of the BCD device provided by the embodiment two of the utility model;
[0060] Figure 3 A structure schematic diagram of a BCD device provided for the embodiment three of the present application is shown in FIG. 3;
[0061] Figure 4 A structure schematic diagram of a BCD device provided for the embodiment four of the present application is shown in FIG. 4;
[0062] Figure 5 A structure schematic diagram of a BCD device provided for the embodiment five of the present application is shown in FIG. 5;
[0063] Figure 6 A structure schematic diagram of a BCD device provided for the embodiment six of the present application is shown in FIG. 6;
[0064] Figure 7 A structure schematic diagram of a BCD device provided for the embodiment seven of the present application is shown in FIG. 7;
[0065] Figure 8 A structure schematic diagram of a BCD device provided for the embodiment eight of the present application is shown in FIG. 8;
[0066] Figure 9 A structure schematic diagram of a BCD device provided for the embodiment nine of the present application is shown in FIG. 9;
[0067] Figure 10 A structure schematic diagram of a BCD device provided for the embodiment ten of the present application is shown in FIG. 10;
[0068] Figure 11 A structure schematic diagram of a BCD device provided for the embodiment eleven of the present application is shown in FIG. 11;
[0069] Figure 12 A structure schematic diagram of a BCD device provided for the embodiment twelve of the present application is shown in FIG. 12;
[0070] Figure 13 A structure schematic diagram of a BCD device provided for the embodiment thirteen of the present application is shown in FIG. 13;
[0071] In the drawings, reference numerals:
[0072] 100 - Substrate; 101 - First well region; 111 - Third ohmic contact region; 102 - Second well region; 112 - First ohmic contact region; 122 - Second ohmic contact region; 103 - Third well region; 113 - Fourth ohmic contact region; 123 - Fifth ohmic contact region; 133 - Sixth ohmic contact region; 104 - Fourth well region; 114 - Seventh ohmic contact region; 115 - Eighth ohmic contact region; 210 - First isolation structure; 220 - Second isolation structure; 230 - Third isolation structure; 301 - First gate oxide layer; 302 - Second gate oxide layer; 303 - Third gate oxide layer; 4 01-First gate electrode layer; 402-Second gate electrode layer; 403-Third gate electrode layer; 501-First dielectric layer; 502-Second dielectric layer; 503-Third dielectric layer; 600-Insulating layer; 701-First interconnect structure; 702-Second interconnect structure; 703-Third interconnect structure; 704-Fourth interconnect structure; 705-Fifth interconnect structure; 706-Sixth interconnect structure; 707-Seventh interconnect structure; 708-Eighth interconnect structure; 709-Ninth interconnect structure; 710-Tenth interconnect structure; 711-Eleventh interconnect structure; A-First end; B-Second end. Detailed Implementation
[0073] The specific embodiments of this utility model will now be described in more detail with reference to the accompanying drawings. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.
[0074] Figure 1 This is a schematic diagram of the BCD device provided in this embodiment. Figure 1 As shown, the BCD device includes a substrate 100, a first well region 101, a second well region 102, at least one ohmic contact region, a first gate oxide layer 301, a first gate electrode layer 401, and a first dielectric layer 501. The first well region 101, the second well region 102, the first gate oxide layer 301, the first gate electrode layer 401, and the first dielectric layer 501 constitute an LDMOS structure.
[0075] Specifically, a first direction is perpendicular to the substrate 100, a second direction is perpendicular to the first direction, the first well region 101 and the second well region 102 are both located in the substrate 100 and both extend downward from a top surface of the substrate 100 into the substrate 100, and the first well region 101 and the second well region 102 are separated from each other in the second direction. In this embodiment, the first well region 101 and the second well region 102 have opposite doping types, i.e., the first well region 101 has a first doping type and the second well region 102 has a second doping type, and the first doping type and the second doping type can be N-type and P-type respectively or P-type and N-type respectively.
[0076] The ohmic contact region includes a first ohmic contact region 112 and a second ohmic contact region 122 arranged side by side in the second well region 102, and both the first ohmic contact region 112 and the second ohmic contact region 122 extend from the top surface of the substrate 100 into the second well region 102; the first well region 101 has a third ohmic contact region 111, and the third ohmic contact region 111 extends from the top surface of the substrate 100 into the first well region 101. In this embodiment, the first ohmic contact region 112 and the second well region 102 have the same doping type, the second ohmic contact region 122 and the first well region 101 have the same doping type, and the third ohmic contact region 111 and the first well region 101 have the same doping type, i.e., the first ohmic contact region 112 has the second doping type, the second ohmic contact region 122 and the third ohmic contact region 111 have the first doping type.
[0077] Further, the LDMOS structure also includes a first isolation structure 210, which is a field oxide layer in this embodiment. The first isolation structure 210 extends from the top surface of the substrate 100 into the first well region 101, and the top surface of the first isolation structure 210 is higher than the top surface of the first well region 101, so that the first well region 101 is separated from the second well region 102 in the second direction. Figure 1 As can be seen, the top surface of the first isolation structure 210 is higher than the top surface of the substrate 100. Of course, in some embodiments, for example, when the first isolation structure 210 is a trench isolation structure, the top surface of the first isolation structure 210 can be flush with the top surface of the substrate 100 or have a slight height difference.
[0078] The first isolation structure 210 has a first end A and a second end B, the first end A of the first isolation structure 210 is closer to the second well region 102 than the second end B, the first end A and the second end B of the first isolation structure 210 do not contact the edge of the first well region 101, but keep a distance from the edge of the first well region 101, that is, the edge of the first isolation structure 210 is located within the edge of the first well region 101, and the third ohmic contact region 111 is adjacent to the second end B. In this embodiment, the first end A and the second end B of the first isolation structure 210 are in a beak structure. The first end of the first isolation structure 210 is adjacent to the second end of the first gate electrode layer 401.
[0079] Optionally, the thickness of the first isolation structure 210 can be
[0080] Please continue to refer to Figure 1 The first gate oxide layer 301 is located on the substrate 100 between the first well region 101 and the second well region 102, specifically, it is located on the part of the top surface of the first well region 101, the substrate 100 between the first well region 101 and the second well region 102 and the part of the top surface of the second well region 102 successively and continuously covering the ohmic contact region. It can be seen from Figure 1 The first gate oxide layer 301 is located on the top surface of the substrate 100 between the second ohmic contact region 122 and the first end A. In this way, the first ohmic contact region 112 and the second ohmic contact region 122 are located on one side of the first gate oxide layer 301 and are adjacent to the first gate oxide layer 301, and the third ohmic contact region 111 is located on the other side of the first gate oxide layer 301 and is adjacent to the first isolation structure 210.
[0081] Further, the first dielectric layer 501 is located on part of the first well region 101, in this embodiment, specifically on part of the top surface of the first isolation structure 210, covering at least part of the top surface of the first well region 101, and the first dielectric layer 501 is located between the end of the first gate electrode layer 401 away from the second well region 102 and the top surface of the first well region 101 (i.e. the first dielectric layer 501 is sandwiched between the end of the first gate electrode layer 401 away from the second well region 102 and the top surface of the first well region 101), the second end of the first gate electrode layer 401 is located on part of the top surface of the part of the first well region 101, and the first gate oxide layer 301 and the first dielectric layer 501 have a distance in the second direction. In this embodiment, the first dielectric layer 501 is located on the area between the first end A and the second end B of the first isolation structure 210, specifically covering part of the top surface of the first isolation structure 210 (e.g. the central area). The first gate electrode layer 401 is located on the first gate oxide layer 301, the first isolation structure 210 and the first dielectric layer 501, specifically successively covering the top surface of the first gate oxide layer 301, part of the top surface of the first isolation structure 210 and at least part of the top surface of the first dielectric layer 501, i.e. the first gate electrode layer 401 extends from the first gate oxide layer 301 to the first dielectric layer 501.
[0082] The first dielectric layer 501 is located on at least the second end of the first gate electrode layer 401 and the top surface of the first well region 101.
[0083] The first gate electrode layer 401 comprises a first part, a second part and a third part, the first part is located on the first gate oxide layer 301, the third part is located on the first dielectric layer 501, the second part connects the first part and the second part, and the height of the third part from the surface of the substrate 100 in the first direction is greater than the height of the first part from the surface of the substrate 100 in the first direction. When the LDMOS structure is working, the third ohmic contact region 111 applies a high voltage, and the second ohmic contact region 122 applies a low voltage. In the on state of the LDMOS structure, the first well region 101 corresponding to the end of the first gate electrode layer 401 away from the second well region 102 introduces a high electric field on the surface of the first well region 101 directly below. The first dielectric layer 501 raises the third part of the first gate electrode layer 401, reduces the surface electric field of the partial region (the region covered by the first dielectric layer 501, that is, the electric field line concentration region or the electric field peak region) of the first well region 101, and further reduces the HCI (hot carrier injection) effect, thereby improving the reliability of the BCD device. Moreover, the preparation of the first dielectric layer 501 is compatible with the BCD process, and the preparation cost is also low.
[0084] In the embodiment, the thickness of the first dielectric layer 501 can be less than the thickness of the first isolation structure 210, and the lateral width of the first dielectric layer 501 can be less than the lateral width of the first isolation structure 210.
[0085] It should be noted that in the embodiment, the first gate electrode layer 401 only covers part of the top surface of the first dielectric layer 501, but it should not be limited thereto. In some embodiments, the first gate electrode layer 401 can also completely cover the top surface of the first dielectric layer 501, that is, the side wall of the first gate electrode layer 401 close to the second end B of the first isolation structure 210 can be flush with the side wall of the first dielectric layer 501 close to the second end B of the first isolation structure 210.
[0086] Optionally, the thickness of the first gate electrode layer 401 can be
[0087] Further, the material of the first dielectric layer 501 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric ability of the high-k material, the first dielectric layer 501 can effectively reduce the surface electric field of the first well region 101 under a smaller thickness. The first dielectric layer 501 can be a single-layer structure or a multi-layer structure. For example, the first dielectric layer 501 can be a nitride layer (such as a silicon nitride layer), or a nitride layer (such as a silicon nitride layer) and an oxide layer (such as a silicon oxide layer, the thickness is in the range of 1-10 nm). The nitride layer is preferably located above the oxide layer to avoid the problem of defects caused by stress mismatch between the nitride layer and silicon.
[0088] Further, the thickness of the first dielectric layer 501 can be But not limited to this.
[0089] Please continue to see Figure 1 The BCD device further comprises an insulating layer 600, which completely covers the substrate 100 and the LDMOS structure, covering the first ohmic contact region 112, the second ohmic contact region 122, the first gate electrode layer 401, and the third ohmic contact region 111, and the first gate electrode layer 401 and the first dielectric layer 501 are located below the insulating layer 600. The insulating layer 600 has openings leading to a first interconnection structure 701, a second interconnection structure 702, a third interconnection structure 703, and a fourth interconnection structure 704. The first interconnection structure 701, the second interconnection structure 702, and the third interconnection structure 703 are respectively interconnected with the first ohmic contact region 112, the second ohmic contact region 122, and the third ohmic contact region 111, and serve as the body, source, and drain of the LDMOS structure, respectively. The fourth interconnection structure 704 is interconnected with the first gate electrode layer 401, thereby serving as the gate of the LDMOS structure. The first interconnection structure 701, the second interconnection structure 702, the third interconnection structure 703, and the fourth interconnection structure 704 can each comprise an electrically connected plug and an interconnection metal layer. The plug is located within the insulating layer 600, and at least part of the top surface of the interconnection metal layer is exposed to the insulating layer 600.
[0090] Optionally, the BCD device can be applied to a driving integrated circuit for power supply and motor, and the working voltage thereof can be 45V-120V.
[0091] Based on this, the embodiment provides a preparation method of the BCD device, comprising the following steps:
[0092] Step S100, providing the substrate 100, ion implantation is performed on the substrate 100 to form the first well region 101, then high-temperature activation is performed on the first well region 101, and high-temperature push joint process is performed on the first well region 101;
[0093] Step S200, thermally growing an oxide layer on the top surface of the substrate 100, and then forming a hard mask layer on the oxide layer;
[0094] Step S300, forming a patterned photoresist layer on the hard mask layer, and etching the hard mask layer to expose part of the oxide layer;
[0095] Step S400, removing the patterned photoresist layer, and then using a furnace tube oxidation process to grow an oxide material on the exposed area of the oxide layer, thereby forming the first isolation structure 210;
[0096] Step S500, removing the hard mask layer, and performing ion implantation on the substrate 100 to form the second well region 102;
[0097] Step S600, etching the oxide layer, and growing the first gate oxide layer 301 at the corresponding position;
[0098] Step S700, forming the first dielectric layer 501 at the corresponding position;
[0099] Step S800, forming the first gate electrode layer 401 at the corresponding position;
[0100] Step S900, ion implantation to form the first ohmic contact region 112, the second ohmic contact region 122, and the third ohmic contact region 111, wherein the first ohmic contact region 112 has the second doping type, and the second ohmic contact region 122 and the third ohmic contact region 111 have the first doping type.
[0101] Step S100, forming the insulating layer 600, the first interconnection structure 701, the second interconnection structure 702, and the third interconnection structure 703.
[0102] Embodiment Two
[0103] Figure 2 A structure schematic diagram of a BCD device is provided for this embodiment. As shown in FIG. 2, the BCD device includes a substrate 100, a first well region 101, a second well region 102, a third well region 103, a first gate oxide layer 301, a first gate electrode layer 401, a first dielectric layer 501, a first gate structure 200, a first ohmic contact region 112, a second ohmic contact region 122, a third ohmic contact region 111, a first interconnection structure 701, a second interconnection structure 702, a third interconnection structure 703, and an insulating layer 600. Figure 2 As shown, the difference between this embodiment and embodiment one is that, in this embodiment, the first dielectric layer 501 extends from the region between the first end portion A and the second end portion B to cover the top surface of the first gate oxide layer 301, specifically the region between the top surface of the first isolation structure 210 and the edge of the first gate oxide layer 301. The first gate electrode layer 401 covers the remaining top surface of the first gate oxide layer 301 and at least part of the top surface of the first dielectric layer 501. In operation, the third ohmic contact region 111 applies a high voltage and the second ohmic contact region 122 applies a low voltage. In the on state of the LDMOS structure, the end of the first well region 101 away from the second well region 102 introduces a high electric field on the surface of the first well region 101 directly below it. In the off state of the LDMOS structure, the surface electric field is concentrated near the first end portion A. In this embodiment, the first dielectric layer 501 raises the end of the first gate electrode layer 401 and the portion covering the first end portion A, thereby reducing the surface electric field of part of the first well region 101 (the region covered by the first dielectric layer 501, i.e. the two electric field concentration regions or the electric field peak region), further reducing the HCI (hot carrier injection) effect, improving the reliability of the LDMOS structure, and further improving the reliability of the BCD device. Moreover, the preparation of the first dielectric layer 501 is compatible with the BCD process and has a relatively low preparation cost.
[0104] Embodiment three
[0105] Figure 3 The structure of the BCD device provided in this embodiment is shown in the figure. Figure 3 As shown, the difference between this embodiment and embodiment one is that, in this embodiment, the first dielectric layer 501 extends from the first isolation structure 200 between the first end portion A and the second end portion B to completely cover the top surface of the first gate oxide layer 301. The first gate electrode layer 401 is located above the first gate oxide layer 301 and covers at least part of the top surface of the first dielectric layer 501. Due to the electric field concentration at the first end portion A, the first dielectric layer 501 in this embodiment covers the first end portion A of the first isolation structure 200, thereby reducing the surface electric field near the first end portion A of the first well region 101, further improving the reliability of the LDMOS structure, and further improving the reliability of the BCD device. At the same time, since the first dielectric layer 501 completely covers the first gate oxide layer 301, the gate-source voltage resistance performance can be improved without changing the operating voltage of the LDMOS structure, thereby improving the reliability of the BCD device.
[0106] Embodiment four
[0107] Figure 4 A structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 5. As shown, the difference between the embodiment and the embodiment one is that, in the embodiment, the LDMOS structure omits the first isolation structure 210, so as to significantly improve the on efficiency of the LDMOS structure. Figure 4
[0108] Further, in the embodiment, the first gate oxide layer 301 extends from the edge of the second ohmic contact region 122 close to the first well region 101 to part of the first well region 101, the first dielectric layer 501 is located on part of the top surface of the first well region 101, specifically, covers part of the top surface of the first gate oxide layer 301, and the first gate electrode layer 401 covers the remaining top surface of the first gate oxide layer 301 and at least part of the top surface of the first dielectric layer 501. It can be understood that, compared with the LDMOS structure with the first isolation structure 210, the withstand voltage performance of the LDMOS structure without the first isolation structure 210 will decrease, and the first dielectric layer 501 in the embodiment can reduce the surface electric field of part of the first well region 101 (the region covered by the first dielectric layer 501, i.e. the electric field line concentration region or the electric field peak region), so as to improve the withstand voltage performance of the LDMOS structure.
[0109] Further, in the embodiment, the edge of the first dielectric layer 501 is located within the edge of the first well region 101, so the first dielectric layer 501 does not cover part of the corresponding channel region of the first gate oxide layer 301, so as not to affect the threshold voltage of the LDMOS structure.
[0110] Embodiment five
[0111] Figure 5 A structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 5. As shown, the difference between the embodiment and the embodiment one is that, in the embodiment, the LDMOS structure omits the first isolation structure 210, so as to significantly improve the on efficiency of the LDMOS structure. Figure 5
[0112] Further, in the embodiment, the first gate oxide layer 301 extends from the edge of the second ohmic contact region 122 close to the first well region 101 to part of the first well region 101, the first dielectric layer 501 completely covers the top surface of the first gate oxide layer 301, and the first gate electrode layer 401 is located on the first gate oxide layer 301 and covers at least part of the top surface of the first dielectric layer 501. It can be understood that, compared with the LDMOS structure with the first isolation structure 210, the LDMOS structure without the first isolation structure 210 has a lower voltage withstanding performance, and the first dielectric layer 501 in the embodiment can reduce the surface electric field of part of the first well region 101 (the region covered by the first dielectric layer 501, i.e., the region where the electric field lines are concentrated or the region where the electric field peaks), thereby improving the voltage withstanding performance of the LDMOS structure; at the same time, since the first dielectric layer 501 completely covers the first gate oxide layer 301, the voltage withstanding performance of the gate-source can be improved without changing the working voltage of the LDMOS structure, thereby improving the reliability of the BCD device.
[0113] Embodiment six
[0114] Figure 6 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 6. Figure 6 As shown in FIG. 6, the difference between the embodiment and the embodiment one is that, in the embodiment, the first isolation structure 210 is a trench isolation structure. Compared with the traditional field oxide layer isolation technology, the trench isolation structure occupies a smaller area, thereby improving the integration of the device, which makes it possible to integrate more circuit elements under the same device size, thereby improving the performance of the integrated circuit.
[0115] Embodiment seven
[0116] Figure 7 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 7. Figure 7 As shown in FIG. 7, the difference between the embodiment and the embodiment two is that, in the embodiment, the first isolation structure 210 is a trench isolation structure. Compared with the traditional field oxide layer isolation technology, the trench isolation structure occupies a smaller area, thereby improving the integration of the device, which makes it possible to integrate more circuit elements under the same device size, thereby improving the performance of the integrated circuit.
[0117] Embodiment eight
[0118] Figure 8 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 8. Figure 8As shown, the difference from Embodiment 3 is that in this embodiment, the first isolation structure 210 is a trench isolation structure. Compared with the traditional field oxide layer isolation technology, the trench isolation structure occupies a smaller area, thereby improving the integration of the device. This allows more circuit elements to be integrated under the same device size, thus improving the performance of the integrated circuit.
[0119] Example 9
[0120] Figure 9 This is a schematic diagram of the BCD device provided in this embodiment. Figure 9 As shown, the difference from Embodiment 1 is that in this embodiment, the BCD device further includes a field-MOS (field-metal-oxide-semiconductor transistor) structure, which includes a third well region 103, a second gate oxide layer 302, a second gate electrode layer 402, and a second dielectric layer 502.
[0121] Specifically, the third well region 103 is located within the substrate 100 and extends from the top surface of the substrate 100 into the substrate 100. In this embodiment, the third well region 103 has the same doping type as the second well region 102, that is, the third well region 103 has the second doping type.
[0122] The ohmic contact region includes a fourth ohmic contact region 113, a fifth ohmic contact region 123, and a sixth ohmic contact region 133 located within the third well region 103. All three regions extend from the top surface of the substrate 100 into the third well region 103. In this embodiment, the fourth ohmic contact region 113 has the same doping type as the third well region 103, while the fifth ohmic contact region 123 and the sixth ohmic contact region 133 have opposite doping types to the third well region 103. That is, the fourth ohmic contact region 113 has the second doping type, and the fifth ohmic contact region 123 and the sixth ohmic contact region 133 have the first doping type.
[0123] Please continue reading Figure 9 The second gate oxide layer 302 covers a portion of the top surface of the third well region 103, specifically covering the top surface of the third well region 103 between the fifth ohmic contact region 123 and the sixth ohmic contact region 133. In this way, the fourth ohmic contact region 113 and the fifth ohmic contact region 123 are adjacent to each other and located on one side of the second gate oxide layer 302, while the sixth ohmic contact region 133 is located on the other side of the second gate oxide layer 302.
[0124] Further, the second dielectric layer 502 is on the second gate oxide layer 302, and the second gate electrode layer 402 is on the second dielectric layer 502. In this embodiment, the second dielectric layer 502 only covers the edge region of the top surface of the second gate oxide layer 302, and the second gate electrode layer 402 covers the remaining region of the top surface of the second dielectric layer 502 and the second gate oxide layer 302. In operation, one of the fifth ohmic contact region 123 and the sixth ohmic contact region 133 applies a high voltage, and the other one applies a low voltage, and the surface electric field of the third well region 103 is high. The second dielectric layer 502 raises the edge region of the second gate electrode layer 402, thereby reducing the surface electric field of the third well region 103 (the region covered by the second dielectric layer 502, i.e. the region where the electric field concentration is likely to occur), improving the reliability of the field MOS structure, and further improving the reliability of the BCD device. The second dielectric layer 502 is compatible with the BCD process and has a low manufacturing cost.
[0125] Further, the material of the second dielectric layer 502 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric capability of the high-k material, the second dielectric layer 502 can effectively reduce the surface electric field of the third well region 103 at a small thickness. The second dielectric layer 502 can be a single-layer structure or a multi-layer structure. For example, the second dielectric layer 502 can be a nitride layer (e.g. a silicon nitride layer), or a stack of a nitride layer (e.g. a silicon nitride layer) and an oxide layer (e.g. a silicon oxide layer, with a thickness of 1-10 nm).
[0126] Further, the thickness of the second dielectric layer 502 can be 1-10 nm. However, the disclosure is not limited thereto.
[0127] Please continue to refer to Figure 9 The insulating layer 600 completely covers the field MOS structure, including the fourth ohmic contact region 113, the fifth ohmic contact region 123, the second gate electrode layer 302, and the sixth ohmic contact region 133. The second gate electrode layer 402 and the second dielectric layer 502 are located below the insulating layer 600. The insulating layer 600 also includes a fifth interconnect structure 705, a sixth interconnect structure 706, a seventh interconnect structure 707, and an eighth interconnect structure 708. The fifth interconnect structure 705, the sixth interconnect structure 706, and the seventh interconnect structure 707 are interconnected with the fourth ohmic contact region 113, the fifth ohmic contact region 123, and the sixth ohmic contact region 133, respectively, and serve as the body, source, and drain of the field MOS structure. The eighth interconnect structure 708 is interconnected with the second gate electrode layer 402, thereby serving as the gate of the field MOS structure. The fifth interconnect structure 705, the sixth interconnect structure 706, the seventh interconnect structure 707 and the eighth interconnect structure 708 may each include an electrically connected plug and an interconnect metal layer, the plug being located within the insulating layer 600, and at least a portion of the top surface of the interconnect metal layer exposing the insulating layer 600.
[0128] It should be noted that the LDMOS structure in this embodiment is not limited to the LDMOS structure in Embodiment 1, but can also be any of the LDMOS structures described in Embodiments 2 to 8.
[0129] Example 10
[0130] Figure 10 This is a schematic diagram of the BCD device provided in this embodiment. Figure 10 As shown, the difference from Embodiment Nine is that in this embodiment, the second dielectric layer 502 completely covers the top surface of the second gate oxide layer 302, and the second gate electrode layer 402 is located on the second gate oxide layer 302 and completely covers the top surface of the second dielectric layer 502. Since the second dielectric layer 502 completely covers the second gate oxide layer 302, the gate-source breakdown voltage can be improved without changing the operating voltage of the field MOS structure, thus improving the reliability of the BCD device.
[0131] It should be noted that the LDMOS structure in this embodiment is not limited to the LDMOS structure in Embodiment 1, but can also be any of the LDMOS structures described in Embodiments 2 to 8.
[0132] Example 11
[0133] Figure 11 This is a schematic diagram of the BCD device provided in this embodiment. Figure 11As shown, the difference between this embodiment and the embodiment one is that, in this embodiment, the BCD device further comprises a MOS capacitor structure. The MOS capacitor structure comprises a fourth well region 104, a third gate oxide layer 303, a third gate electrode layer 403, and a third dielectric layer 503.
[0134] Specifically, the fourth well region 104 is located in the substrate 100 and extends from the top surface of the substrate 100 into the substrate 100. In this embodiment, the fourth well region 104 has the same doping type as the second well region 102, i.e., the fourth well region 104 has the second doping type.
[0135] The ohmic contact region comprises a seventh ohmic contact region 114 and an eighth ohmic contact region 115 located in the fourth well region 104. The seventh ohmic contact region 114 and the eighth ohmic contact region 115 both extend from the top surface of the substrate 100 into the fourth well region 104, and the seventh ohmic contact region 114 and the eighth ohmic contact region 115 are at a distance from each other. In this embodiment, the seventh ohmic contact region 114 and the eighth ohmic contact region 115 have the same doping type as the fourth well region 104, i.e., the seventh ohmic contact region 114 and the eighth ohmic contact region 115 have the first doping type.
[0136] Further, the MOS capacitor structure further comprises a second isolation structure 220 and a third isolation structure 230. In this embodiment, the second isolation structure 220 and the third isolation structure 230 are both field oxide layers. The second isolation structure 220 and the third isolation structure 230 extend from the top surface of the substrate 100 into the fourth well region 104, and the second isolation structure 220 and the third isolation structure 230 further extend upward to be higher than the top surface of the fourth well region 104, so that the second isolation structure 220 and the third isolation structure 230 are located between the seventh ohmic contact region 114 and the eighth ohmic contact region 115. Figure 11 As can be seen, the top surfaces of the second isolation structure 220 and the third isolation structure 230 are higher than the top surface of the substrate 100. In some embodiments, the top surfaces of the second isolation structure 220 and the third isolation structure 230 can also be flush with the top surface of the substrate 100.
[0137] The second isolation structure 220 and the third isolation structure 230 are both located between the seventh ohmic contact region 114 and the eighth ohmic contact region 115; at the same time, the second isolation structure 220 and the third isolation structure 230 are not in contact but at a distance. In this embodiment, the end portions of the second isolation structure 220 and the third isolation structure 230 have a beak structure.
[0138] Please continue to refer to Figure 11The third gate oxide layer 303 is located on a part of the top surface of the fourth well region 104, between the second isolation structure 220 and the third isolation structure 230, and covers the top surface of the fourth well region 104 between the second isolation structure 220 and the third isolation structure 230. In this way, the seventh ohmic contact region 114 and the eighth ohmic contact region 115 are located on both sides of the third gate oxide layer 303, and the seventh ohmic contact region 114 is isolated from the third gate oxide layer 303 by the second isolation structure 220, and the eighth ohmic contact region 115 is isolated from the third gate oxide layer 303 by the third isolation structure 230.
[0139] Further, the third dielectric layer 503 covers the third gate oxide layer 303, and the third gate electrode layer 403 covers at least a part of the top surface of the third dielectric layer 503. In this embodiment, the third dielectric layer 503 completely covers the top surface of the third gate oxide layer 303, and the third gate electrode layer 403 completely covers the top surface of the third dielectric layer 503. The third dielectric layer 503 can improve the voltage resistance performance of the MOS capacitor structure, and ensure that it still has a relatively high capacitance, thereby improving the reliability of the BCD device. The third dielectric layer 503 is compatible with the BCD process, and has a relatively low preparation cost.
[0140] Further, the material of the third dielectric layer 503 can be a high-k material, such as silicon nitride, metal oxide, etc. By using the high dielectric capability of the high-k material, the third dielectric layer 503 can effectively improve the voltage resistance performance of the MOS capacitor structure at a relatively small thickness. The third dielectric layer 503 can be a single-layer structure, or a multi-layer structure. For example, the third dielectric layer 503 can be a nitride layer (such as a silicon nitride layer), or a stack of a nitride layer (such as a silicon nitride layer) and an oxide layer (such as a silicon oxide layer, with a thickness of 1-10 nm).
[0141] Further, the thickness of the third dielectric layer 503 can be 1-10 nm. But it should not be limited thereto.
[0142] Please continue to refer to Figure 11 The insulating layer 600 also completely covers the MOS capacitor structure, covering the seventh ohmic contact 114, the third gate electrode layer 403 and the eighth ohmic contact region 115, and the third dielectric layer 503 and the third gate oxide layer 303 are below the insulating layer 600. The insulating layer 600 also has a ninth interconnection structure 709, a tenth interconnection structure 710 and an eleventh interconnection structure 711, the ninth interconnection structure 709 and the tenth interconnection structure 710 are respectively interconnected with the seventh ohmic contact region 114 and the eighth ohmic contact region 115, and the eleventh interconnection structure 711 is interconnected with the third gate electrode layer 403. The third gate electrode layer 403 and the substrate 100 serve as the plate of the MOS capacitor structure, the third gate oxide layer 303 serves as the dielectric layer of the MOS capacitor structure, and the ninth interconnection structure 709, the tenth interconnection structure 710 and the eleventh interconnection structure 711 serve as connection and conduction. The voltage applied to the third gate electrode layer 403 and the substrate 100 can control the flow of carriers in the channel in the substrate 100, thereby inducing charges in the semiconductor to form an inversion layer. The ninth interconnection structure 709, the tenth interconnection structure 710 and the eleventh interconnection structure 711 can each include an electrically connected plug and an interconnection metal layer, the plug being located in the insulating layer 600, and at least part of the top surface of the interconnection metal layer being exposed from the insulating layer 600.
[0143] It should be noted that the LDMOS structure in the embodiment is not limited to the LDMOS structure in Embodiment One, but can also be any one of the LDMOS structures in Embodiments Two to Eight.
[0144] Embodiment Twelve
[0145] Figure 12 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 12. Figure 12 As shown, the difference between the embodiment and Embodiment Eleven is that in the embodiment, the second isolation structure 220 and the third isolation structure 230 are both trench isolation structures.
[0146] Embodiment Thirteen
[0147] Figure 13 The structure schematic diagram of the BCD device provided in the embodiment is shown in FIG. 13. Figure 13 As shown, the difference between the embodiment and Embodiment One is that in the embodiment, the BCD device simultaneously includes the LDMOS structure, the field MOS structure and the MOS capacitor structure.
[0148] The LDMOS structure in the embodiment is the LDMOS structure in Embodiment 1, the field MOS structure is the field MOS structure in Embodiment 9, and the MOS capacitor structure is the MOS capacitor structure in Embodiment 11. However, it should be understood that the LDMOS structure in the embodiment is not limited to the LDMOS structure in Embodiment 1, and the LDMOS structure in the embodiment can also be any one of the LDMOS structures in Embodiments 2 to 8, the field MOS structure can also be the field MOS structure in Embodiment 10, and the MOS capacitor structure can also be the MOS capacitor structure in Embodiment 12, which will not be described one by one here.
[0149] In conclusion, in the BCD device provided in the embodiment of the present application, the BCD device comprises a substrate, a first well region and a second well region with opposite doping types, at least one ohmic contact region, a first dielectric layer located on part of the first well region, a first gate oxide layer, and a first gate electrode layer. The first gate oxide layer is located outside the ohmic contact region and successively covers part of the top surface of the first well region, the substrate between the first well region and the second well region, and part of the top surface of the second well region. The second end of the first gate electrode layer is located on part of the top surface of the first well region. The first gate oxide layer and the first dielectric layer have a distance in the second direction. The first gate electrode layer comprises a first part, a second part, and a third part. The first part is located on the first gate oxide layer, the third part is located on the first dielectric layer, the second part connects the first part and the second part, and the height of the third part from the substrate surface in the first direction is greater than the height of the first part from the substrate surface in the first direction. The present application uses the first dielectric layer to raise the third part of the first gate electrode layer, thereby reducing the surface electric field of the first well region, further reducing the HCI (hot carrier injection) effect, and improving the reliability of the BCD device. Moreover, the preparation of the first dielectric layer is compatible with the BCD process, and the preparation cost is also relatively low.
[0150] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiments, the description is relatively simple because it corresponds to the method disclosed in the embodiments. The relevant parts can be referred to the description of the method.
[0151] It should also be noted that, although the utility model has disclosed as above with preferred embodiments, the above embodiments are not used to limit the utility model. For any skilled person in the art, without departing from the scope of the utility model technical scheme, the above disclosed technical content can be used to make many possible changes and modifications to the utility model technical scheme, or modified as equivalent examples of equivalent changes. Therefore, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the utility model, which does not deviate from the content of the utility model technical scheme, still belongs to the scope of the utility model technical scheme protection.
[0152] It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the specification are merely used to distinguish different components, elements, steps and the like in the specification, and are not used to represent the logical relationship or sequence relationship between the components, elements, steps and the like.
[0153] In addition, it should be recognized that the terms described herein are used only to describe particular embodiments and not to limit the scope of the utility model. It must be noted that the singular forms "a", "an", and "the" used herein include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "a means" means reference to one or more steps or means and can include sub-steps and sub-means. All conjunctions used herein should be interpreted in the broadest possible sense. In addition, the word "or" should be interpreted as having the logical "or" definition rather than the logical "exclusive or" definition, unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the utility model can include manually, automatically or a combination of performing selected tasks.
Claims
1. A BCD device, characterized by, The application relates to a semiconductor device, comprising: a substrate, a first direction being perpendicular to the substrate, a second direction being perpendicular to the first direction; a first well region and a second well region having opposite doping types, the first well region and the second well region extending downward from a surface of the substrate, the first well region and the second well region being separated from each other in the second direction; at least one ohmic contact region extending downward from a surface of the first well region; a first dielectric layer located on a portion of the first well region; a first gate oxide layer located on a portion of a top surface of the first well region, a portion of a top surface of the second well region, and a portion of a top surface of the substrate between the first well region and the second well region, a second end portion of a first gate electrode layer being located on the portion of the top surface of the first well region, the first gate oxide layer having a distance from the first dielectric layer in the second direction; and the first gate electrode layer comprising a first portion, a second portion and a third portion, the first portion being located on the first gate oxide layer, the third portion being located on the first dielectric layer, the second portion connecting the first portion and the second portion, the third portion having a height from the surface of the substrate in the first direction greater than a height of the first portion from the surface of the substrate in the first direction.
2. The BCD device of claim 1, wherein, the first dielectric layer being located on at least a portion of the second end portion of the first gate electrode layer and a portion of the top surface of the first well region.
3. The BCD device of claim 1 or 2, wherein, Further comprising: a first isolation structure extending from a top surface of the substrate into the first well region, the first dielectric layer being located on a portion of a top surface of the first isolation structure.
4. The BCD device of claim 3, wherein, the top surface of the first isolation structure being flush with the top surface of the substrate, or the top surface of the first isolation structure being higher than the top surface of the substrate.
5. The BCD device of claim 3, wherein, the first isolation structure being a field oxide layer or a trench isolation structure.
6. The BCD device of claim 3, wherein, a thickness of the first isolation structure is 7. The BCD device of claim 3, wherein, the first isolation structure having a first end portion and a second end portion, the first end portion of the first isolation structure being adjacent to the second end portion of the first gate electrode layer, the first dielectric layer being located on a portion of the first isolation structure between the first end portion of the first isolation structure and the second end portion of the first isolation structure, the first gate electrode layer sequentially and continuously covering a top surface of the first gate oxide layer, the first dielectric layer, and at least a portion of a top surface of the first dielectric layer and the first gate oxide layer between the first isolation structure and the first dielectric layer.
8. The BCD device of claim 3, wherein, the first isolation structure having a first end portion and a second end portion, the first end portion of the first isolation structure being adjacent to the second end portion of the first gate electrode layer, the first dielectric layer extending from a portion of the first isolation structure between the first end portion of the first isolation structure and the second end portion of the first isolation structure to cover a portion of a top surface of the first gate oxide layer, the first gate electrode layer covering a remaining top surface of the first gate oxide layer and at least a portion of a top surface of the first dielectric layer.
9. The BCD device of claim 8, wherein, an edge of the first dielectric layer being located within an edge of the first well region.
10. The BCD device of claim 3, wherein, The first isolation structure has a first end and a second end, the first end of the first isolation structure is adjacent to the second end of the first gate electrode layer, the first dielectric layer extends from a region between the first end of the first isolation structure and the second end of the first isolation structure to completely cover the top surface of the first gate oxide layer, and the first gate electrode layer covers at least part of the top surface of the first dielectric layer.
11. The BCD device of claim 2, wherein, The first dielectric layer covers part of the top surface of the first gate oxide layer, and the first gate electrode layer covers the remaining top surface of the first gate oxide layer and at least part of the top surface of the first dielectric layer.
12. The BCD device of claim 11, wherein, An edge of the first dielectric layer is located within an edge of the first well region.
13. The BCD device of claim 2, wherein, The first dielectric layer completely covers the top surface of the first gate oxide layer, and the first gate electrode layer covers at least part of the top surface of the first dielectric layer.
14. The BCD device of claim 1, wherein, The first dielectric layer is a nitride layer or a stack of a nitride layer and an oxide layer.
15. The BCD device of claim 1 or 14, wherein, the thickness of the first dielectric layer is 16. The BCD device of claim 1, wherein, The ohmic contact region includes a first ohmic contact region, a second ohmic contact region, and a third ohmic contact region; The first ohmic contact region and the second ohmic contact region extend from the top surface of the substrate into the second well region and abut each other, the first ohmic contact region and the second well region are of the same doping type, the second ohmic contact region is of the same doping type as the first well region, and the first ohmic contact region and the second ohmic contact region are located on one side of the first gate oxide layer; The third ohmic contact region extends from the top surface of the substrate into the first well region, the third ohmic contact region is of the same doping type as the first well region, and the third ohmic contact region is located on the other side of the first gate oxide layer; An insulating layer covers the first ohmic contact region, the second ohmic contact region, the first gate electrode layer, and the third ohmic contact region, the first gate electrode layer and the first dielectric layer are located below the insulating layer, and openings are formed in the insulating layer to lead out a first interconnection structure, a second interconnection structure, a third interconnection structure, and a fourth interconnection structure, the first interconnection structure, the second interconnection structure, and the third interconnection structure are respectively interconnected with the first ohmic contact region, the second ohmic contact region, and the third ohmic contact region, and the fourth interconnection structure is interconnected with the first gate electrode layer.
17. The BCD device of claim 1, wherein, Further comprising: A third well region extending from the top surface of the substrate into the substrate, the third well region being of the same doping type as the second well region; A second gate oxide layer covering part of the top surface of the third well region; A second dielectric layer covering at least part of the top surface of the second gate oxide layer; And A second gate electrode layer covering at least the second dielectric layer.
18. The BCD device of claim 17, wherein, The second dielectric layer covers an edge region of the top surface of the second gate oxide layer, and the second gate electrode layer covers the top surface of the second dielectric layer and the remaining region of the top surface of the second gate oxide layer.
19. The BCD device of claim 17, wherein, The second dielectric layer completely covers the top surface of the second gate oxide layer, and the second gate electrode layer completely covers the top surface of the second dielectric layer.
20. The BCD device of any of claims 17-19, wherein, The second dielectric layer is a nitride layer or a stack of a nitride layer and an oxide layer.
21. The BCD device of any of claims 17-19, wherein, the thickness of the second dielectric layer is 22. The BCD device of any of claims 17-19, wherein, The ohmic contact region includes a fourth ohmic contact region, a fifth ohmic contact region and a sixth ohmic contact region, the fourth ohmic contact region, the fifth ohmic contact region and the sixth ohmic contact region extend from the top surface of the substrate into the third well region, the fourth ohmic contact region and the fifth ohmic contact region are located on one side of the second gate oxide layer, the sixth ohmic contact region is located on the other side of the second gate oxide layer, the fourth ohmic contact region is of the same doping type as the third well region, the fifth ohmic contact region and the sixth ohmic contact region are of the opposite doping type as the third well region; An insulating layer covers the fourth ohmic contact region, the fifth ohmic contact region, the second gate electrode layer and the sixth ohmic contact region, the second gate electrode layer and the second dielectric layer are below the insulating layer, the insulating layer has a fifth interconnection structure, a sixth interconnection structure, a seventh interconnection structure and an eighth interconnection structure therein, the fifth interconnection structure, the sixth interconnection structure and the seventh interconnection structure are respectively interconnected with the fourth ohmic contact region, the fifth ohmic contact region and the sixth ohmic contact region, and the eighth interconnection structure is interconnected with the second gate electrode layer.
23. The BCD device of claim 1 or 17, wherein, Further comprising: A fourth well region extending from the top surface of the substrate into the substrate, the fourth well region is of the same doping type as the second well region; A third gate oxide layer covering part of the top surface of the fourth well region; A third dielectric layer covering the third gate oxide layer; And A third gate electrode layer covering at least part of the top surface of the third dielectric layer.
24. The BCD device of claim 23, wherein, The third dielectric layer completely covers the top surface of the third gate oxide layer, and the third gate electrode layer completely covers the top surface of the third dielectric layer.
25. The BCD device of claim 23, wherein, Further comprising: A second isolation structure and a third isolation structure extending from the top surface of the substrate into the fourth well region and located on both sides of the third gate oxide layer respectively.
26. The BCD device of claim 25, wherein, The top surface of the second isolation structure and the third isolation structure is flush with the top surface of the substrate, or the top surface of the second isolation structure and the third isolation structure is higher than the top surface of the substrate.
27. The BCD device of claim 25, wherein, The second isolation structure and the third isolation structure are field oxide layers or trench isolation structures.
28. The BCD device of claim 23, wherein, The third dielectric layer is a nitride layer or a stack of a nitride layer and an oxide layer.
29. The BCD device of claim 23, wherein, the third dielectric layer has a thickness of 30. The BCD device of claim 23, wherein, The ohmic contact region includes a seventh ohmic contact region and an eighth ohmic contact region, the seventh ohmic contact region and the eighth ohmic contact region extend from the top surface of the substrate into the fourth well region, the seventh ohmic contact region and the eighth ohmic contact region are respectively located on both sides of the third gate oxide layer, and the seventh ohmic contact region and the eighth ohmic contact region are of the same doping type as the fourth well region; An insulating layer covers the seventh ohmic contact region, the third gate electrode layer and the eighth ohmic contact region, the third dielectric layer and the third gate oxide layer are below the insulating layer, the insulating layer has a ninth interconnection structure, a tenth interconnection structure and an eleventh interconnection structure therein, the ninth interconnection structure and the tenth interconnection structure are respectively interconnected with the seventh ohmic contact region and the eighth ohmic contact region, and the eleventh interconnection structure is interconnected with the third gate electrode layer.
31. The BCD device of claim 1, wherein, The BCD device has an operating voltage of 45V to 120V.