Interface integrated circuit and interface integrated equipment

Abstract

The utility model relates to the technical field of interface equipment, and discloses an interface integrated circuit and interface integrated equipment. The interface integrated circuit comprises a processor, a plurality of display interfaces, a plurality of serial communication interfaces, a first display signal conversion chip, a second display signal conversion chip, a serial signal conversion chip, a first LPC signal conversion chip, a second LPC signal conversion chip, a first interface chip, a second interface chip and a third interface chip. The plurality of display interfaces comprise an HDMI interface, an LVDS interface, a VGA interface and a DP interface or an EDP interface; the processor is connected with the LVDS interface through the first display signal conversion chip, and the processor is connected with the VGA interface through the second display signal conversion chip; and the serial signal conversion chip is connected with a plurality of serial communication interfaces through the first LPC signal conversion chip, the first interface chip and the second interface chip. According to the utility model, a plurality of serial communication interfaces and a plurality of display interfaces can be integrated.

Description

TECHNICAL FIELD

[0001] The utility model relates to interface equipment technical field, concretely relates to an interface integrated circuit and interface integrated equipment. BACKGROUND

[0002] Based on the user's use demand, easy usability and cost and other factors, the host equipment on the market usually only contains single display interface, and is connected with a display or other equipment. However, in some specific scenarios (such as ticket system, live equipment, etc.), the single display interface is prone to have the shortcomings of limited data transmission speed, too large dependence on external equipment, large space occupation, complex wiring, high maintenance and management cost, etc. CONTENT OF THE UTILITY MODEL

[0003] Therefore, the utility model provides an interface integrated circuit and interface integrated equipment to improve the problems of single display interface, such as limited data transmission speed, too large dependence on external equipment, large space occupation, complex wiring, high maintenance and management cost, etc.

[0004] The utility model provides an interface integrated circuit, interface integrated circuit includes processor, a plurality of display interfaces, a plurality of serial communication interfaces, first display signal conversion chip, second display signal conversion chip, serial signal conversion chip, first LPC signal conversion chip, second LPC signal conversion chip, first interface chip, second interface chip and third interface chip, a plurality of display interfaces include HDMI interface, LVDS interface and VGA interface and DP interface or EDP interface, and each serial communication interface includes RS232 interface, RS422 interface and RS485 interface, the first end of processor connects HDMI interface, the second end of processor connects DP interface or EDP interface, and the third end of processor is connected with LVDS interface through first display signal conversion chip, and the fourth end of processor is connected with VGA interface through second display signal conversion chip, the fifth end of processor is connected with the first end of serial signal conversion chip, and the second end of serial signal conversion chip is connected with a plurality of serial communication interfaces through first LPC signal conversion chip, first interface chip and second interface chip, and the third end of serial signal conversion chip is connected with the first end of second LPC signal conversion chip, and the second end of second LPC signal conversion chip is connected with a plurality of serial communication interfaces through third interface chip, and the third end of second LPC signal conversion chip is connected with a plurality of serial communication interfaces through first interface chip and second interface chip, wherein first display signal conversion chip is used to convert the EDP signal of the third end output of processor and the LVDS signal of LVDS interface adaptation, and second display signal conversion chip is used to convert the DDI signal of the fourth end output of processor and the VGA signal of VGA interface adaptation, serial signal conversion chip is used to convert the ESPI signal of the fifth end output of processor and LPC signal, first LPC signal conversion chip and second LPC signal conversion chip are used to convert the received LPC signal and UART signal, and first interface chip, second interface chip and third interface chip are used to switch the RS232 interface, RS422 interface and RS485 interface.

[0005] In the embodiment, by setting the first display signal conversion chip, the second display signal conversion chip, the serial signal conversion chip, the first LPC signal conversion chip, the second LPC signal conversion chip, the first interface chip, the second interface chip and the third interface chip, the processor can be integrated with the plurality of display interfaces and the plurality of serial communication interfaces.

[0006] (1) High connectivity and flexibility, specifically, multiple serial communication interfaces and multiple display interface integrated devices can support multiple serial ports and display interfaces simultaneously, providing higher connectivity and flexibility, more convenient connection and management of multiple external devices or displays, meeting the diversified needs of the system.

[0007] (2) Improve data transmission speed, specifically, multiple display interfaces and multiple serial communication interface integrated devices have higher data transmission speed, which can meet the needs of high-speed data transmission and improve the performance and efficiency of the system.

[0008] (3) Reduce dependence on external devices, multiple display interfaces and multiple serial communication interface integrated devices have multiple serial ports and display interfaces built-in, without the need for additional external devices or interface converters, reducing system dependency and compatibility issues, simplifying system configuration and management.

[0009] (4) Save space and simplify wiring, specifically, multiple display interfaces and multiple serial communication interface integrated devices integrate multiple interfaces in one device, saving space resources and simplifying wiring, which can better manage and organize interfaces and lines, reducing wiring confusion and management difficulties.

[0010] (5) Reduce maintenance and management costs, specifically, multiple display interfaces and multiple serial communication interface integrated devices integrate multiple interfaces, reducing the costs of purchasing, installing, configuring and maintaining additional devices and interfaces, thereby reducing maintenance and management costs.

[0011] In an alternative embodiment, two second interface chips are provided between the first LPC signal conversion chip and one serial communication interface, and the interface integrated circuit further includes a pin and a jumper cap; the first interface chip connects the RS232 interface through the pin, one second interface chip connects the RS422 interface through the pin, and the other second interface chip connects the RS485 interface, and the jumper cap is used to switch the RS232 interface, the RS422 interface and the RS485 interface at different positions on the pin.

[0012] In this embodiment, the interface is switched by adjusting the position of the jumper cap, without the need to redesign or replace the hardware circuit, reducing the hardware cost and improving the versatility and adaptability of the circuit.

[0013] In an alternative embodiment, the third interface chip switches the RS232 interface, the RS422 interface and the RS485 interface based on the configuration information of the BIOS.

[0014] In this embodiment, the switching process is performed through BIOS configuration, which can ensure that the system can perform appropriate signal processing and isolation during the switching process, reduce the possibility of signal interference, and ensure the stability and accuracy of communication.

[0015] In an optional implementation, the serial communication interface is further connected with an electrostatic protection circuit, the electrostatic protection circuit comprising a bidirectional TVS diode and a capacitor; one end of the bidirectional TVS diode and one end of the capacitor are both connected with the serial communication interface, and the other end of the bidirectional TVS diode and the other end of the capacitor are both grounded.

[0016] In the embodiment, the bidirectional TVS diode and the capacitor are arranged to protect the circuit from external electrostatic interference and transient voltage surges.

[0017] In an optional implementation, the first end of the processor is connected with the HDMI interface in series with a resistor and an inductor.

[0018] In the embodiment, the resistor is used for impedance matching to reduce signal reflection and loss, ensure efficient signal transmission, prevent signal distortion, and improve the quality and stability of HDMI data transmission; the inductor constitutes a common-mode inductor to suppress common-mode interference signals and prevent their transmission, thereby ensuring the purity of HDMI differential signals and improving the anti-interference ability and stability of signal transmission.

[0019] In an optional implementation, the HDMI interface and the first end of the processor both comprise an HPD pin, the HPD pin of the HDMI interface and the HPD pin of the first end of the processor are connected through an HPD detection circuit, the HPD detection circuit outputs a target electrical signal after the HDMI interface is connected with a display device, and the target electrical signal triggers the first end of the processor to output a DDI signal.

[0020] In an optional implementation, the interface integrated circuit further comprises a display interface voltage conversion module; one end of the display interface voltage conversion module is connected with the display interface, and the other end of the display interface voltage conversion module is connected with the display device, for converting a signal of a first voltage threshold transmitted by the display device into a signal of a second voltage threshold adapted to the display interface.

[0021] In an optional implementation, the interface integrated circuit further comprises a third LPC signal conversion chip and a GPIO interface; the first end of the third LPC signal conversion chip is connected with the fourth end of the serial signal conversion chip, and the second end of the third LPC signal conversion chip is connected with the GPIO interface, and the third LPC signal conversion chip is used for converting and processing the received LPC signal and the GPIO signal adapted to the GPIO interface.

[0022] In an alternative embodiment, the processor comprises a PCIE port, a SATA3.0 port and a USB2.0 port, the interface integrated circuit further comprises a plurality of USB2.0 interfaces, a plurality of USB3.0 interfaces, a plurality of M.2 KEY M interfaces, a SATA interface, a SATA connector, an Ethernet controller chip and a plurality of network interfaces; the network interfaces are connected with the PCIE port through the Ethernet controller chip, the M.2 KEY M interfaces are connected with the SATA3.0 port, the SATA interface is connected with the SATA3.0 port through the SATA connector, and the USB2.0 interfaces and the USB3.0 interfaces are connected with the USB2.0 port.

[0023] In a second aspect, the utility model provides an interface integrated equipment, interface integrated equipment includes interface integrated circuit of above -mentioned first aspect or its any implementation. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the specific embodiment of the utility model or the technical scheme in the related art, the drawings needed in the specific embodiment or related art description will be briefly introduced below, and obviously, the drawings in the following description are some embodiments of the utility model, and those skilled in the art can obtain other drawings according to these drawings without creating labor.

[0025] Figure 1 It is a schematic diagram of an interface integrated circuit according to an embodiment of the utility model;

[0026] Figure 2 It is a schematic diagram of the output signal of the first end of the processor according to an embodiment of the utility model;

[0027] Figure 3 It is a schematic diagram of the processor and HDMI interface connection according to an embodiment of the utility model;

[0028] Figure 4 It is a schematic diagram of a HDMI interface according to an embodiment of the utility model;

[0029] Figure 5 It is a schematic diagram of a HDMI interface power supply module according to an embodiment of the utility model;

[0030] Figure 6 It is a schematic diagram of a HDMI interface voltage conversion module according to an embodiment of the utility model;

[0031] Figure 7 It is a schematic diagram of a HPD detection circuit according to an embodiment of the utility model;

[0032] Figure 8Is the output signal of the fourth end of a kind of processor according to the embodiment of the utility model's schematic diagram;

[0033] Figure 9 Is the signal output of another kind of processor according to the embodiment of the utility model's schematic diagram of the fourth end;

[0034] Figure 10 Is the signal output of another kind of processor according to the embodiment of the utility model's schematic diagram of the fourth end;

[0035] Figure 11 Is the schematic diagram of a VGA interface according to the embodiment of the utility model;

[0036] Figure 12 Is the schematic diagram of another VGA interface according to the embodiment of the utility model;

[0037] Figure 13 Is the schematic diagram of another VGA interface according to the embodiment of the utility model;

[0038] Figure 14 Is the schematic diagram of a second display signal conversion chip according to the embodiment of the utility model;

[0039] Figure 15 Is the schematic diagram of a first voltage conversion circuit according to the embodiment of the utility model;

[0040] Figure 16 Is the schematic diagram of a second voltage conversion circuit according to the embodiment of the utility model;

[0041] Figure 17 Is the schematic diagram of a third voltage conversion circuit according to the embodiment of the utility model;

[0042] Figure 18 Is the schematic diagram of a second display signal conversion chip power supply module according to the embodiment of the utility model;

[0043] Figure 19 Is the schematic diagram of another second display signal conversion chip power supply module according to the embodiment of the utility model;

[0044] Figure 20 Is the schematic diagram of another second display signal conversion chip power supply module according to the embodiment of the utility model;

[0045] Figure 21 Is the schematic diagram of another second display signal conversion chip power supply module according to the embodiment of the utility model;

[0046] Figure 22 Is the schematic diagram of a VGA interface power supply module according to the embodiment of the utility model;

[0047] Figure 23 is a schematic view of an output signal of a third end of a processor according to an embodiment of the present application;

[0048] Figure 24 is a schematic view of a first display signal conversion chip according to an embodiment of the present application;

[0049] Figure 25 is a schematic view of an LVDS interface according to an embodiment of the present application;

[0050] Figure 26 is a schematic view of a connection relationship of an output signal of a third end of a processor according to an embodiment of the present application;

[0051] Figure 27 is a schematic view of a first display configuration control circuit according to an embodiment of the present application;

[0052] Figure 28 is a schematic view of a second display configuration control circuit according to an embodiment of the present application;

[0053] Figure 29 is a schematic view of an SMBUS interface chip according to an embodiment of the present application;

[0054] Figure 30 is a schematic view of an online burning FW circuit according to an embodiment of the present application;

[0055] Figure 31 is a schematic view of another HDP detection circuit according to an embodiment of the present application;

[0056] Figure 32 is a schematic view of a pull-up circuit according to an embodiment of the present application;

[0057] Figure 33 is a schematic view of a crystal oscillator circuit according to an embodiment of the present application;

[0058] Figure 34 is a schematic view of a display configuration circuit according to an embodiment of the present application;

[0059] Figure 35 is a schematic view of a first display signal conversion chip power supply module according to an embodiment of the present application;

[0060] Figure 36 is a schematic view of another first display signal conversion chip power supply module according to an embodiment of the present application;

[0061] Figure 37 is a schematic view of still another first display signal conversion chip power supply module according to an embodiment of the present application;

[0062] Figure 38 is a schematic view of a connection relationship of an LVDS interface and a CS5211 chip according to an embodiment of the present application;

[0063] Figure 39 is another connection schematic view of an LVDS interface according to an embodiment of the present application;

[0064] Figure 40 is a schematic view of an LED power supply control circuit according to an embodiment of the present application;

[0065] Figure 41 is a schematic view of another LED power supply control circuit according to an embodiment of the present application;

[0066] Figure 42 is a schematic view of a backlight control circuit according to an embodiment of the present application;

[0067] Figure 43 is a schematic view of another backlight control circuit according to an embodiment of the present application;

[0068] Figure 44 is a schematic view of a color depth selection circuit according to an embodiment of the present application;

[0069] Figure 45 is a schematic view of an LVDS device access detection circuit according to an embodiment of the present application;

[0070] Figure 46 is a schematic view of an output signal of an IT8786E according to an embodiment of the present application;

[0071] Figure 47 is a schematic view of an output signal of a fifth end of a processor according to an embodiment of the present application;

[0072] Figure 48 is a schematic view of a third interface chip according to an embodiment of the present application;

[0073] Figure 49 is a schematic view of a COM interface according to an embodiment of the present application;

[0074] Figure 50 is a schematic view of a fault safety circuit according to an embodiment of the present application;

[0075] Figure 51 is a connection relationship schematic view of a COM interface according to an embodiment of the present application;

[0076] Figure 52 is a schematic view of an electrostatic protection circuit according to an embodiment of the present application;

[0077] Figure 53 is a schematic view of a third interface chip power supply module according to an embodiment of the present application;

[0078] Figure 54 is a schematic view of an output signal of a second LPC signal conversion chip according to an embodiment of the present application;

[0079] Figure 55 is a schematic view of an output signal of another second LPC signal conversion chip according to an embodiment of the present application;

[0080] Figure 56 is a schematic view of a first interface chip according to an embodiment of the present application;

[0081] Figure 57 is a schematic view of another COM interface according to an embodiment of the present application;

[0082] Figure 58 is a schematic view of another electrostatic protection circuit according to an embodiment of the present application;

[0083] Figure 59 is a schematic view of a first interface chip power supply module according to an embodiment of the present application;

[0084] Figure 60 is a schematic view of a serial signal conversion chip according to an embodiment of the present application;

[0085] Figure 61 is a schematic view of an F81216E chip according to an embodiment of the present application;

[0086] Figure 62 is a schematic view of still another crystal oscillator circuit according to an embodiment of the present application;

[0087] Figure 63 is a schematic view of a connection relationship of an F81216E chip according to an embodiment of the present application;

[0088] Figure 64 is a schematic view of a connection relationship of another F81216E chip according to an embodiment of the present application;

[0089] Figure 65 is a schematic view of a connection relationship of still another F81216E chip according to an embodiment of the present application;

[0090] Figure 66 is a schematic view of a connection relationship of still another F81216E chip according to an embodiment of the present application;

[0091] Figure 67is a schematic view of the connection of the F81216E chip and the power supply according to the embodiment of the present application;

[0092] Figure 68 is a schematic view of a first LPC signal conversion chip power supply module according to the embodiment of the present application;

[0093] Figure 69 is a schematic view of another first interface chip according to the embodiment of the present application;

[0094] Figure 70 is a schematic view of the connection relationship between two second interface chips and the F81216E chip according to the embodiment of the present application;

[0095] Figure 71 is a schematic view of the connection of the interface chip and the RS232 interface, the RS422 interface and the RS485 interface according to the embodiment of the present application;

[0096] Figure 72 is a schematic view of another COM interface according to the embodiment of the present application;

[0097] Figure 73 is a schematic view of another first interface chip power supply module according to the embodiment of the present application. DETAILED DESCRIPTION

[0098] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. According to the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0099] At present, the host devices on the market usually have a single serial communication interface and a single display interface. The single serial communication interface and the single display interface usually have the following problems:

[0100] (1) Limited connectivity. Specifically, the single display interface can usually only connect one display, and it is difficult to connect multiple displays at the same time, which limits the expandability and application range of the host device.

[0101] (2) Limited data transmission speed. Specifically, the single serial communication interface usually has a low data transmission speed and cannot meet the demand for high-speed data transmission. In applications requiring high-speed data transmission, the single serial communication interface is likely to become a bottleneck, affecting the performance and efficiency of the host device.

[0102] (3) Excessive reliance on external devices. Specifically, single serial communication interface and display interface devices usually require specific external devices or displays for connection and use, which increases the system's dependence and compatibility issues. Moreover, additional devices and interface converters may be needed to meet the connection requirements of different devices and displays.

[0103] (4) Large space occupation and complex wiring. Specifically, a single serial communication interface and display interface device requires independent physical interfaces and connection lines, which occupy a large space and increase the complexity of wiring.

[0104] (5) High maintenance and management costs. Specifically, due to the limitations of single serial communication interface and display interface devices, additional devices and interfaces may be required to meet connection requirements, thereby increasing the maintenance and management costs of the devices, including the costs of purchasing, installing, configuring and repairing the devices.

[0105] In view of this, the present invention provides an interface integrated circuit that, by integrating multiple serial communication interfaces and multiple display interfaces, can improve data transmission speed, reduce dependence on external devices, save space, simplify wiring, and reduce maintenance and management costs.

[0106] The interface integrated circuit provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0107] like Figure 1 As shown, the interface integrated circuit includes a processor 110, multiple display interfaces, multiple serial communication interfaces (Communication Port, COM), a first display signal conversion chip, a second display signal conversion chip, a serial signal conversion chip, a first low pin count bus (LPC) signal conversion chip, a second LPC signal conversion chip, a first interface chip, a second interface chip, and a third interface chip.

[0108] The plurality of display interfaces include a High-Definition Multimedia Interface (HDMI), a Low-Voltage Differential Signaling (LVDS) interface, a Video Graphics Array (VGA) interface, and a DisplayPort (DP) or Embedded DisplayPort (EDP), and each serial communication interface includes a Recommended Standard 232 (RS232) interface, a Recommended Standard 422 (RS422) interface, and a Recommended Standard 485 (RS485) interface.

[0109] In Figure 1 , EDP / DP represents the EDP interface or the DP interface, LVDS represents the LVDS interface, VGA represents the VGA interface, HDMI represents the HDMI interface, CS5211 represents the first display signal conversion chip, IT6516 represents the second display signal conversion chip, COM1-2, COM3-6, COM7-10, and COM11-14 each represent a serial communication interface, RS232 / RS422 / RS485 represents a corresponding serial communication interface and can be specifically an RS232 interface, an RS422 interface, or an RS485 interface, F85227N represents a serial signal conversion chip, F81216E represents the first LPC signal conversion chip, IT8786E represents the second LPC signal conversion chip, UM3243 represents the first interface chip, UM3483 represents the second interface chip, and UM324463 represents the third interface chip. Figure 1 In , the interface integrated circuit includes one EDP interface or DP interface, one LVDS interface, three VGA interfaces, one HDMI interface, and fourteen COM interfaces, but is not limited thereto.

[0110] Specifically, as shown in Figure 1 , a first end of the processor 110 is connected to the HDMI interface, a second end of the processor 110 is connected to the DP interface or the EDP interface, a third end of the processor 110 is connected to the LVDS interface through the first display signal conversion chip (CS5211), and a fourth end of the processor 110 is connected to the VGA interface through the second display signal conversion chip (IT6516).

[0111] The first display signal conversion chip is used for conversion processing of the EDP signal output by the third end of the processor 110 and the LVDS signal adapted to the LVDS interface, that is, when the display device connected to the LVDS interface transmits a signal to the processor 110, the CS5211 is used for converting the received LVDS signal into an EDP signal adapted to the third end of the processor, and when the processor 110 transmits a signal to the LVDS interface, the CS5211 is used for converting the received EDP signal into an LVDS signal adapted to the LVDS interface.

[0112] The second display signal conversion chip is used for conversion processing of the display data interface (DDI) signal output by the fourth end of the processor 110 and the VGA signal adapted to the VGA interface, that is, when the display device connected to the VGA interface transmits a signal to the processor 110, the IT6516 is used for converting the received VGA signal into a DDI signal adapted to the fourth end of the processor, and when the processor 110 transmits a signal to the VGA interface, the IT6516 is used for converting the received DDI signal into a VGA signal adapted to the VGA interface.

[0113] The fifth end of the processor 110 is connected to the first end of the serial signal conversion chip (F85227N), the second end of the serial signal conversion chip (F85227N) is connected to a plurality of serial communication interfaces (such as COM7-10 and COM11-14 in FIG. 1) through the first LPC signal conversion chip (F81216E), the first interface chip (UM3243) and the second interface chip (UM3483). Figure 1

[0114] The third end of the serial signal conversion chip (F85227N) is connected to the first end of the second LPC signal conversion chip (IT8786E), the second end of the second LPC signal conversion chip (IT8786E) is connected to a plurality of serial communication interfaces (such as COM1-2 in FIG. 1) through the third interface chip (UM324463), and the third end of the second LPC signal conversion chip (IT8786E) is connected to a plurality of serial communication interfaces (such as COM3-6 in FIG. 1) through the first interface chip (UM3243) and the second interface chip (UM3483). Figure 1 Figure 1

[0115] ​​​The serial signal conversion chip (F85227N) is configured to convert and process the enhanced serial peripheral interface (ESPI) signal and the LPC signal output by the fifth end of the processor 110, that is, when the processor 110 transmits a signal to a device connected to the COM interface, the F85227N is configured to convert the received ESPI signal into an LPC signal, and when the device connected to the COM interface transmits a signal to the processor 110, the F85227N is configured to convert the received LPC signal into an ESPI signal.

[0116] The first LPC signal conversion chip and the second LPC signal conversion chip are both configured to convert and process the received LPC signal and the universal asynchronous receiver / transmitter (UART) signal, that is, the F81216E and the IT8786E can be configured to convert the received LPC signal into a UART signal and convert the received UART signal into an LPC signal.

[0117] The first interface chip, the second interface chip, and the third interface chip are all configured to switch and process the RS232 interface, the RS422 interface, and the RS485 interface, that is, by using the UM3243, the UM3483, and the UM324463, the COM interface can be set as the RS232 interface, the RS422 interface, or the RS485 interface.

[0118] For example, the processor 110 in the embodiment can be a central processing unit (CPU), for example, the processor 110 can be a J6412 model processor of the Elkhart Lake platform, which adopts a ball grid array (BGA) package, the size can be 35 mm x 24 mm, the thermal design power (TDP) can be 10 W, and the processor can accept a wide range of direct current (DC) input (such as 9V-36V) and TFX (Thin Form Factor eXpansion) power input.

[0119] In the embodiment, by arranging the first display signal conversion chip, the second display signal conversion chip, the serial signal conversion chip, the first LPC signal conversion chip, the second LPC signal conversion chip, the first interface chip, the second interface chip, and the third interface chip, the processor can integrate multiple display interfaces and multiple serial communication interfaces, and the device integrating the multiple display interfaces and the multiple serial communication interfaces has the following advantages:

[0120] (1) High connectivity and flexibility, specifically, the multiple serial communication interface and multiple display interface integrated device can support multiple serial ports and display interfaces simultaneously, providing higher connectivity and flexibility, more convenient connection and management of multiple external devices or displays, meeting the diversified needs of the system.

[0121] (2) Improve data transmission speed, specifically, the multiple display interface and multiple serial communication interface integrated device has higher data transmission speed, can meet the needs of high-speed data transmission, can improve the performance and efficiency of the system.

[0122] (3) Reduce dependence on external devices, multiple display interface and multiple serial communication interface integrated device built-in multiple serial ports and display interfaces, without additional external devices or interface converters, reducing the system's dependence and compatibility issues, simplifying the system configuration and management.

[0123] (4) Save space and simplify wiring, specifically, the multiple display interface and multiple serial communication interface integrated device integrates multiple interfaces in one device, saving space resources and simplifying wiring, better managing and organizing interfaces and lines, reducing wiring confusion and management difficulties.

[0124] (5) Reduce maintenance and management costs, specifically, the multiple display interface and multiple serial communication interface integrated device integrates multiple interfaces, reducing the cost of purchasing, installing, configuring and maintaining additional devices and interfaces, thereby reducing maintenance and management costs.

[0125] That is, the present embodiment enables the processor to integrate multiple display interfaces and multiple serial communication interfaces, which can improve data transmission speed, reduce dependence on external devices, save space, simplify wiring, and reduce maintenance and management costs.

[0126] First, the connection between the processor and the multiple display interfaces will be described in detail below in conjunction with the accompanying drawings.

[0127] As shown in FIG. 1, the processor 100 is connected to multiple display interfaces 200, 300, 400, 500, 600, 700, 800 and 900. Figure 2As shown, the signals outputted by the plurality of control pins (PIN) of the first end of the processor 110 include DDI2_CPU_PT_TXN0, DDI2_CPU_PT_TXP0, DDI2_CPU_PT_TXN1, DDI2_CPU_PT_TXP1, DDI2_CPU_PT_TXP2, DDI2_CPU_PT_TXN2, DDI2_CPU_PT_TXN3, DDI2_CPU_PT_TXP3, DDI2_CPU_PT_AUXP and DDI2_CPU_PT_AUXN, which are transmitted to the HDMI interface and used for the output of video and audio signals. After conversion, the signals outputted from the processor 110 are converted into DDI_TX0, HDMI_TX2, DDI_TX1, HDMI_TX1, DDI_TX2, HDMI_TX0 and DDI_TX3, HDMI_CLK.

[0128] As shown in the example, Figure 3 As shown, the first end of the processor is connected with the HDMI interface through the series connection of resistors (R24 to R31) and inductors (L1 to L4). Specifically, Figure 3 The left side HDMI1_CPU_CD_TXP0, HDMI1_CPU_CD_TXN0, HDMI1_CPU_CD_TXP1, HDMI1_CPU_CD_TXN1, HDMI1_CPU_CD_TXP2, HDMI1_CPU_CD_TXN2, HDMI1_CPU_CD_CLKP and HDMI1_CPU_CD_CLKN pins are connected with the first end of the processor 110 as shown in Figure 2 Figure 3 The right side HDMI1_CN_TXP0, HDMI1_CN_TXN0, HDMI1_CN_TXP1, HDMI1_CN_TXN1, HDMI1_CN_TXP2, HDMI1_CN_TXN2, HDMI1_CN_CLKP and HDMI1_CN_CLKN are connected with the corresponding pins in the HDMI interface as shown in Figure 4

[0129] In the embodiment, the resistors are used for impedance matching to reduce signal reflection and loss, ensure efficient signal transmission, prevent signal distortion, improve the quality and stability of HDMI data transmission; the inductors are used for common mode inductance to suppress common mode interference signals, prevent their transmission, ensure the purity of HDMI differential signals (HDMI_CN_TXP[X], HDMI_CN_TXN[X]) and improve the anti-interference ability and stability of signal transmission.

[0130] ​​For example, the first end of the processor is also connected in series with capacitors (C4-C11). The capacitors can act as filters to remove high-frequency noise in the signal, stabilize the HDMI data signal, make HDMI data transmission more reliable, and ensure the quality of high-definition audio and video signals.

[0131] Specifically, the interface integrated circuit also includes an HDMI interface power supply module and a display interface voltage conversion module. The HDMI interface power supply module is connected to the HDMI interface to supply power to it. The display interface voltage conversion module is connected to the display interface at one end and to the display device at the other end. It is used to convert the signal transmitted by the display device at a first voltage threshold into a signal at a second voltage threshold adapted to the display interface, enabling different modules to recognize and process signals. In this embodiment, the display interface voltage conversion module is specifically an HDMI interface voltage conversion module, and the display interface is specifically an HDMI interface.

[0132] For example, the HDMI interface power supply module can be as follows: Figure 5 As shown, Figure 5 5V_HDMI1_S0 and Figure 4 The 5V_HDMI1_S0 connection, specifically, Figure 5 The 5V_S0 and 12V_S0 are external power supplies. These power supplies are processed by the HDMI interface power supply module to power the HDMI interface. The 12V_S0 voltage charges capacitor C3 through resistor R3, causing the gate voltage of MOSFET Q2 to gradually increase. When the gate voltage reaches the turn-on voltage of MOSFET Q2, MOSFET Q2 turns on, and the 5V_S0 power supply outputs a 5V_HDMI_M_S0 signal through the drain of MOSFET Q2. Then, the 5V_HDMI_M_S0 signal passes through fuse F1 and ferrite bead B1, and is filtered by capacitors C1 and C2 before outputting a 5V voltage to the HDMI interface.

[0133] In this embodiment, the HDMI interface power supply module includes an anti-backflow circuit formed by an N-type MOSFET. When the HDMI interface power supply module provides a stable power supply to the HDMI interface, the anti-backflow circuit is used to prevent the HDMI voltage from flowing back into the board.

[0134] For example, an HDMI interface voltage conversion module can be as follows: Figure 6 As shown, Figure 6 The DDC_HDMI1_CN_SCL and DDC_HDMI1_CN_SDA in the context of... Figure 4 The corresponding pin connections in the HDMI interface are shown.

[0135] Specifically, Figure 6The field effect transistor Q3A in the figure is used to convert the serial clock (SCL) signal, and the field effect transistor Q3B is used to convert the serial data (SDA) signal. By controlling the gate (G) voltage to turn on or turn off, the conversion of the 3.3V (3D3V_S0) level signal to the 5V (5V_HDMI1_S0) level signal is realized. When the gate receives a suitable voltage, the field effect transistor is turned on, allowing the signal to pass and realizing the level conversion; when it is turned off, the signal is blocked.

[0136] Among them, the resistor R6, the resistor R7, the capacitor C13 and the capacitor C14 and other components form a simple filter and protection circuit, which prevents high-frequency noise and interference signals from affecting the main signal, and ensures the stability and consistency of signal transmission.

[0137] In some embodiments, as shown in Figure 2 and Figure 4 The first end of the HDMI interface and the processor 110 both include a hot-plug detection (HPD) pin, and the HPD pin of the HDMI interface and the HPD pin of the first end of the processor are connected through an HPD detection circuit. The HPD detection circuit outputs a target electrical signal after the HDMI interface accesses the display device, and the target electrical signal triggers the first end of the processor to output a DDI signal. The target electrical signal can be a high-level signal.

[0138] Specifically, the HPD detection circuit can be as shown in Figure 7 The HPD detection circuit is used to detect whether the HDMI device is connected or disconnected. When the HDMI device is inserted, the HPD_CN_HDMI1 signal state changes (usually from low to high), and the change is transmitted to the HPD_PCH_CD_HDMI1 through the field effect transistor, which informs the processor 110 that a new device is accessed, and the processor 110 can output the DDI signal; when the device is pulled out, the signal state reverses, and the processor 110 can stop the output operation on the device.

[0139] Among them, the resistor R1 is a pull-up resistor, which connects the gate of the field effect transistor Q1 to the 3.3V power supply (3D3V_S0), and provides a stable high-level bias for the gate, so that the field effect transistor Q1 remains in the on or off state under normal circumstances. The resistor R2 is a pull-down resistor, which is connected between the HPD_CN_HDMI1 signal and the ground. When there is no external signal to pull up HPD_CN_HDMI1, the signal is pulled down to the ground level, ensuring that the signal is in a determined low level state when there is no input.

[0140] In the embodiment, the connection between the processor and the HDMI interface does not need other conversion chips, the cost can be reduced, and the resolution of the HDMI interface is up to 4096x2160@60Hz, and the experience of the user can be improved.

[0141] For example, the interface integrated circuit provided in the embodiment includes three VGA interfaces, as shown in the following figure. Figures 8 to 10 As shown in the figure, the signals output by the plurality of control pins (PINs) of the fourth end of the processor 110 include DDI1_CPU_PT_TXN0, DDI1_CPU_PT_TXP0, DDI2_CPU_PT_TXN1, DDI1_CPU_PT_TXP1, DDI1_CPU_PT_AUXP, DDI1_CPU_PT_AUXN, etc., and the above signals are used for data serial transmission. Among them, the signals output by the control pins of the processor 110 corresponding to different VGA interfaces are different in the number after DDI, for example, the first VGA interface (VGA1) corresponds to DDI0, the second VGA interface (VGA2) corresponds to DDI1, and the third VGA interface (VGA3) corresponds to DDI2.

[0142] The structure of the three VGA interfaces can be as shown in the following figure. Figures 11 to 13 As shown in the figure, the structure of the second display signal conversion chip (IT6516) can be as shown in the following figure, which is described in connection with the connection relationship of one of the VGA interfaces and the processor, and the rest of the VGA interfaces are the same. Figure 14

[0143] Specifically, the DDI1_CPU_PT_TXN0, DDI1_CPU_PT_TXP0, DDI2_CPU_PT_TXN1, DDI1_CPU_PT_TXP1, DDI1_CPU_PT_AUXP, and DDI1_CPU_PT_AUXN on the left side of the IT6516 are connected to the corresponding control pins of the fourth end of the processor 110 as shown in the following figure. Figure 8

[0144] For example, the interface integrated circuit further includes a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit, and the first voltage conversion circuit, the second voltage conversion circuit, and the third voltage conversion circuit are used for precisely adjusting the voltage level of the input signal and the output signal.

[0145] ​​The signal terminal VGA1_VSYNC in the IT6516 is connected to the corresponding pin in the VGA interface after being converted into the VGA1_CN_VSYNC signal by the first voltage conversion circuit, the signal terminal VGA1_HSYNC in the IT6516 is connected to the corresponding pin in the VGA interface after being converted into the VGA1_CN_HSYNC signal by the second voltage conversion circuit, and the signal terminals VGA1_SDA and VGA1_SCL in the IT6516 are connected to the corresponding pins in the VGA interface after being converted into the VGA1_CN_SDA signal and the VGA1_CN_SCL signal by the third voltage conversion circuit.

[0146] Specifically, the first voltage conversion circuit can be as shown in the figure. Figure 15 As shown in the figure, the VGA_VSYNC vertical synchronization signal is input to the driving chip U1, the driving chip U1 performs buffering and driving processing (amplification, shaping, etc.) on the input VGA_VSYNC signal and then outputs, the output signal is filtered by the RC filter circuit composed of the resistor R4 and the capacitor C15, high-frequency noise and interference signals are prevented from affecting the main signal, the VGA_CN_VSYNC signal is stably output to the VGA interface, and the 5V_S0 power supply supplies power to the driving chip U1.

[0147] The second voltage conversion circuit can be as shown in the figure. Figure 16 The second voltage conversion circuit is basically the same as the first voltage conversion circuit, and will not be described in detail here.

[0148] The third voltage conversion circuit can be as shown in the figure. Figure 17 Specifically, the 3.3V VGA1_SDA (serial data) and VGA1_SCL (serial clock) signals are respectively input to the source electrodes of the corresponding field effect transistor Q2B and field effect transistor Q2A, the gate electrodes of the field effect transistors are provided with voltage by the 3.3V power supply, and the on-off state of the field effect transistors changes with the input signal level. When the input 3.3V signal is at a high level, the field effect transistor is turned on, the 5V power supply pulls up the level of the output signal (VGA1_CN_SDA, VGA1_CN_SCL) to close to 5V through the pull-up resistor (R15, R16) and the turned-on field effect transistor, and the level conversion is completed; when the input 3.3V signal is at a low level, the field effect transistor is turned off, and the output end level is pulled down to close to 0V (low level) by the pull-up resistor.

[0149] The converted 5V VGA signal (VGA1_CN_SDA, VGA1_CN_SCL) is output through the circuit and recognized and processed by the display device connected to the subsequent VGA interface, and is used for data communication and control between VGA devices, such as transmission of display configuration information, etc.

[0150] Exemplarily, the interface integrated circuit further comprises a second display signal conversion chip power supply module and a VGA interface power supply module, the second display signal conversion chip power supply module supplies power for the second display signal conversion chip, and the VGA interface power supply module supplies power for the VGA interface.

[0151] Specifically, the second display signal conversion chip power supply module comprises a chip power supply circuit as shown in Figures 18 to 21 The power supply provides required voltages for the second display signal conversion chip through different voltage stabilizing circuits, and the chip power supply circuit as shown in Figures 18 to 21 performs filtering and adjustment through a capacitor and a magnetic bead. The VGA interface power supply module can be similar to the above-described HDMI interface power supply module as shown in Figure 22 , and thus will not be described in detail here.

[0152] In the embodiment, the second display signal conversion chip can manage and process input data streams and output data streams, so as to communicate with and interact with the device connected with the VGA interface.

[0153] Optionally, an HPD detection circuit is also arranged between the VGA interface and the second display signal conversion chip, and the HPD detection circuit is used to detect whether the VGA device is connected or disconnected.

[0154] As shown in Figure 23 , the signals output by the plurality of control pins of the third end of the processor include EDP_CPU_PT_TXN0, EDP_CPU_PT_TXP0, EDP_CPU_PT_TXN1, EDP_CPU_PT_TXP1, EDP_CPU_PT_AUXN, EDP_CPU_PT_AUXP, HPD_LVDS_EDP, EDP_BKLTCTL, GPIO0_M_TR5511, GPIO1_M_TR5511, GPIO2_M_TR5511, GPIO3_M_TR5511, GPIO4_RESET_TR5511, SMB_PCH_PT_SCL, SMB_PCH_PT_SDA and PLTRST_PCH_TR5511, etc., and the processor controls the resolution of the LVDS interface output through the GPIO interface. The structure of the first display signal conversion chip (CS5211) can be as shown in Figure 24 , and the structure of the LVDS interface can be as shown in Figure 25 .

[0155] Among them, the CS5211 chip can also be used to manage the transmission and processing of EDP signals, such as sending EDP_HPD signals to a display device, managing the display level, brightness, etc.

[0156] Specifically, the EDP_CPU_PT_TXN0, EDP_CPU_PT_TXP0, EDP_CPU_PT_TXN1 and EDP_CPU_PT_TXP1 signal terminals of the third end of the processor 110 are connected to the corresponding control pins of the CS5211 chip Figure 24 as shown, the EDP_CPU_PT_AUXP signal terminal of the third end of the processor 110 and the PLTRST_PCH_TR5511 signal terminal are both connected to ground through a series resistor, and the EDP_CPU_PT_AUXN signal terminal of the third end of the processor 110 and the GPIO4_RESET_TR5511 signal terminal are both connected to the 3D3V_S0 power supply through a series resistor. Figure 26

[0157] The GPIO0_M_TR5511, GPIO1_M_TR5511, GPIO2_M_TR5511 and GPIO3_M_TR5511 of the third end of the processor 110 are connected to the GPIO0_TR5511, GPIO1_TR5511, GPIO2_TR5511 and GPIO3_TR5511 pin terminals of the CS5211 through the first display configuration control circuit.

[0158] For example, the first display configuration control circuit can be as shown in Figure 27 As shown, the first display configuration control circuit realizes the transmission control of the GPIO signal (GPIO0_M_TR5511-GPIO3_M_TR5511) to the corresponding output signal (GPIO0_TR5511-GPIO3_TR5511) through the conduction and cutoff of the field effect tube (Q1A, Q1B, Q3A, Q3B). Among them, the pull-up and pull-down effect of the resistor in the first display configuration control circuit ensures the level stability of the GPIO signal in different states. The pull-up resistor keeps the signal at high level when there is no input, and the pull-down resistor pulls the signal low when necessary, avoiding the state of signal suspension or instability, ensuring that the display configuration signal can be accurately recognized and processed, so as to realize the correct configuration of the display device, such as setting the display mode, resolution and other parameters.

[0159] The GPIO4_RESET_TR5511 and PLTRST_PCH_TR5511 of the third end of the processor 110 are connected to the pin terminal of the RESET_D_M_M_TR5511 of the CS5211 through the second display configuration control circuit.

[0160] For example, the second display configuration control circuit can be as shown in Figure 28 ​As shown, the second display configuration control circuit integrates the reset signals of the two different sources of PLTRST PCH TR5511 and GPIO4 RESET TR5511 into the RESET D TR5511 signal through the diode D1, and isolates them to avoid mutual influence between the signals. The RESET D TR5511 signal is further processed and converted through the circuit composed of field effect tubes Q4A and Q4B. Specifically, the conduction and cutoff of the field effect tube are controlled according to the state of the input signal, the transmission or blocking of the signal is realized, and the signal is converted into the RESET D M M TR5511 output, which is used for reset operation on the related equipment (display equipment, etc.).

[0161] The third end of the processor 110 is connected to the SMB PCH PT SCL and SMB PCH PT SDA of the CS5211 through the SMBUS interface chip SMBUS ISP TR5511. Figure 29 As shown, the SMBUS interface chip SMBUS ISP TR5511 is connected to the pin end of the SMB PCH PT M SCL and SMB PCH PT M SDA of the CS5211 through the online burning firmware layer (FW) circuit.

[0162] Exemplarily, the online burning FW circuit can be as shown. Figure 30 As shown, the processor can flexibly control the on-off of the SMBus communication by controlling the switching state of the field effect tube in the online burning FW circuit, which is convenient for managing the communication in different stages such as the beginning, progress and end of burning, and realizes reliable online firmware burning operation, so that the firmware can be written into the CS5211 chip.

[0163] The third end of the processor 110 is connected to the HPD LVDS EDP signal end of the CS5211 chip through the HDP detection circuit.

[0164] Exemplarily, the HDP detection circuit can be as shown. Figure 31 As shown, the HDP detection circuit is used for detecting whether the LVDS interface is connected to the display equipment.

[0165] The BLUP TR5511, BLDN TR5511 and PWRDN TR5511 of the CS5211 chip are connected to the Figure 32The pull-up (PULLUP) circuit is shown, the pull-up circuit is connected to 3D3V_S0 (3.3V power supply) through three resistors (R26, R27, R28) respectively BLUP_TR5511 (brightness increase control signal), BLDN_TR5511 (brightness reduction control signal), PWRDN_TR5511 (power off control signal). When there is no external signal to pull down these pins, it keeps high level, provides a certain initial level condition for display device control circuit, facilitates correct identification of signal state during device initialization.

[0166] The XI_TR5511 and XO_TR5511 of the CS5211 chip are connected as shown Figure 33 The crystal oscillator circuit is shown, the crystal oscillator circuit generates a stable 27MHz clock signal through the crystal oscillator X1, provides a clock reference for the CS5211 chip, and ensures that each part of the circuit can work in coordination according to a fixed rhythm.

[0167] The DDC_E2P_CONN_SCL and DDC_E2P_CONN_SDA signal terminals of the CS5211 chip are connected to the corresponding pins of the DDC_LVDS_SCL and DDC_LVDS_SDA of the LVDS interface through the display configuration circuit.

[0168] For example, the display configuration circuit can be as shown Figure 34 The storage chip in the display configuration circuit is used to store the configuration information of the display device, and communicates with the processor through the I2C bus, so that the processor can read the configuration information of the display device, so as to correctly configure the display output, and ensure that the display device can work normally in the appropriate mode.

[0169] Specifically, the interface integrated circuit further comprises a first display signal conversion chip power supply module for supplying power to the first display signal conversion chip.

[0170] For example, the first display signal conversion chip power supply module comprises a chip power supply circuit as shown Figures 35 to 37 The power supply provides the required voltage for the first display signal conversion chip through different voltage stabilizing circuits, such as Figures 35 to 37 The chip power supply circuit is filtered and adjusted by capacitors and magnetic beads.

[0171] Specifically, as shown Figure 38As shown in the figure, the signal terminals of LVDS_LOW_CN_N0, LVDS_LOW_CN_P0, LVDS_LOW_CN_N1, LVDS_LOW_CN_P1, LVDS_LOW_CN_N2, LVDS_LOW_CN_P2, LVDS_LOW_CN_N3, LVDS_LOW_CN_P3, LVDS_LOW_CN_CLKN and LVDS_LOW_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors. Moreover, the signal terminals of LVDS_UP_CN_N0, LVDS_UP_CN_P0, LVDS_UP_CN_N1, LVDS_UP_CN_P1, LVDS_UP_CN_N2, LVDS_UP_CN_P2, LVDS_UP_CN_N3, LVDS_UP_CN_P3, LVDS_UP_CN_CLKN and LVDS_UP_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors.

[0172] In the embodiment, the matching resistors are arranged on the respective signal lines, so that the signal integrity can be determined, the reflection and interference can be reduced, and the transmission quality of the signals can be ensured.

[0173] As shown in the figure, the signal terminals of LVDS_LOW_CN_N0, LVDS_LOW_CN_P0, LVDS_LOW_CN_N1, LVDS_LOW_CN_P1, LVDS_LOW_CN_N2, LVDS_LOW_CN_P2, LVDS_LOW_CN_N3, LVDS_LOW_CN_P3, LVDS_LOW_CN_CLKN and LVDS_LOW_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors. Moreover, the signal terminals of LVDS_UP_CN_N0, LVDS_UP_CN_P0, LVDS_UP_CN_N1, LVDS_UP_CN_P1, LVDS_UP_CN_N2, LVDS_UP_CN_P2, LVDS_UP_CN_N3, LVDS_UP_CN_P3, LVDS_UP_CN_CLKN and LVDS_UP_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors. Figure 39 Figure 39 As shown in the figure, the signal terminals of LVDS_LOW_CN_N0, LVDS_LOW_CN_P0, LVDS_LOW_CN_N1, LVDS_LOW_CN_P1, LVDS_LOW_CN_N2, LVDS_LOW_CN_P2, LVDS_LOW_CN_N3, LVDS_LOW_CN_P3, LVDS_LOW_CN_CLKN and LVDS_LOW_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors. Moreover, the signal terminals of LVDS_UP_CN_N0, LVDS_UP_CN_P0, LVDS_UP_CN_N1, LVDS_UP_CN_P1, LVDS_UP_CN_N2, LVDS_UP_CN_P2, LVDS_UP_CN_N3, LVDS_UP_CN_P3, LVDS_UP_CN_CLKN and LVDS_UP_CN_CLKP of the LVDS interface are connected to the corresponding pins of the CS5211 chip after being connected in series with resistors and inductors.

[0174] Specifically, the related pins (such as LVDS_BITSET) of the LVDS interface are further connected to the LED power supply control circuit, the backlight control circuit, the color depth selection circuit and the frequency division circuit. Exemplarily, the LED power supply control circuit can be as shown in Figure 40 and Figure 41 which is used for managing and controlling the power supply (such as current control and voltage regulation, etc.) of the LED display screen. The backlight control circuit can be as shown in Figure 42 and Figure 43 which is used for adjusting the brightness of the display screen based on the PWM signal. The color depth selection circuit can be as shown in Figure 44 which is used for controlling and selecting the color depth that the display device can present, so as to provide diversified display modes for the user.

[0175] Exemplarily, the DET_LVDS_N signal terminal of the LVDS interface is connected to the LVDS device access detection circuit. The LVDS device access detection circuit can be as shown in Figure 45 which is used for detecting whether the LVDS device is accessed.

[0176] ​Specifically, whether the LVDS device is connected is determined by monitoring the level change of the DET_LVDS_N signal, wherein the resistor R49 is a pull-up resistor connected to 3D3V_S5 (3.3V power supply), and when there is no external signal to pull down the DET_LVDS_N signal, the signal pin is pulled high to 3.3V, so that the signal is kept at a high level, providing a default stable level reference for the detection circuit. The resistor R53 functions as a current limiter and signal buffer, and the capacitor C47 functions as a filter.

[0177] In the embodiment, the interface integrated circuit is compatible with most LVDS interface screens on the market, has strong adaptability, wide application scenarios, and a display interface resolution of up to 1920x1080@60Hz, which can improve the user experience.

[0178] The connection between the processor and the plurality of serial communication interfaces will be described in detail below with reference to the accompanying drawings.

[0179] For example, the second LPC signal conversion chip (IT8786E) is used to convert the LPC signal into a UART signal, and the signals output by the plurality of control pins of the second end of the IT8786E can be as shown in Figure 46 The fifth end of the processor 110 includes signal pins as shown in Figure 47 The structure of the third interface chip (UM324463) can be as shown in Figure 48 The third interface chip and the IT8786E are connected to the same signal end, the third interface chip and the processor are connected to the same signal end, and the third interface chip is also connected to a COM interface as shown in Figure 49 The third interface chip can convert the received UART signal into a signal compatible with the COM port and transmit the signal to the COM interface.

[0180] Specifically, the COM1_MODE1 signal end of the processor is connected to the COM1_SOUT and COM1_SIN signal ends of the COM port through a fail-safe circuit, and in the circuit, the COM1_DTR and COM1_DCD signal ends of the COM port are both connected in series with resistors and then grounded.

[0181] For example, the fail-safe (Fail Safe) circuit can be as shown in Figure 50 The fail-safe circuit is used to ensure that the subsequent circuit can still operate safely and stably when the communication interface fails or abnormally.

[0182] Specifically, the COM1_MODE1 signal is input to the gate of the field effect transistor Q1, when the COM1_MODE1 is high, the field effect transistor Q1 is turned on, and the drain voltage is raised, so that the gate voltage of the field effect transistor Q8 is also raised. When the gate voltage of the field effect transistor Q8 reaches the turn-on threshold, the field effect transistor Q8 is turned on, and the 5V_COM_S0 power supply supplies power to the COM1_MODE1_M signal through the field effect transistor Q8, so that the subsequent circuit is powered on and works. At this time, the communication signals COM1_SOUT and COM1_SIN can be transmitted through elements such as diode D9, and resistors R25 and R27 play a role in current limiting and impedance matching. In the signal transmission process, D9 prevents the signal from appearing in reverse voltage, and protects the circuit elements. The COM1_DTR and COM1_DCD signals are processed by resistors R30 and R31 for current limiting and the like.

[0183] When the COM1_MODE1 is low, Q1 is cut off, the gate voltage of Q8 is lowered, Q8 is also cut off, the connection between the 5V_COM_S0 power supply and COM1_MODE1_M is cut off, the subsequent circuit stops power supply, and the risk of damage caused by continuous work of the circuit in abnormal conditions is avoided. The capacitor C15 continuously filters the COM1_MODE1 signal throughout the process, ensuring the stability of the control signal.

[0184] For example, the third interface chip can switch the RS232 interface, the RS422 interface and the RS485 interface based on the configuration information of the BIOS.

[0185] Specifically, as shown in Figure 51 , the COM interface is connected to the RS232 interface, the RS422 interface and the RS485 interface through the jumper structure, and the third interface chip can short or disconnect different pins of the jumper based on the configuration information of the BIOS, so that the COM interface is switched to the RS232 interface, the RS422 interface or the RS485 interface. That is, the third interface chip can switch between the RS232 interface, the RS422 interface and the RS485 interface according to the selected jumper configuration.

[0186] For example, the signal end of the COM interface is also connected to an electrostatic protection circuit, as shown in Figure 52 , the electrostatic protection circuit includes a bidirectional TVS diode and a capacitor, one end of the bidirectional TVS diode and one end of the capacitor are connected to the serial communication interface, and the other end of the bidirectional TVS diode and the other end of the capacitor are grounded.

[0187] In this embodiment, by providing a bidirectional TVS diode and a capacitor, the circuit can be protected from external electrostatic interference and transient voltage impact.

[0188] Specifically, the interface integrated circuit further comprises a third interface chip power supply module, which can be configured as shown in Figure 53 The third interface chip power supply module is configured to provide 5V power supply for the third interface chip. The third interface chip power supply module is configured to prevent reverse power supply voltage by setting a Schottky diode, thereby protecting subsequent chip and other circuit elements from damage caused by reverse voltage.

[0189] For example, the signals output by the plurality of control pins of the third end of the second LPC signal conversion chip (IT8786E / IT8787E) can be configured as shown in Figure 54 or Figure 55 The structure of the first interface chip (UM3243) can be configured as shown in Figure 56 The structure of the second interface chip (UM3483) is similar to that of the first interface chip.

[0190] Specifically, the first interface chip and the second LPC signal conversion chip are connected to the same signal end, the first interface chip can convert the received UART signal into an RS232 standard signal, and the second interface chip and the second LPC signal conversion chip are connected to the same signal end, the second interface chip can convert the received UART signal into an RS422 standard signal or an RS485 standard signal. The first interface chip is connected to the RS232 interface in the COM interface, and the second interface chip is connected to the RS422 interface or the RS485 in the COM interface.

[0191] For example, the COM interface can be configured as shown in Figure 57 The COM interface is also configured to connect to an external communication device, the signal generated by the external communication device is transmitted into the COM interface, and is transmitted to the processor 110 after being processed by the serial port driving module.

[0192] Specifically, the signal end of the COM interface in the embodiment is also connected to an electrostatic protection circuit, which can be configured as shown in Figure 58 The electrostatic protection circuit is the same as the electrostatic protection circuit shown in Figure 57 Therefore, no detailed description is given here.

[0193] The interface integrated circuit further comprises a first interface chip power supply module and a second interface chip power supply module, the first interface chip power supply module can be configured as shown in Figure 59 to supply power for the first interface chip, and the second interface chip power supply module has the same structure as the first interface chip power supply module and is configured to supply power for the second interface chip.

[0194] For example, the serial signal conversion chip (F85227N) can be configured as shown in Figure 60As shown, the control pin of the first end of the serial signal conversion chip is connected with the corresponding signal end of the processor 110, which can be used for receiving the ESPI signal, the second end of the serial signal conversion chip (F85227N) is connected with the first LPC signal conversion chip (F81216E), and the serial signal conversion chip (F85227N) is also used for converting the ESPI signal into an LPC signal and transmitting the LPC signal to the F81216E through the corresponding pin.

[0195] Specifically, the structure of the F81216E can be as shown in Figure 61 As shown, the F81216E can be used for converting the received LPC signal into a UART signal.

[0196] Among them, the 24M_CLKIN1 and 24M_CLKIN2 signal ends of the F81216E are connected with the crystal circuit, and the crystal circuit can be as shown in Figure 62 As shown, the crystal circuit is used for generating a clock signal for the F81216E chip. As shown, Figure 63 The LPC1_LAD0_C, LPC1_LAD1_C, LPC1_LAD2_C, LPC1_LAD3_C, SERIRQ#_C, LRESET#_C, LFRAME#_C and PCICLK_C signal ends of the F81216E chip are all connected with the 3D3V_S0 power supply through a series resistance.

[0197] As shown, Figure 64 The UART8_SIO_DTR_N, UART7_SIO_DTR_N, UART10_SIO_SOUT, UART9_SIO_SOUT, UART8_SIO_SOUT and UART7_SIO_SOUT signal ends of the F81216E chip are all connected with the ground through a series resistance.

[0198] As shown, Figure 65 The UART10_SIO_RTS_N, UART9_SIO_DTR_N, UART7_SIO_RTS_N, UART8_SIO_RTS_N and UART9_SIO_RTS_N signal ends of the F81216E chip are all connected with the ground through a series resistance.

[0199] As shown, Figure 66 The WDT_OUT# signal end of the F81216E chip is connected with the 3D3V_S0_F81216E power supply through a series resistance; as shown, Figure 67 The GPIOA34 and GPIOA35 signal ends of the F81216E chip are both connected with the 3D3V_S0_F81216E power supply through a series resistance.

[0200] Specifically, the interface integrated circuit further comprises a first LPC signal conversion chip power supply module, which can be used to supply 3V power for the first LPC signal conversion chip, as shown in Figure 68

[0201] Specifically, two second interface chips are arranged between the first LPC signal conversion chip and the serial communication interface, the first part of the pins of the F81216E chip is connected to the first interface chip, the second part of the pins of the F81216E chip is connected to one of the second interface chips, and the third part of the pins of the F81216E chip is connected to the other second interface chip.

[0202] Specifically, the first interface chip can be used to convert the UART signal into an RS232 standard signal, as shown in Figure 69 Figure 70

[0203] Further, the interface integrated circuit further comprises a pin and a jumper cap, as shown in Figure 71 Figure 72

[0204] Specifically, the interface integrated circuit further comprises a first interface chip power supply module, which can be used to supply power for the first interface chip, as shown in Figure 73

[0205] Specifically, the interface integrated circuit further comprises a third LPC signal conversion chip (F75113U) and a GPIO interface.

[0206] ​​​​​​Specifically, the first end of the third LPC signal conversion chip is connected to the fourth end of the serial signal conversion chip, and the second end of the third LPC signal conversion chip is connected to the GPIO interface, and the third LPC signal conversion chip is used for converting the received LPC signal and the GPIO signal adapted to the GPIO interface. That is, the F75113U is used for converting the received LPC signal into the GPIO signal adapted to the GPIO interface, and for converting the received GPIO signal into the LPC signal. The GPIO supports 3V and 5V power supply switching, and realizes the functions of 12 groups of GP_IN and 12 groups of GP_OUT.

[0207] Exemplarily, the processor includes a PCIE port, a SATA3.0 port and a USB2.0 port, and the interface integrated circuit further includes a plurality of USB2.0 interfaces, a plurality of USB3.0 interfaces, a plurality of M.2KEY M interfaces, a SATA interface, a SATA connector (colay), an Ethernet controller chip (Intel I210AT chip) and a plurality of network interfaces.

[0208] The network interface is connected to the PCIE port through the Ethernet controller chip, the M.2KEY M interface is connected to the SATA3.0 port, the SATA interface is connected to the SATA3.0 port through the SATA connector, and the USB2.0 interface and the USB3.0 interface are both connected to the USB2.0 port.

[0209] Specifically, the interface integrated circuit can include ten groups of USB2.0 signals and two groups of USB3.0 signals. The four-way USB2.0 interface is directly connected to the USB port on the CPU, and the four-way USB2.0 interface and the two-way USB3.0 interface are connected to the USB3.0+USB2.0 port, so that the processor can integrate two USB3.0 interfaces and six USB2.0 interfaces.

[0210] The interface integrated circuit provided by the embodiment adopts a MiNi PCIE interface, is connected to the MiNi PCIE interface through a PCIE X1 signal, and can realize WIFI function through a MINIPCIE to WIFI expansion card. The USB2.0 signal of the CPU is connected to the MiNi PCIE interface, and the BT function can be realized through the MINIPCIE to WIFI expansion card.

[0211] Exemplarily, the second LPC signal conversion chip (IT8786E) is further connected with an operating system recovery (OS-RECOVER) button, a remote control (REMOT) button, a power button (PWR Button) and a reset button (Reset Button).

[0212] Specifically, an operating system recovery (OS-RECOVER) button is used to recover the system to a normal operable state in case of operating system failure or crash, etc. A remote control (REMOT) button allows a user to operate the interface integrated device from a remote location through a network, such as remote booting, remote debugging, etc. A power button (PWR Button) is used to turn on or off the power of the device, and a reset button (Reset Button) is used to restart and recover the interface integrated device to an initial state when the interface integrated device has a problem such as freezing or abnormal operation, but does not need to be completely turned off.

[0213] For example, the processor in the embodiment supports the use of fourth generation double data rate synchronous dynamic random access memory (DDR4), and the maximum memory capacity that can be supported is 16 GB.

[0214] The embodiment also provides an interface integrated device, which comprises the interface integrated circuit provided in any of the above embodiments. The interface integrated device can be a live device, a computer host, or other device that needs to be connected to multiple displays or external devices.

[0215] In the description of the present specification, the description of the terms "the embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, the skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0216] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one feature. In the description of the present application, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0217] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope of the present application.

Claims

1. An interface integrated circuit, characterized by comprising: The interface integrated circuit comprises a processor, a plurality of display interfaces, a plurality of serial communication interfaces, a first display signal conversion chip, a second display signal conversion chip, a serial signal conversion chip, a first LPC signal conversion chip, a second LPC signal conversion chip, a first interface chip, a second interface chip and a third interface chip; The plurality of display interfaces comprise an HDMI interface, an LVDS interface, a VGA interface and a DP interface or an EDP interface, and each serial communication interface comprises an RS232 interface, an RS422 interface and an RS485 interface; A first end of the processor is connected to the HDMI interface, a second end of the processor is connected to the DP interface or the EDP interface, a third end of the processor is connected to the LVDS interface through the first display signal conversion chip, and a fourth end of the processor is connected to the VGA interface through the second display signal conversion chip; A fifth end of the processor is connected to a first end of the serial signal conversion chip, a second end of the serial signal conversion chip is connected to a plurality of serial communication interfaces through the first LPC signal conversion chip, the first interface chip and the second interface chip, a third end of the serial signal conversion chip is connected to a first end of the second LPC signal conversion chip, a second end of the second LPC signal conversion chip is connected to a plurality of serial communication interfaces through the third interface chip, and a third end of the second LPC signal conversion chip is connected to a plurality of serial communication interfaces through the first interface chip and the second interface chip; The first display signal conversion chip is configured to convert an EDP signal output by the third end of the processor and an LVDS signal adapted to the LVDS interface, and the second display signal conversion chip is configured to convert a DDI signal output by the fourth end of the processor and a VGA signal adapted to the VGA interface; The serial signal conversion chip is configured to convert an ESPI signal and an LPC signal output by the fifth end of the processor, the first LPC signal conversion chip and the second LPC signal conversion chip are both configured to convert a received LPC signal and a UART signal, and the first interface chip, the second interface chip and the third interface chip are all configured to switch an RS232 interface, an RS422 interface and an RS485 interface.

2. The interface integrated circuit according to claim 1, characterized by Two second interface chips are arranged between the first LPC signal conversion chip and one serial communication interface, and the interface integrated circuit further comprises a pin and a jumper cap; The first interface chip is connected to the RS232 interface through the pin, one second interface chip is connected to the RS422 interface through the pin, another second interface chip is connected to the RS485 interface, and the jumper cap is used to switch the RS232 interface, the RS422 interface and the RS485 interface at different positions on the pin.

3. The interface integrated circuit according to claim 1, characterized by The third interface chip switches the RS232 interface, the RS422 interface and the RS485 interface based on configuration information of BIOS.

4. The interface integrated circuit according to claim 2 or 3, characterized by The serial communication interface is also connected with an electrostatic protection circuit, the electrostatic protection circuit comprising a bidirectional TVS diode and a capacitor; One end of the bidirectional TVS diode and one end of the capacitor are both connected with the serial communication interface, and the other end of the bidirectional TVS diode and the other end of the capacitor are both grounded.

5. The interface integrated circuit according to any one of claims 1 to 3, wherein, The first end of the processor is connected with the HDMI interface in series with a resistor and an inductor.

6. The interface integrated circuit according to any one of claims 1 to 3, wherein, The HDMI interface and the first end of the processor both comprise an HPD pin, the HPD pin of the HDMI interface and the HPD pin of the first end of the processor are connected through an HPD detection circuit, the HPD detection circuit outputs a target electrical signal after the HDMI interface accesses a display device, and the target electrical signal triggers the first end of the processor to output a DDI signal.

7. The interface integrated circuit according to any one of claims 1 to 3, wherein, The interface integrated circuit further comprises a display interface voltage conversion module; One end of the display interface voltage conversion module is connected with the display interface, and the other end is connected with a display device, for converting a signal of a first voltage threshold transmitted by the display device into a signal of a second voltage threshold adapted by the display interface.

8. The interface integrated circuit according to any one of claims 1 to 3, wherein, The interface integrated circuit further comprises a third LPC signal conversion chip and a GPIO interface; The first end of the third LPC signal conversion chip is connected with the fourth end of the serial signal conversion chip, and the second end of the third LPC signal conversion chip is connected with the GPIO interface, and the third LPC signal conversion chip is used for converting an LPC signal received and a GPIO signal adapted by the GPIO interface.

9. The interface integrated circuit according to any one of claims 1 to 3, wherein, The processor comprises a PCIE port, a SATA3.0 port and a USB2.0 port, and the interface integrated circuit further comprises a plurality of USB2.0 interfaces, a plurality of USB3.0 interfaces, a plurality of M.2KEY M interfaces, a SATA interface, a SATA connector, an Ethernet controller chip and a plurality of network interfaces; The network interfaces are connected with the PCIE port through the Ethernet controller chip, the M.2KEY M interfaces are connected with the SATA3.0 port, the SATA interface is connected with the SATA3.0 port through the SATA connector, and the USB2.0 interfaces and the USB3.0 interfaces are both connected with the USB2.0 port.

10. An interface integration device, comprising: The interface integrated device comprises the interface integrated circuit according to any one of claims 1 to 9.

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