Semiconductor packaging structure and semiconductor device

Abstract

The present disclosure relates to a semiconductor package structure and a semiconductor device, the semiconductor package structure comprising: a substrate layer comprising a substrate body having a first cavity and a second cavity; the power adjusting assembly comprises an MOS device and a magnetic core piece, the MOS device is installed in the first cavity, and the magnetic core piece is installed in the second cavity; and the metal layer comprises a coil part which is wound in the circumferential direction of the magnetic core piece. According to the semiconductor packaging structure, the inductor with low cost and high L / R is formed in the semiconductor packaging structure, so that the parasitic inductance can be reduced, and the current requirement can be quickly responded.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor device design and manufacturing, in particular, to a semiconductor package structure and a semiconductor device. BACKGROUND

[0002] In the related art, the power supply of a semiconductor device is usually converted from a higher voltage (12V or 48V) to a lower voltage (0.75-01V) by an adjusting component on a PCB (printed circuit board). When the SOC (chip) of the semiconductor device is high-power, there will be a large current flowing through the PCB (for example, more than 1000A when the power is 1000W). The large current on the printed circuit board will generate high Joule heat, thereby reducing the power delivered to the SOC. In addition, the printed circuit board and the package structure have parasitic inductance, which will delay the power supply to the SOC when the large current increases, resulting in a decrease in the voltage at the SOC bump. Therefore, in order to maintain the circuit function at the same frequency, we need to increase the output voltage of the VRM (voltage regulation module), which will increase the power consumption. SUMMARY

[0003] The purpose of the present disclosure is to provide a semiconductor package structure and a semiconductor device, which forms a low-cost, high L / R inductor inside the semiconductor package structure, thereby reducing parasitic inductance and quickly responding to current demand, to at least partially solve the problems in the related art.

[0004] To achieve the above-mentioned purpose, according to a first aspect of the present disclosure, a semiconductor package structure is provided, comprising:

[0005] a substrate layer comprising a substrate body having a first cavity and a second cavity;

[0006] a power adjusting component comprising a MOS device and a magnetic core, the MOS device being mounted in the first cavity, and the magnetic core being mounted in the second cavity; and

[0007] a metal layer comprising a coil portion arranged circumferentially around the magnetic core.

[0008] Optionally, the substrate body further comprises a third cavity, and the semiconductor package structure further comprises a capacitor mounted in the third cavity.

[0009] Optionally, the capacitor comprises a DTC capacitor and / or a 3D MIM capacitor.

[0010] Optionally, the first cavity and the second cavity are respectively located on two sides of the third cavity.

[0011] Optionally, the substrate body further comprises a plurality of through holes, and the metal layer comprises a first metal layer located in the through holes.

[0012] Optionally, the substrate layer further comprises a plurality of buildups formed on at least one side of the substrate body.

[0013] Optionally, the metal layer further comprises a second metal layer located on the plurality of buildups.

[0014] Optionally, the semiconductor package structure further comprises an isolation layer formed on a side of the buildup away from the substrate body, and the isolation layer is formed with a pad electrically connected with the metal layer.

[0015] Optionally, the substrate body is glass.

[0016] Optionally, the semiconductor package structure further comprises a chip element located above the substrate body.

[0017] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising the semiconductor package structure as described above.

[0018] By the above technical solution, i.e. the semiconductor package structure of the present disclosure, comprising a substrate layer, a power regulation component and a metal layer, by embedding the power regulation component into the substrate body of the semiconductor package structure, i.e. mounting the MOS device and the magnetic core element into the first cavity and the second cavity of the substrate body respectively, and forming a coil part located in the circumference of the magnetic core element on the metal layer to form an inductor. Through the above arrangement, the semiconductor package structure of the present disclosure forms an inductor with low cost and high L / R inside the semiconductor package structure, which is conducive to reducing the parasitic inductance and can quickly respond to the current demand.

[0019] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the following detailed description, serve to explain the present disclosure. In the drawings:

[0021] Figure 1 is a connection structure diagram of a semiconductor package structure and a PCB in the related art.

[0022] Figure 2 is a power supply principle diagram of a semiconductor package structure in the related art.

[0023] Figure 3 is a structure diagram of a semiconductor package structure provided by some embodiments of the present disclosure.

[0024] Figure 4 is a connection structure diagram of a semiconductor package structure and a PCB provided by some embodiments of the present disclosure.

[0025] Figures 5 to 16 is a flow chart of a preparation process of the semiconductor package structure provided by some embodiments of the present disclosure.

[0026] Legend of Reference Signs

[0027] 10 - semiconductor package structure; 20 - inductor; 30 - MOS device; 40 - PCB board; 41 - core power supply line; 42 - backhaul ground line;

[0028] 110 - substrate body; 111 - first cavity; 112 - second cavity; 113 - third cavity; 114 - through hole; 115 - glue; 116 - second copper plating layer; 120 - build-up layer; 130 - metal layer; 130a - first copper plating layer; 131 - coil part; 132 - first metal layer; 133 - second metal layer; 140 - isolation layer; 150 - pad;

[0029] 200 - magnetic core piece; 300 - MOS device; 400 - DTC capacitor; 500 - chip piece. DETAILED DESCRIPTION

[0030] The detailed description of the specific embodiments of the present disclosure is described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0031] In the present disclosure, the orientation words such as "up, down, left, right" used without the opposite description generally refer to the up, down, left, right of the corresponding drawings; "inner, outer" refers to the contour of the corresponding parts. The terms "first", "second" and the like used in the present disclosure are used to distinguish one element from another element, and do not have sequential and important meanings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated.

[0032] As Figure 1 and Figure 2The diagram shows the connection structure between the semiconductor package structure 10 and the PCB board 40 in the related technology, illustrating the power supply for the semiconductor package structure. The semiconductor device is typically powered by a regulating component (including MOS device 30 and inductor 20) on the PCB board 40 (printed circuit board), which converts a higher voltage (12V or 48V) to a lower voltage (0.75-0.1V), and supplies it to the semiconductor package structure 10 (Vdd) through the core power supply line 41. Simultaneously, the Vss of the semiconductor package structure 10 is connected to the return ground line 42 of the PCB board 40. When the chip 500 (e.g., SOC) of the semiconductor package structure 10 is high-power, a large current will flow through the PCB board 40 (e.g., greater than 1000A for 1000W power). High current on a printed circuit board generates high Joule heat, which reduces the power delivered to the SOC (System-on-a-Chip). In addition, the printed circuit board and package structure have parasitic inductance, which delays power supply to the SOC when the current increases, causing the voltage at the SOC bump to drop. Therefore, in order to maintain circuit function at the same frequency, we need to increase the output voltage of the VRM (Voltage Regulator Module), which increases power consumption.

[0033] To achieve the above objectives, such as Figures 3 to 16 As shown, according to a first aspect of this disclosure, a semiconductor package structure is provided, the semiconductor package structure including a substrate layer, a power conditioning component, and a metal layer 130. The substrate layer includes a substrate body 110 having a first cavity 111 and a second cavity 112; the power conditioning component includes a MOS device 300 and a magnetic core 200, the MOS device 300 being mounted in the first cavity 111, the magnetic core 200 being mounted in the second cavity 112, and the metal layer 130 including a coil portion 131 wound circumferentially around the magnetic core 200, capable of cooperating with the magnetic core 200 to form a low-cost, high L / R inductor.

[0034] The semiconductor packaging structure disclosed herein, comprising a substrate layer, a power regulation component, and a metal layer 130, incorporates the power regulation component within the substrate body 110 of the semiconductor packaging structure. Specifically, the MOS device 300 and the magnetic core 200 are respectively mounted within the first cavity 111 and the second cavity 112 of the substrate body 110. A coil portion 131 circumferentially located within the magnetic core 200 is formed in the metal layer 130 to create an inductor. Through this configuration, the semiconductor packaging structure of this disclosure, by forming a low-cost, high-L / R inductor within the semiconductor packaging structure, facilitates the reduction of parasitic inductance and enables rapid response to current demands. Furthermore, corresponding to higher-power chips 500, a high voltage (relative to 0.75-0.1V) can be provided on the PCB substrate, and the initial voltage can be reduced from 12V to 3-4.8V. Figure 4As shown, the circuit between the core power supply line and the backhaul ground line can be 12V, 48V, or reduced to 3-5V. For example, the voltage at the connection between the PCB and Vdd can be 3-12V.

[0035] It should be noted that the metal layer 130 also includes a first metal layer 132 and a second metal layer 133, wherein the first metal layer 132 is located in the through hole 114 of the substrate body 110 and penetrates the upper and lower parts of the substrate body 110 to realize electrical connection on both sides; and the second metal layer 133 is formed between the plurality of laminates 120 and used to connect the MOS device 300, the capacitor, the PCB (printed circuit board), and the SOC (chip 500), which will be described in detail in the following embodiments.

[0036] In some embodiments, the substrate body 110 includes but is not limited to a glass substrate, and can also be a substrate body 110 of other materials.

[0037] Optionally, the substrate body 110 also includes a third cavity 113, and the semiconductor package structure also includes a capacitor mounted in the third cavity 113. The capacitor includes a DTC capacitor 400 and / or a 3D MIM capacitor. Under the premise that the substrate body 110 is a glass substrate, since the DTC capacitor 400 and / or the 3D MIM capacitor used has a thermal expansion coefficient close to that of the glass substrate, the stress of the capacitor can be reduced, the risk of cracking can be reduced, and the reliability can be increased.

[0038] It should be noted that the substrate body 110 can also adopt other substrate structures, and the capacitor can also be other forms of capacitors.

[0039] The positions of the first cavity 111, the second cavity 112, and the third cavity 113 can be arranged in any suitable manner. In some embodiments, the first cavity 111 and the second cavity 112 are respectively located on both sides of the third cavity 113. Therefore, the MOS device 300 in the first cavity 111, the magnetic core 200 in the second cavity 112, and the capacitor in the third cavity 113 can be arranged in sequence, so that the current passes through the MOS device 300, then passes through the inductor formed by the magnetic core 200 and the coil part 131, and then reaches the capacitor, thereby reducing the length of the metal layer 130 and saving space. Of course, the first cavity 111 and the second cavity 112 can also be arranged in other ways, as long as the power supply connection can be met and the inductor formed by the magnetic core 200 and the coil part 131 can be arranged on the power supply line.

[0040] In some embodiments, the substrate body 110 is further formed with a plurality of through holes 114 penetrating through opposite sides of the substrate body 110, and a first metal layer 132 is formed in the through holes 114, the first metal layer 132 acting as a part of the metal layer 130 and being used for electrical connection of both sides of the substrate body 110. The first metal layer 132 can be made of copper, for example. The first metal layer 132 can be formed by plating copper and using photolithography and etching.

[0041] As shown in FIG. 1, the number of the through holes 114 is five, one of which is located on the left side of the MOS device 300 and used for connection with the Vdd pad 150, one of which is located between the MOS device 300 and the magnetic core 200, one of which is located between the magnetic core 200 and the DTC capacitor 400 and forms two ends of the coil 131, and two of which are located on the right side of the DTC capacitor 400, one of which is used for connection between the DTC capacitor 400 and the Vss pad 150, and the other of which is used for signal connection between the PCB and the SOC. Figure 16

[0042] In some embodiments, the semiconductor package structure includes a plurality of buildups 120 arranged on at least one side of the substrate body 110. In general, a plurality of buildups 120 are arranged on both sides of the substrate body 110, and a plurality of second metal layers 133 are sequentially arranged between the buildups 120 to realize electrical connection with the pads 150 on the outermost buildups 120.

[0043] It can be understood that the buildup 120 can adopt a structure layer and arrangement known in the related art, for example, the buildup 120 can be an ABF layer (Ajinomoto Build-up Film Layer).

[0044] In order to realize connection with the chip 500, in some embodiments, the metal layer 130 further includes a second metal layer 133 formed between the buildups 120, the second metal layer 133 in the buildups 120 above the substrate body 110 being used for connection with the chip 500 (e.g., the SOC), and the second metal layer 133 in the buildups 120 below the substrate body 110 being used for connection with the PCB to realize power supply, grounding and signal communication.

[0045] ​Optionally, the semiconductor package structure further comprises an isolation layer 140 formed on the side of the build-up layer 120 away from the substrate body 110, and the isolation layer 140 is formed with a pad 150 connected with the second metal layer 133. The pad 150 can be formed by laser drilling a window in the isolation layer 140 and forming the pad 150 in the window, and the pad 150 is electrically connected with the second metal layer 133. The build-up layer 120 can be a multi-layer structure, and the second metal layer 133 can be multiple, and distributed among the multiple build-up layers 120, and the electrical connection of the multiple second metal layers 133 can be achieved by arranging a via hole 114 in each build-up layer 120 and forming a metal conductive layer in the via hole 114.

[0046] As shown in Figure 3 and Figure 4 In some embodiments of the present disclosure, the semiconductor package structure further comprises a chip piece 500 above the substrate layer. The chip piece 500, such as a SOC, can be connected by welding with the pad 150 above the substrate layer.

[0047] It can be understood that the capacitor piece is inside the cavity of the substrate body 110 below the chip piece 500, for example, directly below, and such an arrangement enables the chip piece 500 to be vertically connected with the capacitor piece, and the ESL and ESR from the capacitor piece to the pad 150 of the chip piece 500 above will be much lower, and the AC noise will be reduced.

[0048] According to a second aspect of the present disclosure, a semiconductor device is provided, which comprises the semiconductor package structure described above, and therefore, the semiconductor device also has all the advantages of the semiconductor package structure described above, which will not be repeated here.

[0049] As shown in Figures 5 to 16 According to a third aspect of the present disclosure, a method for manufacturing a semiconductor package structure is also provided, which comprises the following steps:

[0050] Providing a substrate body 110.

[0051] Forming a first cavity 111 and a second cavity 112 in the substrate body 110.

[0052] Embedding a MOS device 300 in the first cavity 111 and embedding a magnetic core piece 200 in the second cavity 112.

[0053] Forming a metal layer 130 comprising a coil portion 131 wound around the magnetic core piece 200.

[0054] The preparation method of the present disclosure forms the first cavity 111 and the second cavity 112 on the substrate body 110, and embeds the MOS device 300 and the magnetic core 200 into the first cavity 111 and the second cavity 112 respectively, and then forms the metal layer 130, wherein the metal layer 130 includes the coil part 131 arranged around the magnetic core 200 in the circumferential direction, and the coil part 131 and the magnetic core 200 in the second cavity 112 form an inductor. By the above method, an inductor with low cost and high L / R can be formed inside the semiconductor package structure to reduce parasitic inductance and quickly respond to current demand.

[0055] In order to also embed the capacitor inside the substrate body 110, as shown in some embodiments, the method further includes: Figure 7

[0056] Forming a third cavity 113 in the substrate body 110.

[0057] Embedding a capacitor in the third cavity 113.

[0058] Among them, the first cavity 111 can be formed first, then the magnetic core 200 is embedded in the first cavity 111, and then the second cavity 112 and the third cavity 113 are formed. In addition, the third cavity 113 and the first cavity 111 and the second cavity 112 can be formed together on the glass substrate by laser or etching. The capacitor can be a DTC capacitor 400 and / or a 3D MIM capacitor. Those skilled in the art can assign the order of forming the first cavity 111, the second cavity 112 and the third cavity 113 and installing the magnetic core 200, the MOS device 300 and the capacitor in any way as long as it can be implemented. Here, it will not be repeated.

[0059] In order to realize the electrical connection or signal connection on both sides of the substrate body 110, as shown in some embodiments, the method can further include: Figure 7

[0060] Forming a through hole 114 in the substrate body 110.

[0061] Copper plating is performed on the through hole 114 or the sidewall of the through hole 114 to form a first metal layer 132 penetrating through both sides of the substrate body 110.

[0062] Among them, the through hole 114 can also be formed in one step with the first cavity 111, the second cavity 112 and the third cavity 113, and then the first metal layer 132 is formed in the through hole 114 by removing the copper plating on the surface of the substrate body 110 through copper plating, photolithography and etching.

[0063] ​​It is to be noted that in some embodiments, the method further comprises, after the steps of embedding the MOS device 300 in the first cavity 111 and embedding the magnetic core 200 in the second cavity 112, forming a build-up layer 120 on the substrate body 110. Forming a metal layer 130 on the build-up layer 120, the metal layer 130 comprising a coil portion 131 wound around the magnetic core 200. By the above method, the first cavity 111 and the second cavity 112 are formed on the substrate body 110, and the MOS device 300 and the magnetic core 200 are embedded in the first cavity 111 and the second cavity 112 respectively, then the build-up layer 120 is formed on the substrate body 110, and the metal layer 130 is formed on the build-up layer 120, wherein the metal layer 130 comprises the coil portion 131 wound around the magnetic core 200, the coil portion 131 and the magnetic core 200 in the second cavity 112 form an inductor, by the above method, an inductor with lower cost and higher L / R inside the semiconductor package structure can be formed to reduce the parasitic inductance and quickly respond to the current demand.

[0064] In some embodiments, the step of forming the metal layer comprising the coil portion wound around the magnetic core comprises:

[0065] After embedding the MOS device 300, the magnetic core 200 and the capacitor in the first cavity 111, the second cavity 112 and the third cavity 113 of the substrate body 110 respectively, one or more build-up layers 120 are formed on the side of the substrate body 110.

[0066] The metal layer 130 is formed on the build-up layer 120 to connect the MOS device 300 and the capacitor.

[0067] The specific steps include, after embedding the MOS device 300, the magnetic core 200 and the capacitor, as shown in Figure 12 and Figure 13 first, two build-up layers 120 are formed on both sides of the substrate body 110 respectively, and the metal layer 130 is formed on the surface of the build-up layer 120 by drilling and metallization; then the metal layer 130 structure of connecting the first metal layer 132 with the MOS device 300, the MOS device 300 with one end of the coil portion 131, the other end of the coil portion 131 with the first metal layer 132, the first metal layer 132 with the DTC capacitor 400, and the DTC capacitor 400 with the first metal layer 132 on the right side is formed by photolithography and etching to realize the connection of the MOS device 300 and the DTC capacitor 400. The upper and lower parts of the first metal layer 132 at the rightmost via hole 114 form metal connection parts respectively.

[0068] Finally, as shown in Figure 14 the step of forming the build-up layer 120 is repeated to multiple layers, and the second metal layer 133 is formed between the multiple build-up layers 120 by metallization process.

[0069] As shown in Figure 15 In some embodiments, the method further comprises:

[0070] An isolation layer 140 is formed on the side of the build-up layer 120 away from the substrate body 110.

[0071] A pad 150 is formed on the isolation layer 140.

[0072] The isolation layer 140 formed on the build-up layer 120 is mainly used to isolate the pad 150 formed in the following step from penetrating into the build-up layer 120, and can be made of any suitable material known in the related art. A window of the pad 150 is formed by photoetching and etching the isolation layer 140, and the pad 150 is formed by pre-pad printing and reflow soldering at the window of the pad 150, and the pad 150 is connected to the second metal layer 133.

[0073] As shown in Figure 16 In some embodiments, the method further comprises:

[0074] A chip piece 500 is provided.

[0075] The chip piece 500 is connected to the pad 150.

[0076] The chip piece 500 can be a SOC chip, and the chip piece 500 is connected to the pad 150 on the substrate, so as to realize chip assembly. It should be noted that the pad 150 on the other side of the substrate body 110 away from the chip piece 500 is used to connect to a PCB board, including but not limited to core power supply, grounding and signal connection.

[0077] Referring to Figures 5 to 16 The manufacturing process of the semiconductor packaging structure is described in detail by using one specific embodiment.

[0078] As shown in Figure 5 A glass substrate is provided, and a first cavity 111 is formed on the glass substrate.

[0079] As shown in Figure 6 A magnetic core piece 200 is embedded in the first cavity 111.

[0080] As shown in Figure 7 A second cavity 112, a third cavity 113 and a plurality of through holes 114 are formed on the glass substrate.

[0081] As shown in Figure 8 A first copper plating layer 130a is formed on the surface of the glass substrate, the sidewalls of the second cavity 112, the third cavity 113 and the plurality of through holes 114.

[0082] As shown in Figure 9As shown, the MOS device 300 is embedded in the second cavity 112, the DTC capacitor 400 is embedded in the third cavity 113, and the gap between the components and the side wall is filled with glue 115.

[0083] As shown, the copper plating on the surface of the glass substrate is removed by means of patterning or mechanical polishing to form the first metal layer 132 in the via hole 114. Figure 10

[0084] As shown, the second copper plating layer 116 is formed on the surface of the glass substrate by copper plating, and the second copper plating layer 116 on the surface of the glass substrate is removed by means of patterning or mechanical polishing, leaving the second copper plating layer 116 corresponding to the connection ends of the first metal layer 132, the MOS device 300 and the DTC capacitor 400. Figure 11

[0085] As shown, an ABF layer is formed on the upper surface and the lower surface of the glass substrate body 110, respectively. Figure 12

[0086] As shown, the openings corresponding to the via hole 114 and the DTC capacitor 400 are formed in the ABF layer by laser drilling, and a copper plating layer is formed in the ABF layer and the openings; then the metal layer 130 is formed by means of patterning, or photoetching and etching, to connect the MOS device 300 and the DTC capacitor 400, and to form the coil part 131 in the circumferential direction of the magnetic core part 200. Figure 13

[0087] As shown, the ABF layer and the copper circuit (copper plating layer metallization) are repeatedly formed, and the cycle is repeated up to a plurality of layers. Figure 14

[0088] As shown, the isolation layer 140 (SR Coating) is formed on the surface of the outermost ABF layer; the pad 150 window is formed by photoetching and etching the isolation layer 140 (SR Coating); and the pad 150 is formed at the corresponding pad 150 window by pre-solder printing and reflow soldering. Figure 15

[0089] As shown, the SOC chip is soldered to the pad 150. Figure 16

[0090] ​​​​​​​The semiconductor package structure and semiconductor device of the present disclosure embed the magnetic core 200 in the glass substrate, and use the through hole 114 (TGV, Through Glass Via) and RDL (Redistribution layer) process, such as the metal layer 130, to form a high L / R, low cost inductor in the semiconductor package structure; at the same time, the switching MOS device 300 is embedded in the glass substrate, and since the thermal expansion coefficient of the glass substrate is close to that of silicon, the thermal stress can be reduced, and the risk of cracking of the MOS device 300 can be reduced. At the same time, the capacitor (such as the DTC capacitor 400 or the 3D MIM capacitor) is embedded in the glass substrate, and the capacitor has a low ESL (equivalent series inductance) and ESR (equivalent series resistance), which can quickly respond to system requirements and reduce AC noise when the circuit is turned on and off. In addition, when a larger power-ready SOC is required, a high voltage (relative to 0.75-1V in the related art) can be provided on the PCB substrate surface, and the initial voltage can be reduced from 12V to 3-4.8V.

[0091] The preferred embodiments of the present disclosure are described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0092] In addition, it should be noted that various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again in the present disclosure.

[0093] In addition, various different embodiments of the present disclosure can also be combined in any appropriate manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A semiconductor package structure, comprising: The semiconductor package structure comprises: a substrate layer comprising a substrate body having a first cavity and a second cavity; a power regulation component comprising a MOS device and a magnetic core, the MOS device being mounted in the first cavity, and the magnetic core being mounted in the second cavity; and a metal layer comprising a coil portion circumferentially arranged around the magnetic core. The substrate body further comprises a third cavity, and the semiconductor package structure further comprises a capacitor mounted in the third cavity.

2. The semiconductor package structure of claim 1, wherein, The capacitor comprises a DTC capacitor and / or a 3D MIM capacitor.

3. The semiconductor package structure of claim 2, wherein, The first cavity and the second cavity are respectively located on two sides of the third cavity.

4. The semiconductor package structure of claim 2, wherein, The substrate body further comprises a plurality of through holes, and the metal layer comprises a first metal layer located in the through holes.

5. The semiconductor package structure of claim 1, wherein, The substrate layer further comprises a plurality of buildups formed on at least one side of the substrate body.

6. The semiconductor package structure of claim 1, wherein, The metal layer further comprises a second metal layer located in the plurality of buildups.

7. The semiconductor package structure of claim 6, wherein, The semiconductor package structure further comprises an isolation layer formed on a side of the buildup away from the substrate body, and the isolation layer is formed with a pad electrically connected with the metal layer.

8. The semiconductor package structure of claim 6, wherein, The substrate body is made of glass.

9. The semiconductor package structure of any one of claims 1-8, wherein, The semiconductor package structure further comprises a chip mounted on the substrate layer.

10. The semiconductor package structure of any one of claims 1-8, wherein, The semiconductor package structure according to any one of claims 1-10.

11. A semiconductor device, characterized by comprising: ​

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