Semiconductor device capable of reducing on-resistance value
By using a metal frame and metal sheet to connect chip electrodes in semiconductor devices, the problems of large area and high electrical loss in traditional packaging are solved, achieving more efficient electrical transmission and chip protection.
Patent Information
- Application Number
- CN202423314864.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In traditional multi-chip packaging, side-by-side chip arrangement occupies a large area, stacking leads to increased electrical transmission loss, and lead connections may cause chip damage.
Two chips are fixed with a metal frame and connected to the chip electrodes with a metal sheet to achieve a common source design, which reduces electrical transmission loss and avoids wire bonding process losses.
It achieves a semiconductor device design that is compact, reduces electrical transmission loss, and minimizes chip loss.
Smart Images
Figure CN223712766U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, especially to the semiconductor device of reducing on resistance. BACKGROUND
[0002] The chips in the conventional multi-chip package are arranged in a side-by-side manner, which requires a large packaging area. With the development of semiconductor miniaturization technology, the packaging size is reduced, and the chips in the multi-chip package are arranged in a stacked manner. In order to avoid the chip stack being too high, the thickness of the chip is designed to be between 2 and 4 mils. In the stacked chip package, the two chips are mainly connected in the same direction by lead, clip or TVS technology. The connection by lead not only increases the electrical transmission loss, but also may cause certain chip loss during the wire bonding process. SUMMARY
[0003] The utility model provides a compact structure, reduce the semiconductor device of electrical transmission loss, reduce chip loss.
[0004] The technical scheme of the utility model is:
[0005] The semiconductor device for reducing on resistance comprises:
[0006] A metal frame;
[0007] A first chip is fixedly arranged on the top surface of the metal frame;
[0008] A second chip is arranged on the top of the first chip;
[0009] A first metal sheet is arranged between the first chip and the second chip and is electrically connected to the source of the first chip and the source of the second chip respectively;
[0010] A second metal sheet is arranged between the first chip and the second chip and is electrically connected to the gate of the first chip and the gate of the second chip respectively;
[0011] A third metal sheet is electrically connected to the drain of the second chip at one end and to the metal frame at the other end.
[0012] Specifically, the metal frame is a copper frame.
[0013] Specifically, the drain of the first chip is fixedly connected to the metal frame.
[0014] Specifically, the utility model further comprises a plastic package body;
[0015] The plastic package body is wrapped around the metal frame, the first chip, the second chip, the first metal sheet, the second metal sheet and the third metal sheet.
[0016] The bottom surface of the metal frame, the bottom surface of the first metal sheet and the bottom surface of the second metal sheet are respectively exposed from inside the plastic package.
[0017] Specifically, the first chip and the second chip are same type chips.
[0018] Specifically, the source and the gate of the first chip are symmetrically distributed.
[0019] Specifically, the bottom surface of the first metal sheet and the bottom surface of the second metal sheet are in the same plane.
[0020] Specifically, the bottom surface of the first metal sheet and the bottom surface of the metal frame are in the same plane.
[0021] The second chip and the first chip are stacked in a positive-negative and electrode-to-electrode mode, the electrodes between the chips are connected through the first metal sheet and the second metal sheet, and the product design of common source is achieved. Compared with the connection of the lead wire, the contact area between the chips is increased, the power transmission loss is reduced, and the chip loss caused by the wire bonding process is avoided. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 is a schematic diagram of the three-dimensional structure of the utility model,
[0023] Figure 2 is a packaging schematic diagram, the third metal sheet is arranged to be deviated in position, mainly for better showing the connection position of the upper and lower ends;
[0024] Figure 3 is a first chip structure one schematic diagram;
[0025] Figure 4 is a first chip structure two schematic diagram;
[0026] Figure 5 is a first chip structure three schematic diagram;
[0027] In the figure, 100 is a metal frame, 200 is a first chip, 300 is a second chip, 400 is a first metal sheet, 500 is a second metal sheet, 600 is a third metal sheet, and 700 is a plastic package. DETAILED DESCRIPTION
[0028] The embodiments of the utility model are described in detail below, examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary, only for explaining the utility model, and cannot be understood as limiting the utility model.
[0029] In the description of the utility model, it is necessary to understand that the orientation or position relation indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like is the orientation or position relation based on the drawing shown, and is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the utility model. In the description of the utility model, unless otherwise specified, the meaning of "a plurality of" is two or more than two.
[0030] In the description of the utility model, it should be explained that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected, it can be mechanical connection, or electrical connection, it can be directly connected, or indirectly connected through intermediate medium, it can be the communication inside two elements. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0031] The following refers to Figures 1-5 The utility model is described;
[0032] The semiconductor device with reduced on-resistance comprises:
[0033] The metal frame 100 is a copper frame;
[0034] The first chip 200 is fixedly arranged on the top surface of the metal frame 100, and the drain electrode of the first chip 200 is fixedly connected with the metal frame 100;
[0035] The second chip 300 is arranged on the top of the first chip 200;
[0036] The first metal sheet 400 is located between the first chip 200 and the second chip 300 and is electrically connected with the source electrode (S) of the first chip 200 and the source electrode (G) of the second chip 300 respectively;
[0037] The second metal sheet 500 is arranged between the first chip 200 and the second chip 300 and is electrically connected with the gate electrode of the first chip 200 and the gate electrode of the second chip 300 respectively;
[0038] The third metal sheet 600 is electrically connected with the drain electrode of the second chip 300 at one end and is electrically connected with the metal frame 100 at the other end.
[0039] The second chip 300 is stacked with the first chip 200 in a positive-negative electrode-to-electrode mode, and the electrodes between the chips are connected through the first metal sheet 400 and the second metal sheet 500 to achieve a common-source product design. The stacking architecture increases the contact area between the chips compared to the general stacking, which can reduce the power loss of the electrical transmission compared to the wire connection, and at the same time avoids the chip loss caused by the wire bonding process.
[0040] Because the chips are electrode-end adhered to each other, and the two chips are connected through the metal sheets on the back, there is no need to encapsulate the glue on the back of the chip as in the general stacking package.
[0041] The plastic package 700 is wrapped on the metal frame 100, the first chip 200, the second chip 300, the first metal sheet 400, the second metal sheet 500, and the third metal sheet 600.
[0042] The bottom surface of the metal frame 100, the bottom surface of the first metal sheet 400, and the bottom surface of the second metal sheet 500 are respectively exposed from the plastic package 700.
[0043] The bottom surface of the first metal sheet 400 and the bottom surface of the second metal sheet 500 are in the same plane.
[0044] The bottom surface of the first metal sheet 400 and the bottom surface of the second metal sheet 500 are in the same plane.
[0045] The first chip 200 and the second chip 300 are respectively the same type of chip. The source and the gate of the first chip 200 are respectively symmetrically distributed, as shown in Figures 4-5 .
[0046] For the disclosed content, the following points need to be explained:
[0047] (1) The disclosed embodiment drawings only involve the structure involved in the disclosed embodiment, and other structures can refer to the general design.
[0048] (2) In the case of no conflict, the disclosed embodiments and the features in the embodiments can be combined to obtain new embodiments.
[0049] The above is only a specific implementation of the disclosure, but the protection scope of the disclosure is not limited thereto, and the protection scope of the disclosure should be subject to the protection scope of the claims.
Claims
1. A semiconductor device for reducing on-resistance, characterized by, The application relates to a chip packaging structure, which comprises the following parts: a metal frame (100); a first chip (200) fixedly arranged on the top surface of the metal frame (100); a second chip (300) arranged on the top of the first chip (200); a first metal sheet (400) arranged between the first chip (200) and the second chip (300) and electrically connected with the source electrode of the first chip (200) and the source electrode of the second chip (300) respectively; a second metal sheet (500) arranged between the first chip (200) and the second chip (300) and electrically connected with the gate electrode of the first chip (200) and the gate electrode of the second chip (300) respectively; a third metal sheet (600) electrically connected with the drain electrode of the second chip (300) at one end and electrically connected with the metal frame (100) at the other end.
2. The low on-resistance semiconductor device of claim 1, wherein The metal frame (100) is a copper frame.
3. The low on-resistance semiconductor device of claim 1, wherein The drain electrode of the first chip (200) is fixedly connected with the metal frame (100).
4. The low on-resistance semiconductor device of claim 1, wherein The application further comprises a plastic sealing body (700); the plastic sealing body (700) is wrapped on the metal frame (100), the first chip (200), the second chip (300), the first metal sheet (400), the second metal sheet (500) and the third metal sheet (600); the bottom surface of the metal frame (100), the bottom surface of the first metal sheet (400) and the bottom surface of the second metal sheet (500) are exposed from the plastic sealing body (700) respectively.
5. The low on-resistance semiconductor device of claim 1, wherein The first chip (200) and the second chip (300) are chips of the same type.
6. The low on-resistance semiconductor device of claim 5, wherein, The source electrode and the gate electrode of the first chip (200) are symmetrically distributed respectively.
7. The low on-resistance semiconductor device of claim 1, wherein The bottom surface of the first metal sheet (400) and the bottom surface of the second metal sheet (500) are in the same plane.
8. The low on-resistance semiconductor device of claim 1, wherein, The bottom surface of the first metal sheet (400) and the bottom surface of the metal frame (100) are in the same plane.