Semiconductor element

Abstract

A semiconductor device is disclosed. The substrate has a first semiconductor fin on the first region and a second semiconductor fin on the second region, and the first semiconductor fin and the second semiconductor fin are in contact with each other in the dislocation region. A dummy gate within or adjacent to the dislocation region is removed to expose a portion of the first semiconductor fin and form an insulating space. An etch is performed to remove the exposed portion of the first semiconductor fin and form a trench in the substrate. The trench and the insulating space are filled with at least one dielectric material to form an electrically insulating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrical conductor material to form two adjacent transistors that are electrically insulated from each other.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] Integrated circuits are formed on semiconductor wafers. A lithographic patterning process uses ultraviolet light to transfer a desired mask pattern to a photoresist on a semiconductor wafer. Etching is then used to transfer the pattern to a layer underneath the photoresist. This process is repeated multiple times using different patterns to build up different layers on the wafer substrate and fabricate useful devices. SUMMARY

[0003] According to at least one embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an erase region, a dielectric insulating structure between the first region and the second region in or adjacent to the erase region.

[0004] According to at least one embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an erase region, wherein the first semiconductor fin has a larger width than the second semiconductor fin, a dielectric insulating structure between the first region and the second region in or adjacent to the erase region.

[0005] According to at least one embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an erase region, wherein the first semiconductor fin and the second semiconductor fin are offset from each other, a dielectric insulating structure between the first region and the second region in or adjacent to the erase region. BRIEF DESCRIPTION OF DRAWINGS

[0006] The nature of the present disclosure will be appreciated as the detailed description proceeds, and in part will become apparent when considered in connection with the accompanying drawings. It is to be understood that various features are not necessarily drawn to scale in the drawings. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figure 1 is a flowchart of a method of preparing a patterned photoresist layer of a semiconductor device and etching a layer of the semiconductor device according to some embodiments;

[0008] Figures 2A-2E At the beginning Figure 1 Before the method, schematic diagrams of the partially completed substrate from different perspectives; Figure 2A It is a floor plan; Figure 2B The substrate is along Figure 2A A schematic diagram of the first X-axis of line segment X1-X1; Figure 2C The substrate is along Figure 2A A schematic diagram of the second X-axis of line segment X2-X2; Figure 2D The substrate is along Figure 2A A schematic diagram of the first Y-axis of line segment Y1-Y1; Figure 2E The substrate is along Figure 2A A schematic diagram of the second Y-axis of line segment Y2-Y2;

[0009] Figures 3A-3D This is a schematic diagram of the substrate from different perspectives after the hard mask layer and the patterned layer have been applied; Figure 3A The substrate is along Figure 2A A schematic diagram of the first X-axis of line segment X1-X1; Figure 3B The substrate is along Figure 2A A schematic diagram of the second X-axis of line segment X2-X2; Figure 3C The substrate is along Figure 2A A schematic diagram of the first Y-axis of line segment Y1-Y1; Figure 3D The substrate is along Figure 2A A schematic diagram of the second Y-axis of line segment Y2-Y2;

[0010] Figures 4A-4D This is a schematic diagram of the substrate from different angles after the patterned hard mask layer has been applied. Figure 4A The substrate is along Figure 2A A schematic diagram of the first X-axis of line segment X1-X1; Figure 4B The substrate is along Figure 2A A schematic diagram of the second X-axis of line segment X2-X2; Figure 4C The substrate is along Figure 2A A schematic diagram of the first Y-axis of line segment Y1-Y1; Figure 4D The substrate is along Figure 2A A schematic diagram of the second Y-axis of line segment Y2-Y2;

[0011] Figures 5A-5D This is a schematic diagram of the substrate from different perspectives after the exposed dummy gate has been removed; Figure 5A The substrate is along Figure 2A A schematic diagram of the first X-axis of line segment X1-X1; Figure 5B The substrate is along Figure 2A A schematic diagram of the second X-axis of line segment X2-X2; Figure 5C The substrate is along Figure 2A A schematic diagram of the first Y-axis of line segment Y1-Y1; Figure 5D The substrate is alongFigure 2A schematic view of the second Y-axis of the line segment Y2-Y2;

[0012] Figures 6A-6D schematic view of the substrate from different perspectives after the exposed dummy oxide is removed to obtain an insulating space; Figure 6A is a schematic view of the substrate along Figure 2A the first X-axis of the line segment X1-X1;

[0013] Figure 6B is a schematic view of the substrate along Figure 2A the second X-axis of the line segment X2-X2; Figure 6C is a schematic view of the substrate along Figure 2A the first Y-axis of the line segment Y1-Y1; Figure 6D is a schematic view of the substrate along Figure 2A the second Y-axis of the line segment Y2-Y2;

[0014] Figures 7A-7D schematic view of the substrate from different perspectives after the exposed portion of the semiconductor fin is removed to form a trench in the substrate; Figure 7A is a schematic view of the substrate along Figure 2A the first X-axis of the line segment X1-X1; Figure 7B is a schematic view of the substrate along Figure 2A the second X-axis of the line segment X2-X2; Figure 7C is a schematic view of the substrate along Figure 2A the first Y-axis of the line segment Y1-Y1; Figure 7D is a schematic view of the substrate along Figure 2A the second Y-axis of the line segment Y2-Y2;

[0015] Figures 8A-8D schematic view of the substrate from different perspectives after the trench and the insulating space are filled with a dielectric material to form an electrically insulating structure; Figure 8A is a schematic view of the substrate along Figure 2A the first X-axis of the line segment X1-X1; Figure 8B is a schematic view of the substrate along Figure 2A the second X-axis of the line segment X2-X2; Figure 8C is a schematic view of the substrate along Figure 2A the first Y-axis of the line segment Y1-Y1; Figure 8D is a schematic view of the substrate along Figure 2A the second Y-axis of the line segment Y2-Y2;

[0016] Figures 9A-9E schematic view of the substrate from different perspectives after the planarization step; Figure 9A is a plan view with the line segment X1-X1, the line segment X2-X2, the line segment Y1-Y1 and the line segment Y2-Y2 as Figure 2A depicted again; Figure 9Bis a schematic view of the substrate along the first X-axis of the line segment X1-X1 ; Figure 9C is a schematic view of the substrate along the second X-axis of the line segment X2-X2; Figure 9D is a schematic view of the substrate along the first Y-axis of the line segment Y1-Y1 ; Figure 9E is a schematic view of the substrate along the second Y-axis of the line segment Y2-Y2;

[0017] Figures 10A-10D is a schematic view of the substrate at different perspectives after the dummy gates and the sacrificial layers exposed in the semiconductor fins are removed; Figure 10A is a schematic view of the substrate along the first X-axis of the line segment X1-X1 ; Figure 9A is a schematic view of the substrate along the first X-axis of the line segment X1-X1 ; Figure 10B is a schematic view of the substrate along the second X-axis of the line segment X2-X2; Figure 9A is a schematic view of the substrate along the second X-axis of the line segment X2-X2; Figure 10C is a schematic view of the substrate along the first Y-axis of the line segment Y1-Y1 ; Figure 9A is a schematic view of the substrate along the first Y-axis of the line segment Y1-Y1 ; Figure 10D is a schematic view of the substrate along the second Y-axis of the line segment Y2-Y2; Figure 9A is a schematic view of the substrate along the second Y-axis of the line segment Y2-Y2;

[0018] Figures 11A-11D is a schematic view of the substrate at different perspectives after the gate oxide is deposited on the semiconductor channels and the electric conductor gate material is applied to obtain two gate-all-around (GAA) transistors adjacent to each other (separated by an electrically insulating structure); Figure 11A is a schematic view of the substrate along the first X-axis of the line segment X1-X1 ; Figure 9A is a schematic view of the substrate along the first X-axis of the line segment X1-X1 ; Figure 11B is a schematic view of the substrate along the second X-axis of the line segment X2-X2; Figure 9A is a schematic view of the substrate along the second X-axis of the line segment X2-X2; Figure 11C is a schematic view of the substrate along the first Y-axis of the line segment Y1-Y1 ; Figure 9A is a schematic view of the substrate along the first Y-axis of the line segment Y1-Y1 ; Figure 11D is a schematic view of the substrate along the second Y-axis of the line segment Y2-Y2; Figure 9A is a schematic view of the substrate along the second Y-axis of the line segment Y2-Y2;

[0019] Figures 12A-12C Three different combinations of different semiconductor fins / fins portions overlapping together in the dislocation region are shown; three different combinations are shown here; in Figure 12A two fins have different widths and overlap together in the dislocation region; in Figure 12B one side of a fin overlaps a plurality of fins in the dislocation region; in Figure 12C two fins have the same width and are offset from each other in the dislocation region;

[0020] Figure 13Ais a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors; Figure 13B is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors;

[0021] Figure 14A is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors; Figure 14B is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors;

[0022] Figure 15A is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors; Figure 15B is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors;

[0023] Figure 16 is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors;

[0024] Figure 17 is a Y-axis cross-sectional view showing opposite ends of a continuous poly on diffusion edge (CPODE) structure formed in a front-end-of-line (FEOL) process for two transistors;

[0025]

Symbol Description

[0026] 100: method

[0027] 102: step

[0028] 105: step

[0029] 106: step

[0030] 110: step

[0031] 115: step

[0032] 120: step

[0033] 125: step

[0034] 130: step

[0035] 135: step

[0036] 140: step

[0037] 145: step

[0038] 150: step

[0039] 155: step

[0040] 160: step

[0041] 200: integrated circuit

[0042] 202: substrate

[0043] 204: shallow trench isolation

[0044] 210: source / drain region

[0045] 211: dummy source / drain region

[0046] 212: dummy gate region

[0047] 214: dummy gate

[0048] 216: dummy gate

[0049] 218: inner dielectric spacer

[0050] 220: interlayer dielectric region

[0051] 224: dielectric spacer

[0052] 226: continuous etch stop layer

[0053] 228: dummy oxide layer

[0054] 230: gate oxide layer

[0055] 232: vertical sidewall

[0056] 235: width

[0057] 240: continuous polysilicon across diffusion layer boundary structure

[0058] 242: insulating space

[0059] 243: sidewall

[0060] 244: trench

[0061] 245: space

[0062] 246: dielectric material

[0063] 248: dielectric material

[0064] 250: gate

[0065] 260: semiconductor fin

[0066] 262: fin portion

[0067] 263: width

[0068] 264: fin portion

[0069] 265: width

[0070] 266: fin portion

[0071] 267: width

[0072] 268: fin portion

[0073] 269: width

[0074] 270: fin portion

[0075] 271: width

[0076] 280: difference region

[0077] 282: region

[0078] 284: region

[0079] 286: region

[0080] 287: side region

[0081] 288: central region

[0082] 289: line

[0083] 290: transistor

[0084] 292: transistor

[0085] 300: stack

[0086] 302: semiconductor nanolayer

[0087] 304: sacrificial layer

[0088] 310: hard mask layer

[0089] 320: bottom layer

[0090] 322: middle layer

[0091] 324: photoresist layer

[0092] 330: cut metal gate structure

[0093] 332: cut metal gate trench

[0094] 335: width

[0095] a: depth

[0096] b: depth

[0097] c: critical dimension

[0098] d: critical dimension

[0099] e: critical dimension

[0100] f: critical dimension

[0101] g: critical dimension

[0102] h: critical dimension

[0103] D: difference

[0104] N: number

[0105] W1: width

[0106] W2: width

[0107] W3: width

[0108] X1-X1: line segment

[0109] X2-X2: line segment

[0110] Y1-Y1: line segment

[0111] Y2-Y2: line segment DETAILED DESCRIPTION

[0112] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described herein to facilitate discussion of the present disclosure. It should be understood by those skilled in the art, however, that these specific examples and configurations do not limit the present disclosure in any way. For example, in the following description, formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly contacting one another, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact one another. Further, in various examples, reference numerals and / or letters can be repeated. Such repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between various embodiments and / or configurations discussed.

[0113] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0114] Numerical values in the specification or claims of this application should be understood to include any numerical value that when reduced to the same number of significant figures as the number of significant figures in the numerical value, would be the same as the numerical value described. All ranges disclosed in this document are inclusive of the endpoints.

[0115] The term "about" can be used to include any numerical value that can vary but does not affect the basic function of the value. When used in a range, "about" also encompasses the absolute values of the two endpoints of the defined range, e.g., "about 2 to about 4" also encompasses the range "from 2 to 4". The term "about" can be considered to be ±10% of the stated number.

[0116] The present disclosure relates to structures made of different layers. When the terms "on" or "above" are used in reference to two different layers (including a substrate), it means that one layer is above the other. These terms do not require that the two layers be in direct contact with each other, and other layers can be allowed to be between them. For example, all layers of a structure can be considered to be "on" a substrate, even though they are not in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other without any other layers between them. In addition, when referring to performing a process step on a substrate, it should also be understood in context to perform the step on any existing layers on the substrate as well.

[0117] The terms "high current" and "low current" used in the present disclosure are relative terms that are values of two currents in comparison to each other, the larger current can be considered "high current" and the lower current can be considered "low current". It is possible that a current value X can be both high current or low current, depending on which current value is compared to.

[0118] The present disclosure relates to methods and systems for reducing damage to adjacent transistors, particularly gate-all-around transistors. Transistors can be designed to handle a particular current density range for a particular application. Gate-all-around transistors can use nanolayers as the semiconductor channel, and the number of nanolayers and their width can be varied to achieve desired performance characteristics.

[0119] Differential design (where the structure has a non-linear shape in a particular region) can substantially improve the efficiency of area usage. In creating nanolayers, there is a risk in integrating high / high current (wide nanolayers) and low / low current (narrow or thin nanolayers) applications (if high current goes through narrow nanolayers). Using separate masks and processes on the substrate to define high current regions and low current regions can increase cost. Finally, transistor isolation processes that occur in the middle-of-line (after the metal gate is deposited and the transistor is fully formed) have a risk of damaging the epitaxial silicon structure in the transistor.

[0120] In the present disclosure, a continuous poly on diffusion edge (CPODE) structure or pattern is used as an electrical insulating or dielectric feature within (or adjacent to) a differential region on a wafer substrate. The CPODE structure is formed by etching one or more semiconductor fins and forming a trench in the substrate (where each fin was originally located), and then filling the trench with a dielectric material. This provides electrical isolation between adjacent active device regions (such as transistors). The method of the present disclosure can be useful when there are differentials in the semiconductor fins and / or when the semiconductor fins have different widths that overlap each other.

[0121] Figure 1 According to some embodiments, a flowchart of a method 100 for insulating a first region from a second region on a substrate is shown. The method is useful for electrically insulating two transistors that are adjacent to each other. Figures 2A-11D Various steps of the method are shown, and these figures are discussed together. These figures provide different perspectives for ease of understanding.

[0122] It is noted that certain common steps will not be fully described each time in the following discussion, and can only be considered as having their corresponding results. For example, a pattern / structure can be formed in a particular layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching, but in the following discussion it can only be referred to as patterning in a particular layer. For completeness, some of these various steps will be discussed here.

[0123] Generally, the photoresist layer can be applied (by, for example, spin coating or spraying, roller coating, dip coating, or extrusion coating). Typically, in spin coating, the substrate is placed on a spin table (which can include a vacuum chuck for holding the substrate in place). The photoresist composition is then applied to the center of the substrate. The rate of the spin table is then increased to spread the photoresist uniformly from the center of the substrate to the edge of the substrate. The spin rate of the spin table is then fixed, which can control the thickness of the final photoresist layer.

[0124] The photoresist composition is then baked or cured to remove the solvent and harden the photoresist layer. In some particular embodiments, the baking occurs at a temperature of about 90 °C to about 110 °C. The baking can be performed by using a hot plate or an oven (or similar device). Thus, the photoresist layer is formed on the substrate.

[0125] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the intended mask pattern. In particular embodiments, extreme ultraviolet light at a wavelength of about 13.5 nm is used to pattern, which allows smaller feature sizes to be achieved. This causes portions of the photoresist layer to be exposed to the radiation and portions of the photoresist layer to not be exposed to the radiation. This exposure causes portions of the photoresist to become soluble in a developer, while other portions of the photoresist remain insoluble in the developer.

[0126] An additional photoresist baking step (post exposure bake (PEB)) can occur after exposure to the radiation. This can help, for example, to release acid leaving groups (ALGs) or other molecules (with significant effect on chemically amplified photoresists).

[0127] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solution. In the developing step, the soluble portions of the photoresist layer are dissolved and washed away, leaving behind a photoresist pattern. An example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers can include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl 2-hydroxyisobutyrate, ethyl lactate, or propylene glycol monomethyl ether acetate, n-pentyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, a post-develop bake or hard bake is performed to stabilize the photoresist pattern after development to optimize performance in subsequent steps.

[0128] Next, the layer underneath the photoresist layer is now exposed. The photoresist pattern is transferred to the layer underneath the patterned photoresist layer by etching. After use, the patterned photoresist layer can be removed, for example, using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other stripping solutions, or by dry etching using an oxygen plasma.

[0129] Generally, any etching step used herein can be implemented using a wet etching, dry etching or plasma etching process such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof as appropriate. The etching can be anisotropic. Depending on the material, the etchant can include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrogen fluoride (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BC13), ammonia (NH3), bromine (Br2), the like, or combinations thereof in various proportions. For example, silicon dioxide can be wet etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry etched using various mixtures such as trifluoromethane, oxygen, carbon tetrafluoride and / or hydrogen.

[0130] Planarization can be implemented to achieve a planar surface. Planarization can be implemented, for example, using a chemical mechanical polishing (CMP) process. Generally, chemical mechanical polishing is implemented using a rotating table with a polishing pad attached. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is supplied onto the polishing pad or onto the wafer substrate. During polishing, both the polishing pad and the carrier are rotated, which induces mechanical and chemical effects on the wafer substrate and / or on the surface above its top layer, thereby removing undesired material and forming a high degree of isoplanar surface. A post-chemical mechanical polishing step is then implemented, which is a brush cleaning of one or both sides of the wafer substrate using a rotating scrubber and cleaning solution.

[0131] Finally, cleaning steps such as wet cleaning can be implemented between process steps. The cleaning solution depends on the etching recipe and the exposed layer. Examples of cleaning solutions can include deionized water, dilute hydrofluoric acid, and other common solutions.

[0132] The methods and systems of the present disclosure include a number of different dielectric structures. The dielectric structures can be made of any suitable combination of dielectric materials. Examples of dielectric materials can include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiO x N y ), hafnium oxynitride (HfO x N y ), or zirconium oxynitride (ZrO x N y ), or hafnium silicate (ZrSi x O y ), or zirconium silicate (ZrSi x O y ), or silicon carbonitride (SiCO x O y N z ), or hexagonal boron nitride (hBN). Other dielectric materials can include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0133] Next, Figures 2A-2E An initial state of the partially completed integrated circuit 200 on the wafer substrate 202 is shown before the method steps are implemented, as received in step 102 of Figure 1 Referring first to the plan view of Figure 2A shows pairs of dummy gate regions 212. Between each pair of dummy gate regions 212 is a pair of low-k dielectric spacers 224 and a continuous etch stop layer 226 (CESL).

[0134] Dashed lines indicate the location of the semiconductor fin (underneath dummy gate region 212, dielectric spacer 224, and continuous etch stop layer 226). As shown in this example, there is a first fin portion 262 and a second fin portion 264 in a first region 282 of the substrate. There is a third fin portion 266 in a middle region or second region 284 of the substrate. Finally, there is a fourth fin portion 268 and a fifth fin portion 270 in a third region 286 of the substrate.

[0135] As shown here, first region 282 is adjacent to second region 284. Likewise, second region 284 is adjacent to third region 286 and separates first region from third region. However, it is noted that these items are merely designations for the regions. Thus, any of the three regions (region 282, region 284, and region 286) can represent the first region, the second region, and the third region.

[0136] First fin portion 262 has a width 263. Second fin portion 264 has a width 265. Third fin portion 266 has a width 267. Fourth fin portion 268 has a width 269. Fifth fin portion 270 has a width 271. The width of each fin is independent of the width of the other fin portions. As shown here, the width 267 of the third fin portion is greater than the widths (width 263, width 265, width 269, and width 271) of the other fin portions.

[0137] Prior to formation of the continuous polysilicon across the diffusion layer boundary structure, the five fin portions are overlapped together and can be considered to form a single semiconductor fin 260. Alternatively, each fin portion can be considered by itself as a respective semiconductor fin. Alternatively, the fin portions in each region can be considered together as a semiconductor fin for that region, since the current density in a region is proportional to the sum of the widths of the fin portions in that region. The locations where the fin portions overlap one another can be considered to be depletion regions 280, two such depletion regions are shown here as rectangles. It is noted that the depletion regions shown here have 90° intersections with the fin portions for simplicity, but their intersection angles can be smaller.

[0138] Reference is next made to Figure 2B A cross-sectional view is provided. An integrated circuit is built on a substrate 202. The substrate is typically a wafer made of a semiconductor material. Such a material can include silicon, for example in the form of single-crystal silicon or in the form of polysilicon. In other embodiments, the substrate can be made of other elemental semiconductors such as germanium, or can include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some particular embodiments, the wafer substrate is silicon.

[0139] Next, a shallow trench insulating layer 204 (or a shallow trench insulating (STI) region) is formed over the substrate 202 near the fin portions. The dielectric material in the shallow trench insulating layer is typically silicon dioxide, although other dielectric materials can be used, such as undoped silicon, silicon oxide (e.g., silicon dioxide), silicon nitride, silicon oxynitride, fluorine-doped silicate glass, or other low-k dielectric materials. Deposition can be accomplished using physical vapor deposition (PVD) or chemical vapor deposition (CVD) or spin-on processes (as known in the art) or can be grown by oxidation. Deposition of the shallow trench insulating layer is typically prior to establishing the layers of the various semiconductor fins 260 / fin portions (fin portion 262, fin portion 264, fin portion 266, fin portion 268, and fin portion 270). If desired, the dielectric material can be deposited above the height of the substrate, then recessed back to the intended height.

[0140] In Figure 2B , the first fin portion 262 and the fourth fin portion 268 are visible in the X-axis view along the line segment X1-X1. In Figure 2C , the third fin portion 266 is visible in the X-axis view along the line segment X2-X2. In Figure 2D , the first fin portion 262 and the second fin portion 264 are visible in the Y-axis view along the line segment Y1-Y1. In Figure 2E , the third fin portion 266 is visible in the Y-axis view along the line segment Y2-Y2.

[0141] As is evident in Figure 2C , each fin portion includes a stack 300 (formed by interleaving semiconductor nanolayers 302 and sacrificial layers 304). The fabrication of these layers can utilize chemical vapor deposition, atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), or other suitable processes. Each semiconductor nanolayer can be, for example, silicon or other suitable material for the substrate. The sacrificial layers 304 can be fabricated in any suitable material (selectively etchable compared to other materials used in the transistor, such as silicon germanium).

[0142] Also shown here are source / drain regions 210, located in the fin portions. In some particular embodiments, these regions are formed from epitaxial silicon (using chemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, or the like). They can also be doped with suitable dopants, such as boron, gallium, or indium, or phosphorus or arsenic. Inner dielectric spacers 218 separate the source / drain regions from the sacrificial layers 304 (which are eventually removed and filled with electrical conductor gate material).

[0143] Next, interlayer dielectric regions 220 (ILD) and dummy gate regions 212 and continuous etch stop layers 226 are disposed over the substrate in an interleaved fashion. As shown in Figure 2B and Figure 2C The interlayer dielectric regions 220 are disposed over and aligned with the source / drain regions 210.

[0144] The interlayer dielectric regions electrically separate the source / drain regions from the final gate end points or electrodes. The interlayer dielectric regions can be formed of any dielectric material, and need not be a high-k dielectric material. Suitable dielectrics can include silicon nitride, silicon oxide (e.g., silicon dioxide), phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high stress undoped silicate glass (HSUSG), and borosilicate glass (BSG), or any combination thereof. The interlayer dielectric can be deposited by any suitable method, such as chemical vapor deposition. The interlayer dielectric regions 220 are surrounded on three sides (top and two sides) by continuous etch stop layers 226. The continuous etch stop layers are typically made from silicon nitride.

[0145] Between the interlayer dielectric regions are dummy gate regions 212. The dummy gates are typically made from polysilicon, and are used to define the shape of the final gate end points or electrodes. The vertical surfaces of the dummy gate regions 212 are covered with low-k dielectric spacers 224 having a dielectric constant equal to or less than the dielectric constant of silicon nitride (about 7). Suitable materials can include various nitrides or oxides. Continuous polysilicon across the diffusion layer boundary structure is typically formed at the location of the dummy gates.

[0146] Dummy oxide layers 228 are located between the fin portions and the dummy gate regions 212. In Figure 2B and Figure 2C , this can be seen above the fin portion 262, the fin portion 266, and the fin portion 268. As shown in Figure 2D and Figure 2E , the dummy oxide layers are present on the top and sides of each semiconductor fin portion (fin portion 262, fin portion 266, and fin portion 268).

[0147] An integrated circuit 200, partially completed on a wafer substrate 202, can be fabricated. First, the substrate is etched to define trenches for a shallow trench insulating layer 204. The trenches are then filled with a dielectric material to form the shallow trench insulating layer. Next, a fin stack 300 is formed, which is a layer of alternating semiconductor nanolayers 302 and sacrificial layers 304 deposited on the substrate. A hard mask is applied and the fin stack is etched to obtain finned semiconductor fins at the desired locations. Anisotropic etching of the sacrificial layer is performed, and internal dielectric spacers 218 are formed at these etched locations on the exposed outer walls of the fin stack. The fin stack is then etched to create trenches at the desired locations for source / drain regions 210. Another anisotropic etching is performed on the newly exposed surfaces of the sacrificial layer in these trenches, and internal dielectric spacers 218 are again formed at the newly etched locations. A dummy oxide layer 228 is then formed on the exposed silicon surface. Epitaxial silicon is then deposited in the trenches to form the source / drain regions 210. A dummy gate material, such as polysilicon, is then deposited onto the substrate. Another mask is applied and the dummy gate material is etched to create trenches over the source / drain regions, forming a dummy gate region 212. A low-dielectric-constant dielectric spacer 224 is then applied to the exposed vertical surfaces of the dummy gate. An interlayer dielectric region 220 is then formed over the source / drain regions. A continuous etch stop layer 226 is then applied to the three exposed sides of the interlayer dielectric region.

[0148] Next, refer to Figure 1 Step 105 is as follows Figures 3A-3D As shown, a hard mask layer 310 (with a thickness of 315) is applied over the dummy gate region 212 and the interlayer dielectric region 220. In some embodiments, the thickness of the hard mask layer 315 is from about 600 angstroms to about 900 angstroms, or from about 700 angstroms to about 800 angstroms.

[0149] exist Figure 1 In selective step 106, the bottom layer 320 and / or the middle layer 322 may be applied over the hard mask layer 310. For the bottom layer, spin-on carbon (SOC) material is suitable. For the middle layer, spin-on glass material is common. When used, the combination of the hard mask layer, bottom layer, and middle layer creates a three-layer patterned etching system, which allows for better control in subsequent etching. Then, in Figure 1 In step 110, the photoresist layer 324 is applied and patterned. In some specific embodiments, extreme ultraviolet light (with a wavelength of approximately 13.5 nm) is used for patterning because this allows for smaller feature sizes to be achieved. If the bottom and middle layers are not used, the photoresist layer is applied directly to the hard mask layer 310.

[0150] The obtained structural display is as follows: Figures 3A-3DThe light blocking layer 324 is patterned to expose two dummy gate regions 212 in the second region 284, i.e. along the line segment Y2-Y2 (within or adjacent to the depletion region 280). As shown in Figure 2A , the third fin portion 266 is exposed. This is shown for illustration only. The dummy gates in the first region 282 and / or the third region 286 can also be shown as exposed. Figure 3D

[0151] Next, in step 115 of Figure 1 , etching is performed to etch through the hard mask layer 310 and expose the dummy gate regions 212 (within or adjacent to the depletion region 280). This can be considered as a hard mask open (HMO). When this occurs, the middle layer 322 and the bottom layer 320 are etched first (using a suitable etchant). After the bottom layer, the middle layer and the photoresist layer are removed, the resulting structure is as shown in Figures 4A-4D .

[0152] Next, in step 120 of Figure 1 , the exposed dummy gates are removed by etching. As shown in Figure 5A , Figure 5B and Figure 5D , the removal of the dummy gates exposes three sides of the third fin portion 266. Compare Figure 5B and Figure 5C , the removal of the dummy gates also extends across the boundary of the first fin portion 262 and the second fin portion 264 on the sides. The empty dummy gates can also be considered as insulating spaces 242 here. When the dummy gates are formed of polysilicon, suitable etchants can include boron trichloride, chlorine gas, silicon tetrachloride, hydrogen chloride, oxygen, hydrogen bromide, sulfur hexafluoride and / or nitrogen trifluoride and in suitable compositions and proportions. It is noted that etching occurs only within or adjacent to the depletion region 280 (see Figure 2A ) and not over the entire second region 284. It is also noted that in some embodiments, the shallow trench isolation layer can also be etched slightly and form small recesses.

[0153] Next, in step 125 of Figure 1 , the dummy oxide is removed. Figures 6A-6D The resulting structure is shown. The removed dummy oxide can be seen in Figure 6B and Figure 6D . The fin portion in the first region shown in Figure 6C is not affected because it is protected by the hard mask layer 310.

[0154] Next, in step 130 of Figure 1 ​In step 130, etching is performed to remove the exposed semiconductor fin portion 266 and form a trench 244 in the substrate. Figures 7A-7D The obtained structure is shown. It is worth noting that... Figure 7A The area shown excluding the third fin portion 266 remains unchanged (with...). Figure 6A (Compared to). This is to be expected because the etchant used for the semiconductor fin portion 266 will not etch the shallow trench insulating layer 204.

[0155] refer to Figure 7A and Figure 7B It is worth noting that the etchant used for the semiconductor nanolayer 302 and the sacrificial layer 304 does not etch the inner dielectric spacer 218. Therefore, there is a protective layer between the trench and the source / drain region 210 (formed from epitaxial silicon, which can be etched by the same etchant used for the semiconductor nanolayer).

[0156] Next, in Figure 1 In step 135, the trench 244 and the insulating space 242 are filled (or backfilled) with at least one dielectric material to form a continuous polysilicon transdiffusion layer boundary structure 240 (insulating the first region 282 and the second region 284). As shown in Figures 8A-8D The trench walls and insulating space walls are backed with a first dielectric material 246. This can be achieved, for example, by atomic layer deposition. In some specific embodiments, the first dielectric material is an oxide, such as silicon oxide. The trenches and insulating spaces are then filled with a second dielectric material 248, different from the first dielectric material. This can be implemented by deposition, as described herein. In some specific embodiments, the second dielectric material is a nitride, such as silicon nitride. As shown, by comparison Figure 8C and Figure 8D Fin portions 262 and 264 in the first region are electrically insulated from fin portion 266 in the second region by a continuous polysilicon trans-diffusion layer boundary structure (extending over the sides of fin portions 262 and 264). More generally, the first region 282 is electrically insulated from the second region 284 by a continuous polysilicon trans-diffusion layer boundary structure.

[0157] Next, in Figure 1 In step 140, the substrate is planarized to remove overfilled dielectric material and hard masking layer 310. The resulting structure is shown in... Figures 9A-9E In the first region 282, the remaining dummy gate regions 212, 284, and 286 are now exposed. For example, the primary dummy gate 214 in the first region is exposed, just as the secondary dummy gate 216 in the second region is exposed.

[0158] Next, in Figure 1In step 145, dummy gate regions (such as primary dummy gate 214 and secondary dummy gate 216) are removed. Any remaining dummy oxide 228 (see Figure 9C ) is also removed. Next, in step 150, the sacrificial layer 304 in the semiconductor fin portions (fin portion 262, fin portion 264, fin portion 266, fin portion 268, and fin portion 270) is removed. The implementation of the two steps is typically etching. It is noted that the sacrificial layer is removed after the continuous polysilicon across the diffusion layer boundary structure is formed. The resulting structure is shown in Figures 10A-10D . The empty spaces after the removal of the dummy gate material can be considered as gate spaces. Referring to Figure 10C , the semiconductor nanolayer 302 is supported by the adjacent source / drain regions 210 (not visible in this perspective) and can also be considered as a semiconductor channel.

[0159] Next, in step 155 of Figure 1 , the gate oxide 230 is applied to the semiconductor nanolayer 302 (or semiconductor channel) as shown in Figures 11A-11D . This can be achieved by, for example, atomic layer deposition. Next, in step 160, an electrically conductive gate material is applied to fill the gate spaces and form gates 250. Any suitable electrically conductive material can be used. In some particular embodiments, metals such as titanium nitride, platinum, cobalt, rhodium, palladium, titanium, tantalum, and the like are used. Thus, gate-all-around transistor 290 and gate-all-around transistor 292 are formed in the first region 282 and the second region 284. As shown in Figure 11B , the second region 284 has three source / drain regions 210 and two gates 250, and thus can be considered as having two transistors. It is noted that not all components of transistor 290 are shown.

[0160] Referring back to Figure 2A , in some embodiments, the width 267 of the semiconductor fin portion 266 in the second region 284 is greater than the sum of the width 263 of the semiconductor fin portion 262 and the width 265 of the semiconductor fin portion 264 in the first region 282. Thus, the second region can handle high current density and can be considered as a high current region relative to the first region (considered as a low current region).

[0161] Next, referring to Figures 12A-12C , the method of the present disclosure can be applied to electrically isolate any different combinations of semiconductor fins / fm portions. Here, three different combinations are shown.

[0162] In Figure 12AIn this case, the first semiconductor fin portion 262 has a nanometer layer with a width Wl. It overlaps with the second semiconductor fin portion 264, which has a nanometer layer with a different width W2, where the width Wl is greater than the width W2, at the dislocation region 280. Also shown here is a continuous polysilicon across diffusion layer boundary structure 240 that goes through the nanometer layer of the first semiconductor fin portion 262. Note that the continuous polysilicon across diffusion layer boundary structure can also go through the second semiconductor fin portion 264, or through both fin portions.

[0163] Figure 12B A combination of a semiconductor fin portion overlapping with multiple semiconductor fin portions is shown. Here, the first semiconductor fin portion 262 overlaps with the second semiconductor fin portion 264 and the third semiconductor fin portion 266 at one end. Assume in another case that the first semiconductor fin portion 262 is separated into multiple fin portions 264, 266 at the dislocation region 280 in the first region 282, each fin portion 264 and 266 has a smaller width than the fin portion 262 in the second region 284. Here, the continuous polysilicon across diffusion layer boundary structure 240 is shown to go through the second semiconductor fin portion 264 and the third semiconductor fin portion 266.

[0164] The first semiconductor fin portion 262 and its nanometer layer has a width Wl. Similarly, the second semiconductor fin portion 264 is designated to have a width W2, and the third semiconductor fin portion 266 is designated to have a width W3. Here, the width Wl is greater than (width W2 + width W3). In general, the number of multiple semiconductor fins N >= 2.

[0165] Figure 12C A combination is shown where the first semiconductor fin portion 262 and the second semiconductor fin portion 264 have the same width (width Wl = width W2), and the two fin portions are offset from each other (with an offset difference D) in the dislocation region 280. The continuous polysilicon across diffusion layer boundary structure 240 is shown here to go through the first semiconductor fin portion 262 and the second semiconductor fin portion 264.

[0166] As mentioned above, the sacrificial layer is removed and the gate electrode is formed after the continuous polysilicon across diffusion layer boundary structure formation. This means that the continuous polysilicon across diffusion layer boundary structure is formed in the front-end-of-line (FEOL) process, or in other words, the continuous polysilicon across diffusion layer boundary structure formation is before the gate electrode material is applied to complete the formation of the transistor. This avoids potential damage to the entire source / drain region (if the continuous polysilicon across diffusion layer boundary structure formation is in the middle-of-line (MEOL), after the gate deposition and the transistor is completed, damage can occur).

[0167] Figures 13A-15B Three different continuous polysilicon across diffusion layer boundary structures formed in the front-end-of-line process are shown.Figure 13A is a Y-axis cross-sectional view showing two transistors on opposite sides of a continuous polysilicon across diffusion layer boundary structure. Figure 13B is a magnified Y-axis cross-sectional view of a portion of a continuous polysilicon across diffusion layer boundary structure, as indicated by the square dashed line in Figure 13A Figures 14A-15B is a similar view of a different structure.

[0168] Referring next to Figure 13A , a continuous polysilicon across diffusion layer boundary structure 240 is shown with a sidewall 243 (formed of a first dielectric material) and a space 245 (formed of a second dielectric material). The continuous polysilicon across diffusion layer boundary structure extends through a shallow trench isolation layer 204 to a substrate 202. A first transistor 290 is located on one side of the continuous polysilicon across diffusion layer boundary structure, and a second transistor 292 is located on the other side of the continuous polysilicon across diffusion layer boundary structure. Each transistor includes a semiconductor nanolayer 302 (enclosed by a gate oxide layer 230). The material of the gate 250 is shown as a hardmask layer 310. Referring next to the magnified view of Figure 13B , the gate oxide layer 230 is also shown as a vertical sidewall 232 that directly contacts the continuous polysilicon across diffusion layer boundary structure 240. Referring back to Figures 11A-11D , the gate oxide layer 230 is present against the continuous polysilicon across diffusion layer boundary sidewall 243, indicating that the continuous polysilicon across diffusion layer boundary structure was formed in a front-end process (before the gate oxide layer 230 was applied).

[0169] Referring next to the second structure of Figures 14A-14B , this structure includes a cut metal gate structure 330. The cut metal gate structure is formed after the metal gate is formed. The metal gate is cut (e.g., by etching) to separate the metal gate into two or more portions. Each portion functions as a metal gate for an independent transistor. A dielectric material is then filled into trenches between adjacent metal gate portions. These trenches form the cut metal gate structure.

[0170] In Figures 14A-14B , the cut metal gate trenches 332 are located between the continuous polysilicon across diffusion layer boundary structure 240 and the semiconductor nanolayers 302 of the transistors 290 and 292. However, as shown in the magnified view of Figure 14B , the gate oxide layer is still shown as a vertical sidewall 232 (directly contacting the continuous polysilicon across diffusion layer boundary sidewall 243). This indicates that the continuous polysilicon across diffusion layer boundary structure was formed in a front-end process.

[0171] Finally, in Figures 15A-15B ​In the third configuration of the present disclosure, there is also a cut metal gate structure 330 with a cut metal gate trench 332 in the continuous polysilicon across diffusion layer boundary structure 240, but still between the semiconductor nanolayer 302 of the transistor 290 and the transistor 292. Figure 15B The magnified view shows that the gate oxide layer 230 still exists as a vertical sidewall 232 (directly contacting the vertical continuous polysilicon across diffusion layer boundary sidewall 243), indicating that the continuous polysilicon across diffusion layer boundary structure is formed in a front-end-of-line process.

[0172] Figure 16 The comparative example is a cross-sectional view of the Y-axis, showing the structure when the formation of the continuous polysilicon across diffusion layer boundary structure is after the formation of the gate electrode, i.e., a back-end-of-line process. The cut metal gate structure 330 is also shown here. The material of the gate oxide layer 230 is not in contact with the continuous polysilicon across diffusion layer boundary structure 240 at all. Instead, the continuous polysilicon across diffusion layer boundary structure 240 is directly in contact with the cut metal gate structure 330. In addition, as shown here, the cut metal gate trench 332 has a greater vertical width 335 than the width 235 of the gate oxide layer 230.

[0173] The method of the present disclosure has many advantages. First, it allows wide nanolayers and narrow nanolayers to be integrated into a single fabrication step without having to define them in different steps. Second, it reduces or prevents damage to epitaxial silicon structures (i.e., source / drain regions) that can occur when an insulating structure is created to insulate the narrow nanolayers and wide nanolayers, reducing the number of damaged epitaxial silicon structures to a minimum. Finally, the method can be applied to a depletion structure, improving the area usage efficiency.

[0174] Additional process steps can be implemented to obtain semiconductor devices comprising adjacent transistors with a depletion region separated by a continuous polysilicon across diffusion layer boundary structure. The semiconductor devices can be used for various applications, such as Bipolar-CMOS-DMOS (BCD) circuits to drive discrete high voltage components; for driving liquid crystal display (LCD), organic light emitting diode (OLED), active matrix organic light emitting diode (AMOLED), or quantum dot display (QLED) display panels; for system image displays, such as mobile phones, facial recognition systems, or for mobile sensors for automotive applications, security applications, energy efficiency, etc.; power management elements to control power flow and direction; and / or image signal processors (ISPs).

[0175] The present disclosure thus relates in some embodiments to methods for insulating a first region and a second region on a substrate. Dummy gates in a depletion region between the first region and the second region are removed to expose portions of semiconductor fins and form insulating spaces. Etching is implemented to remove the exposed portions of semiconductor fins and create trenches in the substrate. The trenches and the insulating spaces are then filled with at least one dielectric material to form a continuous polysilicon across diffusion layer boundary structure that insulates the first region and the second region.

[0176] Additionally, disclosed in various embodiments are methods for insulating two adjacent transistors. A substrate is received having a first semiconductor fin in a first region and a second semiconductor fin in a second region. Each semiconductor fin comprises layers of island body nanolayers interleaved with sacrificial nanolayers. Dummy gates are removed within (or adjacent to) a depletion region to expose portions of the first semiconductor fin and form insulating spaces. Etching is implemented to remove the exposed portions of the first semiconductor fin and create trenches in the substrate. The trenches and the insulating spaces are filled with at least one dielectric material to form a continuous polysilicon across diffusion layer boundary structure between the first region and the second region. The substrate is then planarized to expose a primary dummy gate in the first region and a secondary dummy gate in the second region. The primary dummy gate, the secondary dummy gate, and the sacrificial layers are removed to form gate spaces in the first region and gate spaces in the second region. An electrical conductor material is deposited in the gate spaces of the first region and in the gate spaces of the second region to form two adjacent transistors electrically insulated from each other by the continuous polysilicon across diffusion layer boundary structure.

[0177] Also disclosed in various embodiments are semiconductor devices including a substrate. The substrate has a first semiconductor fin on a first region and a second semiconductor fin on a second region. The first semiconductor fin and the second semiconductor fin contact each other at a drain region. A dielectric insulating structure is shown intervening between the first region and the second region within (or adjacent to) the drain region.

[0178] The methods, systems, and devices of the present disclosure are further illustrated by the following non-limiting working examples. It is to be understood that the examples are only intended to illustrate and not to limit the scope of the materials, conditions, process parameters, and the like as discussed herein.

[0179] Example.

[0180] According to the methods of the present disclosure, a number of wafers are prepared and have continuous polysilicon across diffusion layer boundary structures. Figure 17 is a line drawing of such a continuous polysilicon across diffusion layer boundary structure. As shown in Figure 17 As shown at the top, there are two side regions 287 and a center region 288. Two metal gates 250 are shown in the center region. Three source / drain regions 210 are also shown, with interlayer dielectric regions 220 thereon. Two separate continuous polysilicon across diffusion layer boundary structures 240 are fabricated on either side of the center region. One continuous polysilicon across diffusion layer boundary structure 240 cuts through a side region 287, and one continuous polysilicon across diffusion layer boundary structure 240 cuts through the center region 288. A dummy source / drain region 211 is shown intervening between the two continuous polysilicon across diffusion layer boundary structures 240. The interlayer dielectric regions 220 are also visible in the side regions.

[0181] Figure 17 The bottom portion of is a line 289 through the cut. The continuous polysilicon across diffusion layer boundary structure 240 cuts through a side region, with a depth a. The continuous polysilicon across diffusion layer boundary structure 240 cuts through the center region, with a depth b.

[0182] The semiconductor channel in this example is formed in three nanometer layers. The continuous polysilicon across diffusion layer boundary structure cuts through the center region at the top nanometer layer level, with a critical dimension c (CD). The continuous polysilicon across diffusion layer boundary structure cuts through the center region at the middle nanometer layer level, with a critical dimension d. The continuous polysilicon across diffusion layer boundary structure cuts through the center region at the bottom nanometer layer level, with a critical dimension e.

[0183] The continuous polysilicon across diffusion layer boundary structure cuts through the side portion region at its top nanolayer level position with critical dimension f. The continuous polysilicon across diffusion layer boundary structure cuts through the side portion region at its middle nanolayer level position with critical dimension g. The continuous polysilicon across diffusion layer boundary structure cuts through the side portion region at its bottom nanolayer level position with critical dimension h.

[0184] The depth of each continuous polysilicon across diffusion layer boundary structure should be at least 180 nanometers (nm). Ideally, depth a = depth b. The critical dimensions of the continuous polysilicon across diffusion layer boundary structure should not be greater than 20 nm, otherwise the epitaxial silicon (i.e., source / drain) region can be damaged. Ideally, critical dimension c = critical dimension f, critical dimension d = critical dimension g, and critical dimension e = critical dimension h.

[0185] The continuous polysilicon across diffusion layer boundary structure was measured and the results are shown in the following table:

[0186]

[0187] As shown in the table, all of the results meet the minimum requirements.

[0188] According to at least one embodiment of the present disclosure, a method for insulating a first region and a second region on a substrate includes removing a dummy gate of a spacer region between the first region and the second region to expose a portion of a semiconductor fin and form an insulating space; etching to remove the exposed portion of the semiconductor fin and form a trench in the substrate; and filling the trench and the insulating space with at least one dielectric material to form a continuous polysilicon across diffusion layer boundary structure that insulates the first region and the second region.

[0189] In some embodiments, the semiconductor fin at a portion of the first region has a larger width than the semiconductor fin at a portion of the second region.

[0190] In some embodiments, the semiconductor fin at a portion of the first region is offset from the semiconductor fin at a portion of the second region.

[0191] In some embodiments, the semiconductor fin is separated into multiple portions at the first region, each of the portions having a smaller width than the semiconductor fin at the second region.

[0192] In some embodiments, the method further includes removing a dummy oxide layer from the exposed portion of the semiconductor fin prior to etching.

[0193] In some embodiments, the first dielectric material is an oxide and the second dielectric material is a nitride.

[0194] In some embodiments, the semiconductor fin comprises a plurality of layers of a semiconductor nanosheet layer and a sacrificial nanosheet layer interleaved.

[0195] In some embodiments, the sacrificial nanosheet layer of the plurality of layers is removed after the formation of the continuous polysilicon across the diffusion layer boundary structure.

[0196] In some embodiments, the dummy gate removal is by: forming a hard mask layer on the substrate; patterning the hard mask layer to expose the dummy gate; and etching to remove the dummy gate.

[0197] In some embodiments, the dummy gate removal is by: forming a hard mask layer on the substrate; patterning the hard mask layer to expose the dummy gate; and etching to remove the dummy gate.

[0198] In some embodiments, further comprising: planarizing to expose a second dummy gate in the first region and a third dummy gate in the second region; etching to remove the second dummy gate and the third gate, forming a gate space in the first region and a gate space in the second region; and depositing an electrical conductor material in the gate space of the first region and the gate space of the second region to form a first transistor and a second transistor.

[0199] According to at least one embodiment of the present disclosure, a method for insulating two adjacent transistors, comprises: obtaining a substrate having a first semiconductor fin on a first region and a second semiconductor fin on a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at a depletion region, and wherein the first semiconductor fin and the second semiconductor fin comprise a plurality of layers of a semiconductor nanosheet layer and a sacrificial nanosheet layer interleaved; removing a dummy gate in or adjacent to the depletion region to expose a portion of the first semiconductor fin and form an insulating space; etching to remove the exposed portion of the first semiconductor fin and form a trench in the substrate; filling the trench and the insulating space with at least one dielectric material to form a continuous polysilicon across the diffusion layer boundary structure between the first region and the second region; planarizing to expose a primary dummy gate in the first region and a secondary dummy gate in the second region; removing the primary dummy gate, the secondary dummy gate, and the sacrificial nanosheet layer of the plurality of layers, forming a gate space in the first region and a gate space in the second region; and depositing an electrical conductor material in the gate space of the first region and the gate space of the second space to form the two adjacent transistors electrically insulated from each other by the continuous polysilicon across the diffusion layer boundary structure.

[0200] In some embodiments, the first semiconductor fin has a larger width than the second semiconductor fin.

[0201] In some embodiments, wherein the first region has a plurality of semiconductor fins in contact with the second semiconductor fin.

[0202] In some embodiments, wherein the first semiconductor fin and the second semiconductor fin are offset from each other.

[0203] According to at least one embodiment of the present disclosure, a semiconductor device, comprising: a substrate; a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin are in contact with each other at an apposition region; a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

[0204] In some embodiments, wherein the first semiconductor fin has a greater width than the second semiconductor fin.

[0205] In some embodiments, wherein the first region has a plurality of semiconductor fins in contact with the second semiconductor fin.

[0206] In some embodiments, wherein the first semiconductor fin and the second semiconductor fin are offset from each other.

[0207] In some embodiments, wherein the first semiconductor fin and the second semiconductor fin each include a source / drain region adjacent to the dielectric insulating structure.

[0208] According to at least one embodiment of the present disclosure, a semiconductor device, comprising: a substrate; a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin are in contact with each other at an apposition region, wherein the first semiconductor fin has a greater width than the second semiconductor fin; a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

[0209] In some embodiments, wherein the first semiconductor fin and the second semiconductor fin are offset from each other.

[0210] In some embodiments, wherein the first semiconductor fin and the second semiconductor fin each include a source / drain region adjacent to the dielectric insulating structure.

[0211] According to at least one embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor fin over a first region, and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an apposition region, wherein the first semiconductor fin and the second semiconductor fin are offset from each other, a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

[0212] In some embodiments, the first semiconductor fin has a greater width than the second semiconductor fin.

[0213] The foregoing outlines features of several embodiments so that a thorough comprehension of the present disclosure can be attained. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor element characterized by comprising: Comprising: a substrate; a first semiconductor fin over a first region and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an apposition region; and a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

2. The semiconductor device according to claim 1, wherein wherein the first semiconductor fin has a greater width than the second semiconductor fin.

3. The semiconductor device according to claim 1, wherein wherein the first region has a plurality of semiconductor fins in contact with the second semiconductor fin.

4. The semiconductor device according to claim 1, wherein wherein the first semiconductor fin and the second semiconductor fin are offset from each other.

5. The semiconductor device according to claim 1, wherein wherein the first semiconductor fin and the second semiconductor fin each include a source / drain region adjacent to the dielectric insulating structure.

6. A semiconductor element characterized by comprising: Comprising: a substrate; a first semiconductor fin over a first region and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an apposition region, wherein the first semiconductor fin has a greater width than the second semiconductor fin; and a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

7. The semiconductor device according to claim 6, wherein wherein the first semiconductor fin and the second semiconductor fin are offset from each other.

8. The semiconductor device according to claim 6, wherein wherein the first semiconductor fin and the second semiconductor fin each include a source / drain region adjacent to the dielectric insulating structure.

9. A semiconductor element characterized by comprising: Comprising: a substrate; a first semiconductor fin over a first region and a second semiconductor fin over a second region, wherein the first semiconductor fin and the second semiconductor fin contact each other at an apposition region, wherein the first semiconductor fin and the second semiconductor fin are offset from each other; and a dielectric insulating structure between the first region and the second region in or adjacent to the apposition region.

10. The semiconductor device according to claim 9, wherein wherein the first semiconductor fin has a greater width than the second semiconductor fin. wherein the first region has a plurality of semiconductor fins in contact with the second semiconductor fin.

Images