Optoelectronic device array structure

Abstract

The utility model discloses a photoelectric device array structure, and relates to the technical field of semiconductors. The structure comprises a driving wafer and compound pixels, the surfaces of the compound pixel and the driving wafer are respectively provided with a bonding structure, the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the surface of one side, far away from the driving wafer, of the bonding structure corresponding to the compound pixel is in contact with a reflecting mirror layer in the compound pixel; the compound pixel comprises a plurality of pixel units which are isolated from one another, and each pixel unit is electrically connected with a first electrode contact in the driving wafer; the periphery of the pixel unit is surrounded by a reflection cavity structure, and the reflection cavity structure is connected with the outer edges of the first semiconductor layer, the reflector layer and the bonding structure in the pixel unit; the top of each pixel unit is provided with a second conductive electrode, and the second conductive electrode is electrically connected with a second electrode contact in the driving wafer.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially to a photoelectric device array structure. BACKGROUND

[0002] Photoelectric device array structure (such as Micro LED) is the core chip of AR (augmented reality) / VR (virtual reality) equipment, compared with LCOS (silicon-based liquid crystal) and OLED (organic light emitting diode) technology, photoelectric device array structure is regarded as the best solution because of its high resolution, low power consumption, high brightness, long life and other advantages.

[0003] Photoelectric device array structure is generally prepared from compound pixels and driving wafer, wherein the compound pixel comprises a first semiconductor layer, an active layer and a second semiconductor layer. In order to form the contact of the semiconductor layer, a transparent conductive film is generally prepared on the surface of the first semiconductor layer as a first semiconductor contact layer, and a bonding structure is prepared on the transparent conductive film and the driving wafer respectively, and the bonding integration of the compound pixel and the driving wafer is completed through the bonding structure.

[0004] Although the transmittance of the transparent conductive film is very high, it still cannot achieve full transparency, which will cause optical loss and cannot achieve the best reflection effect. At the same time, the thickness of the film has limitations. When the film is too thin, the resistance is large, and when the transparent conductive oxide film is thick, the resistance and etching anomaly will be improved, but the reflectivity will be reduced. Therefore, the contradiction between the thickness of the transparent conductive film and the brightness and voltage makes the photoelectric device array structure unable to obtain the best device performance. SUMMARY

[0005] The utility model discloses a photoelectric device array structure which can greatly reduce the loss of light between the pixel unit and the mirror layer metal when there is no transparent conductive film or the transparent conductive film is very thin, and achieve the best brightness improvement.

[0006] To achieve the above-mentioned utility model purposes, the utility model provides the following technical scheme:

[0007] The compound pixel and the surface of the driving wafer are respectively provided with a bonding structure, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the surface of the side of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the mirror layer in the compound pixel;

[0008] The compound pixel comprises a plurality of mutually isolated pixel units, and each pixel unit forms an electrical connection with a first electrode contact in the driving wafer.

[0009] An outer periphery of the pixel unit is surrounded by a reflective cavity structure, the reflective cavity structure is connected with an outer edge of the first semiconductor layer, the mirror layer, the bonding structure in the pixel unit, and the first semiconductor layer at least includes a stacked first partial layer and a second partial layer, the first partial layer is in contact with the mirror layer, and a projection of the second partial layer on the driving wafer is within a projection of the first partial layer on the driving wafer.

[0010] A top of the pixel unit is provided with a second conductive electrode, and the second conductive electrode forms an electrical connection with a second electrode contact in the driving wafer.

[0011] In a possible implementation, an outer surface of the pixel unit is attached with a passivation layer.

[0012] The reflective cavity structure is also connected with an outer edge of the passivation layer.

[0013] In a possible implementation, a spacer structure is arranged between the reflective cavity structure and the passivation layer on the sidewall surface of the pixel unit.

[0014] In a possible implementation, an outer periphery of the pixel unit is entirely filled with a first insulating layer.

[0015] Or,

[0016] An outer periphery of the pixel unit is covered with a second insulating layer in a thin film pattern.

[0017] In a possible implementation, the first insulating layer is filled with a first metal mesh gate structure, a top of the first metal mesh gate structure is in contact with the second conductive electrode, and a bottom of the first metal mesh gate structure is higher than a surface of the driving wafer.

[0018] In a possible implementation, a metal filling structure in communication is arranged between the second conductive electrode and the second electrode contact.

[0019] In a possible implementation, a second metal mesh gate structure is further arranged on a top of the second conductive electrode.

[0020] In a possible implementation, an inside of a pixel area of the driving wafer is provided with at least one second electrode contact.

[0021] In a possible implementation, a first semiconductor contact layer is arranged between the mirror layer and the first semiconductor layer.

[0022] In a possible implementation, a thickness of the first semiconductor contact layer is not greater than 70 nm.

[0023] In a possible implementation, the pixel unit is provided with a redundant structure outside a periphery thereof.

[0024] In a possible implementation, a distribution width of the redundant structure is not less than a minimum value of a pixel unit size in the pixel region.

[0025] Compared with the prior art, the utility model has the following beneficial effects:

[0026] The optoelectronic device array structure comprises a driving wafer and a compound pixel; the compound pixel and the surface of the driving wafer are respectively provided with bonding structures, the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with a mirror layer in the compound pixel; the compound pixel comprises a plurality of pixel units, each pixel unit forms an electrical connection with a first electrode contact in the driving wafer; the periphery of the pixel unit is surrounded by a reflection cavity structure, the reflection cavity structure is connected with the first semiconductor layer, the mirror layer and the outer edge of the bonding structure in the pixel unit, and the first semiconductor layer at least comprises a first partial layer and a second partial layer stacked, the first partial layer is in contact with the mirror layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer; the top of the pixel unit is provided with a second conductive electrode, and the second conductive electrode forms an electrical connection with a second electrode contact in the driving wafer; thus, in the case that the device is provided with the mirror layer at the bottom, the electrical connection of the remaining part of the first semiconductor layer and the electrical enhancement connection of the reflection cavity structure are retained, the electrical connection and the pixel etching to metal leakage problem in the case that there is no transparent conductive thin film or the transparent conductive thin film is extremely thin are solved, the loss of light between the compound and the mirror metal is greatly reduced, and the best brightness improvement is realized. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a method flow chart of a preparation method of an optoelectronic device array structure provided in the embodiment of the application;

[0028] Figure 2 It is a structure schematic diagram of a compound pixel provided in the embodiment of the application;

[0029] Figure 3 It is a structure schematic diagram of a driving wafer provided in the embodiment of the application;

[0030] Figure 4 It is a structure schematic diagram of a bonded device provided in the embodiment of the application;

[0031] Figure 5 It is a structure schematic diagram of a pixelated device provided in the embodiment of the application;

[0032] Figure 6Figure 1 is a schematic diagram of a structure of a pixelated device after isolation according to an embodiment of the application;

[0033] Figure 7 Figure 2 is a schematic diagram of a structure of another pixelated device after isolation according to an embodiment of the application;

[0034] Figure 8 Figure 3 is a schematic diagram of a structure of a device after isolation layer preparation according to an embodiment of the application;

[0035] Figure 9 Figure 4 is a schematic diagram of a structure of another device after isolation layer preparation according to an embodiment of the application;

[0036] Figure 10 Figure 5 is a schematic diagram of a structure of a device after opening preparation according to an embodiment of the application;

[0037] Figure 11 Figure 6 is a schematic diagram of a structure of a device after second conductive pole preparation according to an embodiment of the application;

[0038] Figure 12 Figure 7 is a schematic diagram of a structure of a photovoltaic device array with a first metal mesh structure and a metal fill structure according to an embodiment of the application;

[0039] Figure 13 Figure 8 is a schematic diagram of a structure of a photovoltaic device array with a metal fill structure according to an embodiment of the application;

[0040] Figure 14 Figure 9 is a schematic diagram of a structure of a photovoltaic device array with an in-pixel second electrode contact according to an embodiment of the application;

[0041] Figure 15 Figure 10 is a schematic diagram of a structure of another photovoltaic device array with an in-pixel second electrode contact according to an embodiment of the application;

[0042] Figure 16 Figure 11 is a schematic diagram of a structure of a photovoltaic device array with an optical enhancement structure according to an embodiment of the application;

[0043] Figure 17 Figure 12 is a schematic diagram of a structure of another photovoltaic device array with an optical enhancement structure according to an embodiment of the application;

[0044] Figure 18 Figure 13 is a schematic diagram of a structure of a non-continuous bonding structure according to an embodiment of the application.

[0045] Reference signs:

[0046] 100 - drive wafer, 110 - first electrode contact, 120 - second electrode contact, 200 - compound pixel, 210 - pixel cell, 211 - bonding structure, 212 - mirror layer, 213 - first semiconductor layer, 214 - active layer, 215 - second semiconductor layer, 216 - substrate, 220 - reflective cavity structure, 230 - passivation layer, 240 - side wall structure, 251 - first insulating layer, 252 - second insulating layer, 261 - first metal mesh gate structure, 262 - metal filling structure, 270 - redundancy structure, 280 - second conductive electrode, 290 - microlens. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0048] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0049] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0050] In the embodiments of the present application, by retaining the first semiconductor layer part and the sidewall of the reflection cavity structure during pixelization of the compound, the electrical connection problem when there is no or very thin transparent conductive film and the pixel etching to the metal leakage problem are solved, the light loss between the pixel unit and the metal of the mirror layer is greatly reduced when there is no or very thin transparent conductive film, and the best brightness improvement is achieved.

[0051] Next, the preparation method of the device structure proposed in the present application is described.

[0052] As shown in Figure 1 , the preparation method of the optoelectronic device array structure can include the following steps:

[0053] Step S1: bonding and integrating the driving wafer and the compound pixel through the bonding structure on the surface of each, to form a bonded device, and the bonding structure corresponding to the compound pixel is stacked with a mirror layer and a first semiconductor layer on the side surface away from the driving wafer.

[0054] Specifically, as shown in Figure 2 , Figure 3 , the bonding structure 211 is prepared on the compound pixel 200 and the driving wafer 100, and the bonding structure 211 includes Au, Cu, AuSn, CuSn, etc.

[0055] Among them, the bonding structure 211 can be a patterned discontinuous metal layer, the bonding structure 211 can be continuous only in the pixel area, and the pixel area is the area used for pixel unit preparation, but in the non-pixel area it is a discontinuous film layer, and in the non-pixel area it is filled with insulating medium for support, and the insulating medium can be one or more of SiO2, Si3N4, PI, etc. Medium, the patterned discontinuous metal layer can achieve better bonding warping and metal cost control. For example, in combination with reference to Figure 18 , the bonding structure 211 on the surface of the driving wafer 100 and the bonding structure 211 on the surface of the compound pixel 200 are discontinuous metal layers.

[0056] Among them, as shown in Figure 2 , the bonding structure 211 at the end of the compound pixel 200 can also be stacked with a mirror layer 212, and the mirror layer 212 is used to reflect the light entering the bottom of the compound pixel 200. The mirror layer 212 includes Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, AuBe / Ag, Cr / Pt, Cr / Rh, etc. Metal layer. Further, an adhesion barrier layer can also be provided between the mirror layer 212 and the bonding structure 211, and the adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.

[0057] If necessary, a transparent oxide, such as ITO or ZnO, can be inserted between the mirror layer and the first semiconductor layer as a first semiconductor contact layer to reduce the difficulty of ohmic contact of the first semiconductor layer. The thickness of the transparent oxide is in the range of 0 to 70 nm.

[0058] An adhesion barrier layer may be disposed between the bonding structure at the driving wafer end and the driving wafer. The bonding structure includes Au, Cu, AuSn, CuSn, etc. The adhesion barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.

[0059] An example of a partial cross-section of a single chip showing the fabrication of a compound pixel with a bonded structure and a driving wafer is shown below:

[0060] In one embodiment, the reflective layer at the compound pixel end is a double-layer structure of 10nm ITO and 100nm Al, the adhesion barrier layer is 50nm Ni, 50nm Cr and 50nm Pt, and the bonding structure is a stack of 100nm Au and 100nm Sn.

[0061] In one embodiment, the adhesion barrier layer at the drive wafer end is 50nm Cr and 50nm Pt, and the bonding structure is a stack of 100nm Au and 100nm Sn.

[0062] Furthermore, such as Figure 4 As shown, after bonding and integration between the two wafer surfaces is completed through the bonding structure 211, the substrate 216 on the surface of the compound pixel 200 can be removed.

[0063] In one possible implementation, the fabrication process of the compound pixel includes: directly fabricating a mirror layer on the first semiconductor layer of the compound pixel. That is, instead of fabricating a transparent conductive film as a first semiconductor contact layer on the surface of the first semiconductor layer, the mirror layer can be fabricated directly on it, thereby avoiding optical losses caused by the first semiconductor contact layer. It is understood that, besides not fabricating the first semiconductor contact layer, a first semiconductor contact layer with a thickness of no more than 70 nm can also be fabricated, minimizing the impact of an excessively thick first semiconductor contact layer on the optical performance of the device.

[0064] Step S2: Pixelate the compound pixel in the bonded device by etching a portion of the first semiconductor layer into the compound pixel, leaving the other portion of the first semiconductor layer intact, to obtain a plurality of continuous pixel units on the first semiconductor layer, each pixel unit forming an electrical connection with a first electrode contact in the driving wafer.

[0065] Specifically, as shown in Figure 5 In the pixel array patterning etching, the number of pixel units 210 obtained by etching is not less than 3, each pixel unit 210 is electrically connected with the first electrode contact 110 in the driving wafer 100, and in the patterning etching, the structure of the compound pixel is not completely disconnected, part of the first semiconductor layer 213 is reserved, and the reserved thickness is 30 nm to 400 nm, which can ensure that the active layer 214 is completely disconnected. It can be understood that the figure only exemplarily illustrates that each pixel unit 210 corresponds to one first electrode contact 110, and each pixel unit 210 can also correspond to a plurality of first electrode contacts 110.

[0066] It can be understood that in the pixelation process, the reservation of part of the first semiconductor layer can avoid over-etching to the metal during the pixel patterning etching, thereby avoiding the problem of device failure caused by metal precipitation and leakage.

[0067] Step S3: performing pixel isolation on the continuous multiple pixel units, and preparing a reflective cavity structure around the pixel units, the reflective cavity structure being connected with the outer edges of the first semiconductor layer, the mirror layer and the bonding structure in the pixel units.

[0068] Specifically, as shown in Figure 6 Further performing pixel isolation on the continuous pixel units 210 in the first semiconductor layer 213, completely disconnecting the structure of the compound pixel, to obtain completely isolated individual pixel units 210, and in the pixel isolation process, the reflective cavity structure 220 around each pixel unit 210 is prepared, and the reflective cavity structure 220 is connected with the outer edges of the first semiconductor layer 213, the mirror layer 212 and the bonding structure 211 in the pixel unit 210.

[0069] It can be understood that the reflective cavity structure forms a columnar cavity structure for the pixel unit, and the light waves emitted by the pixel unit can be reflected back and forth in the cavity structure to provide optical positive feedback, thereby greatly improving the light emitting efficiency of the device.

[0070] In a possible implementation, before the pixel isolation on the continuous multiple pixel units, the method further includes the following steps: depositing an insulating medium on the outer surface of the continuous multiple pixel units to prepare a passivation layer; and depositing an insulating medium on the surface of the passivation layer again to prepare a side wall structure.

[0071] Specifically, after the structure shown in Figure 5 and before the structure shown in Figure 6 , as shown in Figure 7As shown, further preparation of the passivation layer 230 and the side wall structure 240 on the pixel unit 210 which is completed by the active layer 214 isolation, the passivation layer 230 is used for passivation protection of the pixel unit 210, and the side wall structure 240 is used for providing support for the subsequent formation of the reflective cavity structure 220. The passivation layer 230 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, silicon nitride, etc. The side wall structure 240 includes a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide, silicon nitride, etc.

[0072] In an embodiment, the compound pixel is etched by a silicon nitride hard mask pattern, a first semiconductor layer of 100 nm is reserved, and then a passivation treatment is performed to form a passivation layer, which can be a dielectric layer of silicon oxide, silicon oxide, silicon nitride, and the thickness of the passivation layer is 10 nm to 200 nm.

[0073] After the preparation of the passivation layer and the side wall structure, the above step S3 can specifically include: performing a first step etching on the side wall structure to reserve the side wall structure of each pixel unit; and performing a second step etching on the continuous passivation layer, the first semiconductor layer, the mirror layer and the bonding structure between adjacent pixel units to complete the preparation of the pixel isolation and the reflective cavity structure.

[0074] The second step etching method includes any one of the following: ion beam etching (IBE) or neutral beam etching (NBE).

[0075] Specifically, the side wall process is used to etch the upper surface of the pixel unit and the side wall structure between the pixel units, only the side wall structure of each pixel unit is reserved, the etching of the side wall structure is completed, and then the IBE or NBE etching scheme is used to prepare the reflective cavity structure which is connected with the side wall of the first semiconductor layer and the bottom layer of the pixel unit. The reflective cavity structure can achieve electrical enhancement. It can be understood that due to the above preparation process, the specific material of the reflective cavity structure is the same as the metal part in the passivation layer, the first semiconductor layer, the mirror layer and the bonding structure during the second step etching.

[0076] Further, after the completion of the second step etching, the following steps are further included: performing full-area filling of the insulating medium on the isolated pixel unit to prepare a first insulating layer; or performing film layer covering of the insulating medium on the isolated pixel unit to prepare a second insulating layer.

[0077] Specifically, the insulating layer is prepared on the device which is completed by the pixel isolation, and the insulating layer can be full-area filled to form a first insulating layer 251 as shown, or can be a non-filled film layer covering to form a second insulating layer 252 as shown. Figure 8 Figure 9 ​The second insulating layer 252 is shown. The first insulating layer 251 or the second insulating layer 252 includes one or a combination of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride, and the present application is not limited thereto.

[0078] Step S4: A second conductive electrode is prepared on the top of the pixel isolation pixel unit, and the second conductive electrode forms an electrical connection with the second electrode contact in the driving wafer.

[0079] In a possible implementation, step S4 can specifically include: performing an opening on the top of the pixel unit to expose the second semiconductor layer of the pixel unit; and performing a conductive film deposition on the top of each pixel unit to form a second conductive electrode, and the second conductive electrode communicates the exposed second semiconductor layer of each pixel unit.

[0080] Specifically, as shown in FIG. 6, an opening is prepared on the top of the pixel unit 210 for the contact of the second conductive electrode 280, and subsequently, the second conductive electrode 280 can be formed on the outer surface of each pixel unit 210 by plating. Figure 10 Figure 8 The structure after the second conductive electrode 280 is prepared according to the structure shown in FIG. 6 can be as shown in FIG. 7. Figure 11

[0081] In a possible implementation, the method further includes the following steps: a first metal mesh structure is prepared in the first insulating layer between adjacent pixel units, the top of the first metal mesh structure is in contact with the second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.

[0082] Specifically, as shown in FIG. 6, in order to achieve electrical enhancement of the second conductive electrode 280, a first metal mesh structure 261 is prepared below the second conductive electrode 280. Figure 12

[0083] In a possible implementation, the method further includes the following steps: a communication metal filling structure is prepared between the second conductive electrode and the second electrode contact.

[0084] Specifically, as shown in FIG. 6, in order to achieve electrical enhancement of the second conductive electrode 280, a first metal mesh structure 261 is prepared below the second conductive electrode 280. Figure 12 Figure 13 ​​​​As shown, in order to realize the electrical connection of the second conductive electrode 280, metal filling is performed between the second conductive electrode 280 and the second electrode contact 120 in the driving wafer 100, and a metal filling structure 262 connecting the two is prepared. The metal filling structure 262 is made of a metal material, such as Al / Ti / Cu, or Al / TiN / Cu, or Al / Ni / Cu, or Al / NiV / Cu, or Al / Ta / Cu, or Al / TaN / Cu, and the above Cu can be replaced by W, and the above structure can also be without Al. The specific type of metal material is not limited in the present application.

[0085] It can be understood that the number of second electrode contacts 120 can be one or a plurality of Figure 14 or Figure 15 As shown, in addition to the second electrode contacts 120 outside the pixel area, one or more second electrode contacts 120 are also arranged in the pixel area. The second electrode contacts 120 in the pixel area can be directly in contact with the second conductive electrode 280, or a metal filling structure 262 connecting the second conductive electrode 280 can be arranged for each second electrode contact 120, and the second electrode contact 120 is in contact with the second conductive electrode 280 through the metal filling structure 262.

[0086] In a possible implementation, the method further includes the following step: synchronously preparing a redundant structure around the periphery of the pixel unit during the preparation of the pixel unit.

[0087] The redundant structure is a structure prepared synchronously with the pixel unit. Unlike the pixel unit, the redundant structure does not need to be in contact with the first electrode contact in the driving wafer, and the size of the redundant structure can be different from the size of the pixel unit.

[0088] Specifically, as shown in Figure 2 to Figure 15 Between the peripheral common cathode and the pixel area, part of the compound pixels is reserved to form a redundant structure 270, to form a higher filling density and improve some steps and density requirements in subsequent semiconductor processes, such as glue trailing, chemical mechanical polishing (CMP), etc. The redundant structure 270 can be a pixel array redundancy or a compound dam structure surrounding the periphery of the pixel array. The distribution width of the redundant structure 270 is not less than the minimum value of the size of the pixel unit in the pixel area. For example, the distribution width of the redundant structure 270 is not less than 10 um.

[0089] In a possible implementation, the method further includes the following step: preparing a second metal mesh structure on the top of the second conductive electrode.

[0090] Specifically, in order to realize the electrical enhancement of the second conductive electrode, a second metal mesh structure is prepared above the second conductive electrode. The second metal mesh structure can be an alloy or a stack of metal materials, such as an alloy of Al, AlCu, AlNi, etc., a stack of Al / TiN, AlCu / TiN, a stack of Al / Ni / Ti / Au, or an alloy or a stack of Au / Ge / Ni / Au.

[0091] In a possible implementation, a microlens, a metasurface or the like optical enhancement structure is prepared on the final structure to realize optical enhancement or optical collimation. As shown in Figure 16 、 Figure 17 indicates that a microlens 290 is prepared as an optical enhancement structure. The microlens 290 can be hemispherical or semi-olive ball-shaped, and a redundant microlens 290 is prepared at the periphery of the pixel array to realize diffuse reflection at the periphery of the pixel array and reduce optical abnormalities such as "ghosting" and the like caused by excessive reflection in the optical module.

[0092] In summary, the preparation method of the photoelectric device array structure provided in the present application integrates the driving wafer and the compound pixel through the bonding structure on the surface of each to form a bonded device. The surface of the compound pixel away from the driving wafer is stacked with a mirror layer and a first semiconductor layer. The compound pixel in the bonded device is pixelated, and the first semiconductor layer in part of the compound pixel is etched to retain another part of the first semiconductor layer, so as to obtain a plurality of pixel units continuous on the first semiconductor layer, each pixel unit being electrically connected with the first electrode contact in the driving wafer. The continuous pixel units are pixel-isolated, and a reflective cavity structure surrounding the pixel units is prepared. The reflective cavity structure is connected with the outer edges of the first semiconductor layer, the mirror layer and the bonding structure in the pixel units. A second conductive electrode is prepared on the top of the pixel units after pixel isolation, and the second conductive electrode is electrically connected with the second electrode contact in the driving wafer. Thus, in the case of the device provided with the bottom mirror layer, the electrical enhancement connection of the retained part of the first semiconductor layer and the reflective cavity structure greatly reduces the loss of light between the compound and the mirror metal, and realizes the best brightness enhancement while solving the electrical connection and pixel etching to metal leakage problem without a transparent conductive film or a very thin transparent conductive film.

[0093] In the present application, as shown in Figure 5 , a photoelectric device array intermediate structure is also provided. The photoelectric device array intermediate structure includes a driving wafer 100 and a compound pixel.

[0094] The compound pixel and the driving wafer 100 are respectively provided with bonding structures 211 on the surface of the driving wafer 100, the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100, and the side surface of the bonding structure 211 corresponding to the compound pixel away from the driving wafer 100 is in contact with the mirror layer 212 in the compound pixel. The compound pixel includes a plurality of pixel units 210, the plurality of pixel units 210 are continuous on the first semiconductor layer 213 in the compound pixel, the first semiconductor layer 213 is arranged on the side surface of the mirror layer 212 away from the driving wafer 100, and each pixel unit 210 is in electrical connection with the first electrode contact 110 in the driving wafer 100.

[0095] The driving wafer 100 can be one or more of the following active designs: thin film transistor (TFT), low temperature polysilicon (LTPS), CMOS integrated circuit, high mobility transistor (HEMT), etc.

[0096] The material of the compound pixel corresponding to the pixel unit 210 can be as follows:

[0097] In the field of Micro-LED, the material of some compound pixels involved in the embodiments of the present application is as shown in the following table, and in some actual applications, the film layer of the compound is more complex, or the materials are cross-used, and the typical main components include P-type contact, N-type contact, active layer sandwiched between the two, and other functional layers.

[0098]

[0099] The contact of the compound is P-type contact and N-type contact, which respectively contacts with the P-type contact layer and the N-type contact layer. The P-type contact corresponds to the barrier layer or the confinement layer or the waveguide layer, and the N-type contact corresponds to the barrier layer or the confinement layer or the waveguide layer. In an embodiment, the P-type contact material includes a single layer or a stack of transparent metal oxides such as ITO, IZO, ZnO, and the like, or a single layer or a stack of metals such as Ni, Cr, Au, Ag, Zn, Be, Al, and the like, or an alloy, or a stack of transparent metal oxides and metals. The N-type contact material includes a single layer or a stack of transparent metal oxides such as ITO, IZO, ZnO, and the like, or a single layer or a stack of metals such as Ni, Cr, Ti, Au, Ge, Al, and the like, or an alloy, or a stack of transparent metal oxides and metals. The deposition of the semiconductor contact layer can be performed by CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), and the like.

[0100] In a possible implementation, a first semiconductor contact layer is arranged between the mirror layer 212 and the first semiconductor layer 213, and the thickness of the first semiconductor contact layer is not greater than 70 nm. By thinning the first semiconductor layer, the influence of the excessive thickness of the first semiconductor contact layer on the optical performance of the device is avoided.

[0101] In summary, the photoelectric device array intermediate structure provided in the present application includes a driving wafer and a compound pixel. The compound pixel and the surface of the driving wafer are respectively provided with bonding structures, the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the mirror layer in the compound pixel. The compound pixel includes a plurality of pixel units, the plurality of pixel units are continuous on the first semiconductor layer in the compound pixel, the first semiconductor layer is arranged on the side surface of the mirror layer away from the driving wafer, and each pixel unit forms an electrical connection with the first electrode contact in the driving wafer. By retaining part of the first semiconductor layer, the problem of over-etching to the metal during the pixel patterning and etching, resulting in the leakage of the metal and the device failure is avoided.

[0102] Further, on the basis of the photoelectric device array intermediate structure described above, the final photoelectric device array structure can be further prepared.

[0103] In the present application, as Figure 11 or Figure 14As shown, the application also provides a photoelectric device array structure, comprising: a driving wafer 100 and a compound pixel.

[0104] The compound pixel and the surface of the driving wafer 100 are respectively provided with bonding structures 211, and the bonding structure 211 corresponding to the compound pixel is in contact with the bonding structure 211 corresponding to the driving wafer 100, and the side surface of the bonding structure 211 corresponding to the compound pixel away from the driving wafer 100 is in contact with the mirror layer 212 in the compound pixel. The compound pixel comprises a plurality of pixel units 210, and each pixel unit 210 forms an electrical connection with the first electrode contact 110 in the driving wafer 100. The outer periphery of the pixel unit 210 is surrounded by a reflection cavity structure 220, and the reflection cavity structure 220 is connected with the outer edge of the first semiconductor layer 213, the mirror layer 212 and the bonding structure 211 in the pixel unit 210, and the first semiconductor layer 213 at least comprises a first partial layer and a second partial layer stacked, the first partial layer is in contact with the mirror layer 212, and the projection of the second partial layer on the driving wafer 100 is within the projection of the first partial layer on the driving wafer 100. The top of the pixel unit 210 is provided with a second conductive electrode 280, and the second conductive electrode 280 forms an electrical connection with the second electrode contact 120 in the driving wafer 100.

[0105] Further, the outer surface of the pixel unit 210 is attached with a passivation layer 230; and the reflection cavity structure 220 is also connected with the outer edge of the passivation layer 230. The passivation layer 230 comprises a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide and silicon nitride.

[0106] Further, the reflection cavity structure 220 and the passivation layer 230 on the side wall surface of the pixel unit 210 are separated by a side wall structure 240. The side wall structure 240 comprises a single layer or a stack of dielectric layers such as aluminum oxide, silicon oxide and silicon nitride.

[0107] Further, as shown in the figure, Figure 11 the outer periphery of the pixel unit 210 is filled with a first insulating layer 251; or, as shown in the figure, Figure 14 the outer periphery of the pixel unit 210 is covered with a thin film type second insulating layer 252. The first insulating layer 251 or the second insulating layer 252 comprises one or a combination of several of silicon oxide, aluminum oxide, silicon nitride and aluminum nitride, which is not limited in the application.

[0108] Further, as shown in the figure, Figure 12As shown, the first insulating layer 251 is filled with a first metal mesh structure 261, the top of the first metal mesh structure 261 is in contact with the second conductive electrode 280, and the bottom of the first metal mesh structure 261 is higher than the surface of the driving wafer 100, thereby enhancing the electrical connection through the first metal mesh structure 261. The first metal mesh structure 261 can be an alloy or a stack of metal materials, such as an alloy of Al, AlCu, AlNi, etc., a stack of Al / TiN, AlCu / TiN, a stack of Al / Ni / Ti / Au, or an alloy or a stack of Au / Ge / Ni / Au.

[0109] Further, as shown in Figure 13 The second conductive electrode 280 and the second electrode contact 120 are connected by a metal filling structure 262, thereby enhancing the electrical connection. The metal filling structure 262 is made of a metal material, such as Al / Ti / Cu, Al / TiN / Cu, Al / Ni / Cu, Al / NiV / Cu, Al / Ta / Cu, or Al / TaN / Cu, and the Cu can be replaced by W. The above structures can also be free of Al, and the specific type of metal material is not limited in the present application.

[0110] Further, a second metal mesh structure is provided on the top of the second conductive electrode 280. The second metal mesh structure can be an alloy or a stack of metal materials, such as an alloy of Al, AlCu, AlNi, etc., a stack of Al / TiN, AlCu / TiN, a stack of Al / Ni / Ti / Au, or an alloy or a stack of Au / Ge / Ni / Au.

[0111] Further, as shown in Figure 14 The inside of the pixel area of the driving wafer 100 is provided with at least one second electrode contact 120, thereby enhancing the electrical connection.

[0112] Further, a first semiconductor contact layer is provided between the mirror layer 212 and the first semiconductor layer 213. In order to avoid the first semiconductor contact layer being too thick, the thickness of the first semiconductor contact layer is not greater than 70 nm.

[0113] Further, a redundant structure 270 is provided around the pixel unit 210. In addition, the distribution width of the redundant structure 270 is not less than the minimum value of the pixel unit size in the pixel area.

[0114] In summary, the photoelectric device array structure provided by the application comprises a driving wafer and a compound pixel; the compound pixel and the surface of the driving wafer are respectively provided with bonding structures, the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with a mirror layer in the compound pixel; the compound pixel comprises a plurality of pixel units, each pixel unit is in electrical connection with a first electrode contact in the driving wafer; the periphery of the pixel unit is surrounded by a reflection cavity structure, the reflection cavity structure is connected with the outer edge of the bonding structure, the first semiconductor layer, the mirror layer and the pixel unit, and the first semiconductor layer at least comprises a first partial layer and a second partial layer which are stacked, the first partial layer is in contact with the mirror layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer; the top of the pixel unit is provided with a second conductive electrode, and the second conductive electrode is in electrical connection with a second electrode contact in the driving wafer; thus, in the case that the device is provided with the mirror layer at the bottom, the electrical connection of the retained partial first semiconductor layer and the electrical enhancement connection of the reflection cavity structure can solve the electrical connection and the pixel etching to metal leakage problem without a transparent conductive film or a very thin transparent conductive film, greatly reduce the loss of light between the compound and the mirror metal, and achieve the best brightness improvement.

[0115] All the optional technical solutions described above can be combined to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0116] It should be noted that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array structure of optoelectronic devices, characterized by, The optoelectronic device array structure comprises a driving wafer and a compound pixel. The compound pixel and the surface of the driving wafer are respectively provided with bonding structures, and the bonding structure corresponding to the compound pixel is in contact with the bonding structure corresponding to the driving wafer, and the side surface of the bonding structure corresponding to the compound pixel away from the driving wafer is in contact with the mirror layer in the compound pixel. The compound pixel comprises a plurality of mutually isolated pixel units, and each pixel unit is electrically connected with a first electrode contact in the driving wafer. The outer periphery of the pixel unit is surrounded by a reflection cavity structure, and the reflection cavity structure is connected with the outer edge of the first semiconductor layer, the mirror layer, and the bonding structure in the pixel unit, and the first semiconductor layer at least comprises a stacked first partial layer and a second partial layer, the first partial layer is in contact with the mirror layer, and the projection of the second partial layer on the driving wafer is within the projection of the first partial layer on the driving wafer. The top of the pixel unit is provided with a second conductive electrode, and the second conductive electrode is electrically connected with a second electrode contact in the driving wafer.

2. The optoelectronic device array structure according to claim 1, wherein The outer surface of the pixel unit is attached with a passivation layer. The reflection cavity structure is also connected with the outer edge of the passivation layer.

3. The optoelectronic device array structure according to claim 2, wherein The reflection cavity structure and the passivation layer on the sidewall surface of the pixel unit are separated by a sidewall structure.

4. The optoelectronic device array structure according to claim 1, wherein The outer periphery of the pixel unit is filled with a first insulating layer. Or, The outer periphery of the pixel unit is covered with a second insulating layer in a thin film pattern.

5. The optoelectronic device array structure according to claim 4, wherein The first insulating layer is filled with a first metal mesh structure, the top of the first metal mesh structure is in contact with the second conductive electrode, and the bottom of the first metal mesh structure is higher than the surface of the driving wafer.

6. The optoelectronic device array structure according to claim 1, wherein A metal filling structure is arranged between the second conductive electrode and the second electrode contact.

7. The optoelectronic device array structure according to claim 1, wherein A second metal mesh structure is further arranged on the top of the second conductive electrode.

8. The optoelectronic device array structure according to claim 1, wherein At least one second electrode contact is arranged in the pixel area of the driving wafer.

9. The optoelectronic device array structure according to claim 1, wherein A first semiconductor contact layer is arranged between the mirror layer and the first semiconductor layer.

10. The optoelectronic device array structure according to claim 9, wherein The thickness of the first semiconductor contact layer is not greater than 70 nm.

11. The optoelectronic device array structure according to claim 1, wherein A redundant structure is arranged on the outer periphery of the pixel unit.

12. The optoelectronic device array structure according to claim 11, characterized in that, The distribution width of the redundant structure is not less than the minimum pixel unit size in the pixel region.

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