Packaging structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises a first substrate; the second substrate is positioned above the first substrate and is electrically connected with the first substrate; the chip unit is arranged above the first substrate and is electrically connected with the first substrate; the heat dissipation assembly is arranged above the chip unit; wherein the lower surface of the second substrate is higher than the upper surface of the chip unit, the second substrate and the chip unit are staggered in the vertical direction, and the second substrate shields part of the chip unit in the vertical direction. The utility model has the advantages that the heat dissipation performance is good, the area of the substrate is not increased, and the stability of the product during working can be improved while the miniaturization requirement of the product size can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular, to a packaging structure. BACKGROUND

[0002] In existing semiconductor products, the packaging structure with substrates on both upper and lower sides has poor heat dissipation performance, which cannot meet the miniaturization requirement of the product size while ensuring the stability of the product during operation.

[0003] In view of the above, there is a need in the art to provide a packaging structure that can overcome the defects of the prior art. CONTENT OF THE INVENTION

[0004] The present application provides a packaging structure that can solve the problems of the prior art. The purpose of the present application is achieved by the following technical solutions.

[0005] One embodiment of the present application provides a packaging structure, comprising: a first substrate; a second substrate located above the first substrate and electrically connected to the first substrate; a chip unit arranged above the first substrate and electrically connected to the first substrate; and a heat dissipation assembly arranged above the chip unit; wherein the lower surface of the second substrate is higher than the upper surface of the chip unit, the second substrate is staggered with the chip unit in the vertical direction, and the second substrate blocks part of the chip unit in the vertical direction.

[0006] In some optional embodiments, the packaging structure according to the above embodiment of the present application, wherein the width of the second substrate is smaller than the width of the first substrate.

[0007] In some optional embodiments, the packaging structure according to the above embodiment of the present application, wherein the packaging structure further comprises an electronic element arranged above the second substrate and electrically connected to the second substrate.

[0008] In some optional embodiments, the packaging structure according to the above embodiment of the present application, wherein the packaging structure further comprises a mold encapsulation layer covering the upper surface of the first substrate, the lower surface and the side surface of the second substrate, and the side surface and part of the upper surface of the chip unit.

[0009] In some optional embodiments, the packaging structure according to the above embodiment of the present application, wherein the upper surface of the mold encapsulation layer is flush with the upper surface of the second substrate.

[0010] In some optional embodiments, the packaging structure according to the above embodiment of the present application, wherein the packaging structure further comprises a heat-conducting adhesive between the heat dissipation assembly and the chip unit, and the upper surface of the heat-conducting adhesive is connected to the heat dissipation assembly.

[0011] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the part of the upper surface of the chip unit is exposed from the mold layer, and the opening of the mold layer exposing the chip unit has a shape of being wide at the top and narrow at the bottom.

[0012] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the height of the upper surface of the chip unit is lower than the height of the upper surface of the mold layer.

[0013] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the chip unit comprises a protruding part of the main body part, the protruding part is located at the side of the main body part close to the second substrate and connected with the main body part, the lower surface of the protruding part is flush with the lower surface of the main body part and the thickness of the protruding part is lower than the thickness of the main body part.

[0014] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the mold layer covers the upper surface and the side surface of the protruding part, the upper surface of the main body part is exposed from the mold layer and the upper surface of the main body part is flush with the upper surface of the mold layer.

[0015] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the second substrate is staggered with the main body in the vertical direction, and the second substrate blocks part or all of the protruding part in the vertical direction.

[0016] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the lower surface of the heat-conducting glue is connected with the upper surface of the chip unit.

[0017] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the mold layer further covers the upper surface of the chip unit.

[0018] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the second substrate comprises a first flat part and a second flat part, the second flat part is located at the side of the first flat part close to the chip unit and connected with the first flat part, the upper surface of the second flat part is flush with the upper surface of the first flat part and the thickness of the second flat part is smaller than the thickness of the first flat part.

[0019] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the second flat part is partially located above the chip unit.

[0020] In some alternative embodiments, the packaging structure according to the above-mentioned one of the embodiments of the present application, wherein the lower surface of the heat-conducting glue is connected with the mold layer located at the upper surface of the chip unit.

[0021] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the packaging structure further comprises a first electrical connector and a second electrical connector, the second substrate is electrically connected to the first substrate through the first electrical connector, and the electronic component is electrically connected to the second substrate through the second electrical connector.

[0022] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the number of the first electrical connectors is less than the number of the second electrical connectors.

[0023] The packaging structure according to the embodiments of the present application has the advantages of good heat dissipation performance and no increase in the substrate area, which can meet the demand of miniaturization of products and improve the stability of products during operation. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as provided in conjunction with the accompanying drawings.

[0025] Figure 1 A schematic diagram of a packaging structure according to one embodiment of the present application is shown;

[0026] Figure 2 A schematic diagram of a chip unit in the packaging structure according to one embodiment of the present application is shown; Figure 1 A schematic diagram of a manufacturing process of the packaging structure according to one embodiment of the present application is shown;

[0027] Figure 3 A schematic diagram of a packaging structure according to a second embodiment of the present application is shown;

[0028] Figure 4 A schematic diagram of a chip unit in the packaging structure according to a second embodiment of the present application is shown; Figure 3 A schematic diagram of a manufacturing process of the packaging structure according to a second embodiment of the present application is shown;

[0029] Figure 5 A schematic diagram of a packaging structure according to a third embodiment of the present application is shown;

[0030] Figure 6-1 A schematic diagram of a chip unit in the packaging structure according to a third embodiment of the present application is shown; Figure 6-2 A schematic diagram of a manufacturing process of the chip unit in the packaging structure according to a third embodiment of the present application is shown; Figure 5 A schematic diagram of a manufacturing process of the packaging structure according to a third embodiment of the present application is shown;

[0031] Figure 7 A schematic diagram of a manufacturing process of the packaging structure according to a third embodiment of the present application is shown; Figure 5 A schematic diagram of a manufacturing process of the packaging structure according to a third embodiment of the present application is shown;

[0032] Figure 8 A schematic diagram of a packaging structure according to a fourth embodiment of the present application is shown; A schematic diagram of a chip unit in the packaging structure according to a fourth embodiment of the present application is shown;

[0033] Figure 9 A package structure according to a fourth embodiment of the present application is shown. Figure 8 A manufacturing flow diagram of a package structure according to a fourth embodiment of the present application is shown.

[0034] Reference signs and component names: 1-first substrate, 2-second substrate, 3-chip unit, 4-heat dissipation component, 5-electronic element, 6-mold layer, 7-thermally conductive adhesive, 8-first electrical connecting member, 9-second electrical connecting member, 21-first flat plate portion, 22-second flat plate portion, 31-main body portion, 32-protruding portion, 300-chip group, 301-groove. DETAILED DESCRIPTION

[0035] The specific embodiments of the present application will be described below in conjunction with the drawings and examples, and those skilled in the art can clearly and completely understand the technical solutions of the present application, the technical problems solved, and the technical effects produced through the content described in the specification. It can be understood that the specific embodiments described herein are only used to explain the present application, and not to limit the present application. In addition, only parts related to the present application are shown in the drawings for ease of description.

[0036] It should be readily understood that the meanings of "on", "over", and "above" in the present application should be interpreted in the broadest manner, such that "on" not only means "directly on" but also means "on" including the presence of intermediate components or layers between them.

[0037] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "over", "upper" and the like can be used herein to describe the relationship of one element or component to another element or component shown in the drawings. In addition to the orientation described in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0038] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are for the purpose of illustrating the content of the specification, for the understanding and reading of the person skilled in the art, and do not serve to define the limiting conditions of the implementation of the present application, and therefore do not have technical substantive significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "first", "second" and "one" cited in the specification are only for the purpose of clear understanding and description, and are not used to limit the scope of the implementation of the present application. The change or adjustment of the relative relationship, without substantial change of the technical content, is also regarded as the scope of the implementation of the present application.

[0039] The term "layer" as used herein refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an extent that is less than the underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers and can have the same or different materials.

[0040] The term "electrical connection" as used herein can be a pad or a bump. Among them, the bump can be, for example, a gold bump (usually rectangular, gold), a solder bump (usually circular, copper plus tin), a pillar bump (usually columnar octagonal or polygonal, copper plus tin or lead plus tin).

[0041] As used herein, the term "molding compound" or "molding compound layer" includes, but is not limited to, epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, and the like.

[0042] In addition, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0043] Figure 1 A schematic diagram of a packaging structure according to one embodiment of the present application is shown. As shown, the packaging structure includes a first substrate 1, a second substrate 2 located above the first substrate 1 and electrically connected to the first substrate 1, a chip unit 3 disposed above the first substrate 1 and electrically connected to the first substrate 1, and a heat dissipation assembly 4 disposed above the chip unit 3. The lower surface of the second substrate 2 is higher than the upper surface of the chip unit 3, the second substrate 2 is staggered with the chip unit 3 in the vertical direction, and the second substrate 2 blocks part of the chip unit 3 in the vertical direction. Figure 1

[0044] In some optional embodiments, the packaging structure according to one embodiment of the present application is provided, wherein the width of the second substrate 2 is smaller than the width of the first substrate 1.

[0045] In some optional embodiments, the packaging structure according to one embodiment of the present application is provided, wherein the packaging structure further includes an electronic element 5 disposed above the second substrate 2 and electrically connected to the second substrate 2.

[0046] In some optional embodiments, the packaging structure according to one embodiment of the present application is provided, wherein the packaging structure further includes a molding compound layer 6 covering the upper surface of the first substrate 1, the lower surface and the side surface of the second substrate 2, and the side surface and part of the upper surface of the chip unit 3.

[0047] In some optional embodiments, the packaging structure according to one embodiment of the present application is provided, wherein the upper surface of the molding compound layer 6 is flush with the upper surface of the second substrate 2.

[0048] ​In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the packaging structure further comprises a thermal conductive glue 7, the thermal conductive glue 7 is located between the heat dissipation component 4 and the chip unit 3, and the upper surface of the thermal conductive glue 7 is connected with the heat dissipation component 4.

[0049] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein part of the upper surface of the chip unit 3 is exposed from the mold sealing layer 6, and the opening of the chip unit 3 exposed from the mold sealing layer 6 is formed by laser etching, so that the opening of the chip unit 3 exposed from the mold sealing layer 6 is in the shape of wide at the top and narrow at the bottom (not shown in the figure).

[0050] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the height of the upper surface of the chip unit 3 is lower than the height of the upper surface of the mold sealing layer 6.

[0051] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the packaging structure further comprises a first electrical connection 8 and a second electrical connection 9, the first electrical connection 8 supports the second substrate 2, and the second substrate 2 is electrically connected with the first substrate 1 through the first electrical connection 8, and the electronic component 5 is electrically connected with the second substrate 2 through the second electrical connection 9.

[0052] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the number of the first electrical connection 8 is less than the number of the second electrical connection 9.

[0053] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the height of the first electrical connection 8 is greater than the height of the second electrical connection 9.

[0054] In some alternative embodiments, the packaging structure according to one of the above embodiments of the present application, wherein the lower surface of the thermal conductive glue 7 is connected with the upper surface of the chip unit 3.

[0055] Figure 2 The manufacturing process of the packaging structure according to one embodiment of the present application is shown as Figure 1 The production process of the packaging structure includes the following steps: Figure 2

[0056] Step 1001: providing the first substrate 1 and setting the chip unit 3 on the first substrate 1;

[0057] Step 1002: setting the second substrate 2 above the first substrate 1, and electrically connecting the second substrate 2 with the first substrate 1 through the first electrical connection 8, wherein part of the second substrate 2 is located above the chip unit 3; ​

[0058] Step 1003: filling a mold encapsulation layer 6 between the first substrate 1 and the second substrate 2, the mold encapsulation layer 6 covering the upper surface of the first substrate 1, the lower surface and the side surface of the second substrate 2, the chip unit 3 and the first electrical connection 8;

[0059] Step 1004: removing part of the mold encapsulation layer 6 above the chip unit 3, exposing part of the upper surface of the chip unit 3 from the mold encapsulation layer 6, disposing an electronic component 5 above the second substrate 2, the electronic component 5 being electrically connected to the second substrate 2 through the second electrical connection 9; and

[0060] Step 1005: disposing a heat dissipation component 4 on the upper surface of the chip unit 3 exposed from the mold encapsulation layer 6, the heat dissipation component 4 being connected to the chip unit 3 through the thermal conductive glue 7.

[0061] Figure 3 A schematic diagram of a packaging structure according to a second embodiment of the present application is shown. As shown, the mold encapsulation layer 6 also covers the upper surface of the chip unit 3. Figure 3

[0062] In some optional embodiments, the packaging structure provided by the above-mentioned one embodiment of the present application, wherein the lower surface of the thermal conductive glue 7 is connected to the mold encapsulation layer 6 located on the upper surface of the chip unit 3.

[0063] Figure 4 A schematic diagram of a manufacturing process of a packaging structure according to a second embodiment of the present application is shown. As shown, the manufacturing process of the packaging structure of the second embodiment includes a plurality of steps: Figure 3 Figure 4 As shown, the manufacturing process of the packaging structure of the second embodiment includes a plurality of steps:

[0064] Step 2001: providing a first substrate 1 and disposing a chip unit 3 on the first substrate 1;

[0065] Step 2002: disposing a second substrate 2 above the first substrate 1, the second substrate 2 being electrically connected to the first substrate 1 through the first electrical connection 8, wherein part of the second substrate 2 is located above the chip unit 3;

[0066] Step 2003: filling a mold encapsulation layer 6 between the first substrate 1 and the second substrate 2, the mold encapsulation layer 6 covering the upper surface of the first substrate 1, the lower surface and the side surface of the second substrate 2, the chip unit 3 and the first electrical connection 8;

[0067] Step 2004: disposing an electronic component 5 above the second substrate 2, the electronic component 5 being electrically connected to the second substrate 2 through the second electrical connection 9, disposing a heat dissipation component 4 on the upper surface of the mold encapsulation layer 6 above the chip unit 3, the heat dissipation component 4 being connected to the mold encapsulation layer 6 through the thermal conductive glue 7.

[0068] Figure 5 ​​A schematic diagram of the packaging structure according to a third embodiment of this application is shown. Figure 5 As shown, the chip unit 3 includes a protrusion 32 of the main body 31. The protrusion 32 is located on the side of the main body 31 near the second substrate 2 and is connected to the main body 31. The lower surface of the protrusion 32 is flush with the lower surface of the main body 31 and the thickness of the protrusion 32 is lower than the thickness of the main body 31.

[0069] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the molding layer 6 covers the upper surface and side surface of the protrusion 32, the upper surface of the main body 31 is exposed from the molding layer 6 and the upper surface of the main body 31 is flush with the upper surface of the molding layer 6.

[0070] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the second substrate 2 is offset from the body in the vertical direction, and the second substrate 2 blocks part or all of the protrusion 32 in the vertical direction.

[0071] Figure 6-1 and Figure 6-2 As shown Figure 5 The diagram shows a manufacturing process of a chip cell in a packaging structure according to a third embodiment of this application. Figure 6-1 and Figure 6-2 As shown, the chip cell manufacturing process of the packaging structure in the third embodiment includes multiple steps:

[0072] Step 3001: Provide chipset 300;

[0073] Step 3002: Create a recess 301 on the chipset 300; and

[0074] Step 3003: Cut the chip assembly 300 along the edge of the groove 301 to obtain the chip unit 3, wherein the chip unit 3 includes a protrusion 32 of the main body 31, the protrusion 32 is located on one side of the main body 31 and connected to the main body 31.

[0075] Figure 7 As shown Figure 5 The diagram shows a manufacturing process schematic of the packaging structure according to the third embodiment of this application. Figure 7 As shown, the manufacturing process of the packaging structure in the third embodiment includes several steps:

[0076] Step 3004: Provide a first substrate 1 and arrange chip units 3 on the first substrate 1, wherein the lower surface of the protrusion 32 and the lower surface of the main body 31 are connected to the upper surface of the first substrate 1.

[0077] Step 3005: disposing a second substrate 2 above the first substrate 1, the second substrate 2 being electrically connected with the first substrate 1 by the first electrical connecting member 8, wherein part of the second substrate 2 is above the protruding portion 32, and the upper surface of the second substrate 2 is flush with the upper surface of the main body portion 31;

[0078] Step 3006: filling a mold encapsulation layer 6 between the first substrate 1 and the second substrate 2, the mold encapsulation layer 6 covering the upper surface of the protruding portion 32, the lower surface and the side surface of the second substrate 2, the chip unit 3 and the first electrical connecting member 8, and the upper surface of the mold encapsulation layer 6 being flush with the upper surfaces of the second substrate 2 and the main body portion 31; and

[0079] Step 3007: disposing an electronic element 5 above the second substrate 2, the electronic element 5 being electrically connected with the second substrate 2 by the second electrical connecting member 9, and disposing a heat dissipation component 4 on the upper surface of the main body portion 31, the heat dissipation component 4 being connected with the main body portion 31 by the heat conductive adhesive 7.

[0080] Figure 8 A schematic diagram of a packaging structure according to a fourth embodiment of the present application is shown. As shown in Figure 8 the second substrate 2 includes a first flat portion 21 and a second flat portion 22, the second flat portion 22 being located on the side of the first flat portion 21 close to the chip unit 3 and being connected with the first flat portion 21, and the upper surface of the second flat portion 22 being flush with the upper surface of the first flat portion 21 and the thickness of the second flat portion 22 being less than the thickness of the first flat portion 21.

[0081] In some optional embodiments, the packaging structure according to one of the embodiments of the present application is provided, wherein the second flat portion 22 is partially above the chip unit 3.

[0082] Figure 9 A schematic diagram of a manufacturing process of the packaging structure according to the fourth embodiment of the present application is shown. As shown in Figure 8 the manufacturing process of the packaging structure according to the fourth embodiment includes the following steps: Figure 9

[0083] Step 4001: providing a first substrate 1 and disposing a chip unit 3 on the first substrate 1;

[0084] Step 4002: disposing a second substrate 2 above the first substrate 1, the second substrate 2 being electrically connected with the first substrate 1 by the first electrical connecting member 8, wherein the second substrate 2 includes a first flat portion 21 and a second flat portion 22, the upper surface of the second flat portion 22 being flush with the upper surface of the first flat portion 21 and the thickness of the second flat portion 22 being less than the thickness of the first flat portion 21, and part of the second flat portion 22 being above the chip unit 3;

[0085] ​Step 4003: filling a mold sealing layer 6 between the first substrate 1 and the second substrate 2, the mold sealing layer 6 covering the upper surface of the first substrate 1, the lower surface and the side surface of the second substrate 2, the chip unit 3 and the first electrical connection 8;

[0086] Step 4004: disposing the electronic element 5 above the second substrate 2, the electronic element 5 being electrically connected to the second substrate 2 through the second electrical connection 9, disposing the heat dissipation component 4 on the upper surface of the mold sealing layer 6 above the chip unit 3, the heat dissipation component 4 being connected to the mold sealing layer 6 through the heat conductive glue 7.

[0087] The packaging structure according to the embodiments of the present application has the advantages of good heat dissipation performance and no increase in the area of the substrate, and can meet the demand for miniaturization of products and improve the stability of the products in operation.

[0088] Although the present application has been described and illustrated with reference to the particular embodiments, the description and illustrations have been made by way of example only, and are not intended to limit the application. It is understood that various changes can be completed without departing from the scope of the application as defined by the claims. There can be differences between the technology in the present application and the actual equipment due to variables in the manufacturing process, etc. There can be other embodiments of the present application that are not specifically described. The specification and drawings should be considered illustrative only and not restrictive, and modifications can be made according to the purpose and spirit of the present application, all of which are within the scope of the claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be recombined, subdivided or arranged in equivalent methods without departing from the teachings of the present application. Therefore, the order and grouping of operations are not limiting to the present application unless specifically indicated herein.

Claims

1. A package structure, characterized by, The package structure comprises: a first substrate; a second substrate above the first substrate and electrically connected to the first substrate; a chip unit above the first substrate and electrically connected to the first substrate; a heat dissipation component above the chip unit; wherein the lower surface of the second substrate is higher than the upper surface of the chip unit, the second substrate is staggered with the chip unit in the vertical direction and the second substrate shields part of the chip unit in the vertical direction.

2. The package structure of claim 1, wherein, The width of the second substrate is smaller than the width of the first substrate.

3. The package structure of claim 2, wherein, The package structure further comprises a mold encapsulation layer covering the upper surface of the first substrate, the lower surface and side surface of the second substrate, and the side surface and part of the upper surface of the chip unit.

4. The package structure of claim 3, wherein, Part of the upper surface of the chip unit is exposed from the mold encapsulation layer, and the opening of the chip unit exposed on the mold encapsulation layer is in the shape of wide at the top and narrow at the bottom.

5. The package structure of claim 4, wherein, The height of the upper surface of the chip unit is lower than the height of the upper surface of the mold encapsulation layer.

6. The package structure of claim 4, wherein, The chip unit comprises a protruding part of the main body part, the protruding part is located at the side of the main body part close to the second substrate and connected to the main body part, the lower surface of the protruding part is flush with the lower surface of the main body part and the thickness of the protruding part is lower than the thickness of the main body part.

7. The package structure of claim 6, wherein, The mold encapsulation layer covers the upper surface and side surface of the protruding part, the upper surface of the main body part is exposed from the mold encapsulation layer and flush with the upper surface of the mold encapsulation layer.

8. The package structure of claim 6, wherein, The second substrate is staggered with the main body in the vertical direction, and the second substrate shields part or all of the protruding part in the vertical direction.

9. The package structure of claim 3, wherein, The second substrate comprises a first flat part and a second flat part, the second flat part is located at the side of the first flat part close to the chip unit and connected to the first flat part, the upper surface of the second flat part is flush with the upper surface of the first flat part and the thickness of the second flat part is smaller than the thickness of the first flat part.

10. The package structure of claim 9, wherein, Part of the second flat part is above the chip unit.

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