Semiconductor device

Abstract

The utility model relates to a semiconductor device. The vertically stacked semiconductor device comprises a first device structure which is bonded to a second device structure through a bonding layer with a compressible metal bonding structure. The compressible metal bond structure is fabricated using a chemical deposition process and has a lower density and a greater degree of compressibility than the equivalent material deposited by the related process. Thus, the mating metal bonding structure has a degree of compliance, enabling effective metal-to-metal contact during a subsequent bonding process. Recrystallization of the metal material during the annealing process results in shrinkage of the metal material and forms void regions between the metal bond and the surrounding dielectric layer, thereby reducing stresses on the surrounding dielectric and dielectric interface. Therefore, bonding defects can be minimized and the efficiency and yield of vertically stacked semiconductor devices can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, particularly a semiconductor device with metal junctions. BACKGROUND

[0002] The semiconductor industry has developed due to the ever increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.).

[0003] In addition to smaller electronic components, improvements in packaging of components have been developed in an effort to provide smaller packages that occupy less area than previous packages. Example methods include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), three-dimensional integrated circuit (3DIC), wafer level package (WLP), package on package (PoP), system on chip (SoC), or system on integrated circuit (SoIC) devices. These three-dimensional devices are fabricated by placing chips on top of chips. These three-dimensional devices provide improved integration density and other advantages due to the reduced interconnect length between stacked chips, however, there are many challenges associated with three-dimensional devices.

[0004] WLP), package on package (PoP), system on chip (SoC), or system on integrated circuit (SoIC) devices. These three-dimensional devices are fabricated by placing chips on top of chips. These three-dimensional devices provide improved integration density and other advantages due to the reduced interconnect length between stacked chips, however, there are many challenges associated with three-dimensional devices. SUMMARY

[0005] The present disclosure provides a semiconductor device. The semiconductor device includes a first device structure, a second device structure, and a plurality of metal junctions. The first device structure includes a first semiconductor substrate, a plurality of first devices, a first interconnect structure, and a first dielectric layer. The second device structure includes a second semiconductor substrate, a plurality of second devices, a second interconnect structure, and a second dielectric layer. The first dielectric layer contacts the second dielectric layer. The metal junctions extend between the first device structure and the second device structure. A plurality of void regions are between each of the metal junctions and a plurality of side surfaces of the first dielectric layer and the second dielectric layer.

[0006] A semiconductor device is provided. The semiconductor device includes a first device structure, a second device structure, and a plurality of metal junctions. The first device structure includes a first semiconductor substrate, a plurality of first devices, a first interconnect structure, and a first dielectric layer. The second device structure includes a second semiconductor substrate, a plurality of second devices, a second interconnect structure, and a second dielectric layer. The first dielectric layer contacts the second dielectric layer. Each of the metal junctions extends between the first device structure and the second device structure. Each of the metal junctions includes at least 1 at% boron, phosphorus, and / or sulfur, including oxides thereof. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the present disclosure can be better understood with reference to the following detailed description and examples in conjunction with the following drawings, in which:

[0008] Figure 1 is a vertical cross-sectional view of an intermediate first device structure showing a first device structure according to various embodiments of the present disclosure.

[0009] Figure 2 is a vertical cross-sectional view of an intermediate first device structure after forming a first dielectric layer over a first interconnect structure according to various embodiments of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of an intermediate first device structure after forming a patterned mask over an upper surface of the first dielectric layer according to various embodiments of the present disclosure.

[0011] Figure 4 is a vertical cross-sectional view of an intermediate first device structure after forming a plurality of openings in the first dielectric layer according to various embodiments of the present disclosure.

[0012] Figure 5 is a vertical cross-sectional view of an intermediate first device structure after forming a plurality of first metal junction structures formed within the openings in the first dielectric layer according to various embodiments of the present disclosure.

[0013] Figure 6 is a vertical cross-sectional view of an intermediate first device structure after aligning a second device structure over the first element device according to embodiments of the present disclosure.

[0014] Figure 7 is a vertical cross-sectional view of a second device structure placed on a first device structure according to various embodiments of the present disclosure.

[0015] Figure 8is a vertical cross-sectional view of a vertical stack of semiconductor devices according to various embodiments of the present disclosure showing a first metal bonding structure of a first bonding layer bonded to a second metal bonding structure of a second bonding layer after an anneal process.

[0016] Figure 9A is a vertical cross-sectional view of a second device structure placed on a first device structure according to another embodiment of the present disclosure.

[0017] Figure 9B is a vertical cross-sectional view of a vertical stack of semiconductor devices according to various embodiments of the present disclosure showing a first metal bonding structure of a first bonding layer bonded to a second metal bonding structure of a second bonding layer after an anneal process.

[0018] Figure 10A is a vertical cross-sectional view of a second device structure placed on a first device structure according to another embodiment of the present disclosure.

[0019] Figure 10B is a vertical cross-sectional view of a vertical stack of semiconductor devices according to various embodiments of the present disclosure showing a first metal bonding structure of a first bonding layer bonded to a second metal bonding structure of a second bonding layer after an anneal process.

[0020] Figure 11 is a vertical cross-sectional view of a first device structure including a first interconnect structure and a first dielectric layer formed over the first interconnect structure according to various embodiments of the present disclosure.

[0021] Figure 12 is a vertical cross-sectional view of an intermediate first device structure after forming a plurality of openings in the first dielectric layer according to various embodiments of the present disclosure.

[0022] Figure 13 is a vertical cross-sectional view of an intermediate first device structure after forming a plurality of first metal bonding structures within the openings in the first dielectric layer according to various embodiments of the present disclosure.

[0023] Figure 14 is a vertical cross-sectional view of a second device structure placed on a first device structure according to various embodiments of the present disclosure.

[0024] Figure 15 is a vertical cross-sectional view of a vertical stack of semiconductor devices according to various embodiments of the present disclosure showing a first metal bonding structure of a first bonding layer bonded to a second metal bonding structure of a second bonding layer after an anneal process.

[0025] Figure 16 is a flowchart of a method of fabricating a vertical stack of semiconductor devices according to an embodiment of the present disclosure.

[0026] Reference signs are explained below:

[0027] 100: first device structure

[0028] 101: first semiconductor substrate

[0029] 103: first device level

[0030] 104: first dielectric material

[0031] 105: first metal feature

[0032] 106: first top metal feature

[0033] 117: front surface

[0034] 118: back surface

[0035] 107: first dielectric layer

[0036] 109: mask

[0037] 108: first metal bonding structure

[0038] 110: first bonding layer

[0039] h: height

[0040] 200: second device structure

[0041] 201: second semiconductor substrate

[0042] 203: second device level

[0043] 204: second dielectric material

[0044] 205: second metal feature

[0045] 206: second top metal feature

[0046] 207: second dielectric layer

[0047] 208: second metal bonding structure

[0048] 210: second bonding layer

[0049] 217: front surface

[0050] 218: back surface

[0051] 300: semiconductor device

[0052] 301: void region

[0053] w: maximum width

[0054] 112: interface

[0055] 113: metal joint

[0056] 127: continuous layer

[0057] 227: second dielectric layer

[0058] 401: method

[0059] 402-410: operations DETAILED DESCRIPTION

[0060] The present disclosure provides many different embodiments or examples to implement different features of the present case. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the scope of the present case. For example, the present disclosure can describe a first feature formed on or over a second feature, which can include embodiments where the first feature is directly on the second feature or where additional features can be formed between the first feature and the second feature such that the first feature can not be directly on the second feature. Also, the different embodiments described throughout the present disclosure can use the same reference symbols throughout the drawings and / or text to indicate the same or similar parts.

[0061] In addition, spatially relative terms are used herein for ease of description to illustrate different positions and orientations of a device in use or operation. The terms "below", "under", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as drawn in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, for example, the device can be otherwise rotated or otherwise oriented (rotated 90 degrees or at other orientation) in use or operation, and the spatially relative terms commensurate therewith. Unless otherwise noted, the term "about" preceding a value means ±10% of the value. Unless specifically stated otherwise, each instance of an element or feature described herein can be replaced with any other instance of the same element or feature. Notably, not all implementations of the disclosure will include all of the features described. Those of ordinary skill in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents for specific implementations of the disclosure.

[0062] Various embodiments disclosed herein relate to semiconductor devices, and in particular to vertically stacked semiconductor devices that include at least one semiconductor die stacked above and bonded to a second device structure, which can be another semiconductor die or a semiconductor wafer, for example. The at least one semiconductor die can be vertically stacked in a configuration such as system integrated chip (SoIC), chip-on-wafer-on-substrate (CoWoS), chip on wafer (CoW), etc. Such vertically stacked semiconductor devices can increase the density of devices that can occupy a given planar area or "footprint."

[0063] A semiconductor die can include a semiconductor material substrate, such as a silicon substrate, having a plurality of circuit components and elements formed on and / or within the semiconductor material. Semiconductor dies are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate (e.g., a wafer), patterning the various material layers using photolithography to form integrated circuits, and separating individual dies from the substrate (e.g., sawing along scribe lines between integrated circuits).

[0064] A first semiconductor device structure can be placed on a second semiconductor device structure in a "face down" configuration to form a vertically stacked semiconductor device such that integrated circuit components formed on a first side (i.e., front side) of a semiconductor substrate of the first semiconductor device structure face integrated circuit components formed on a front side of a semiconductor substrate of the second semiconductor device structure. The first semiconductor device structure and the second semiconductor device structure can be, for example, semiconductor dies, semiconductor wafers, or a combination thereof (e.g., semiconductor dies on a semiconductor wafer). Bonding processes can be used to bond bonding features on the first semiconductor device structure to corresponding bonding features on the second semiconductor device structure.

[0065] In some embodiments, direct bonding techniques (e.g., metal-to-metal (M-M) and dielectric-to-dielectric (D-D) bonding techniques) can be used to bond the first semiconductor device structure and the second semiconductor device structure to form a vertically stacked semiconductor device. In such bonding techniques, a bonding layer comprising an array of metal bonding pads surrounded by a dielectric material can be formed on both the first semiconductor device structure and the second semiconductor device structure. The bonding layer on the first semiconductor device structure can be aligned above the corresponding bonding layer on the second semiconductor device structure, and the two bonding layers can be brought into contact with each other. This can result in chemical pre-bonding between the dielectric materials of the respective bonding layers. An annealing process can then be performed to facilitate bonding of the metal bonding pads of the respective bonding layers, resulting in a metal bond extending between the first semiconductor device structure and the second semiconductor device structure.

[0066] In many cases, the process window for performing successful direct metal-to-metal (M-M) and dielectric-to-dielectric (D-D) bonding between two semiconductor device structures can be relatively small, particularly when the size of the metal bonding pads and the spacing (i.e., pitch) between the bonding pads in the respective bonding layers are reduced in order to provide higher performance and greater energy efficiency in the vertically stacked semiconductor device. One important parameter during the bonding process is the amount of “dishing” of the metal bonding pads in the bonding layers. “Dishing” can be defined as the difference in height between the lowest point of the metal bonding pad (typically at the center of the pad) and the highest point of the dielectric material laterally surrounding the bonding pad. Excessive dishing can result in defective bonding (i.e., metal disconnection defects) between the metal pads in the respective bonding layers. Furthermore, in some cases, the expansion of the metal pads during the annealing process can create high stress at the metal-to-metal interface. This stress can result in delamination defects at the dielectric-to-dielectric interface surrounding the metal pads. Metal disconnection defects and / or dielectric delamination defects should be avoided as they can negatively impact the performance of the vertically stacked semiconductor device and can reduce device yield.

[0067] To improve the reliability of the joint between the first device structure and the second device structure in a vertically stacked semiconductor device, various embodiments disclosed herein can include a joint layer having a compressible metal joint structure. In various embodiments, the compressible metal joint structure can be fabricated using an electroless deposition (ED) process. Electroless deposition is a chemical deposition process that utilizes a redox reaction to reduce metal ions from a chemical solution onto a target surface, resulting in the deposition of a metal material onto the surface. The metal material deposited through the ED process can be less dense than equivalent materials deposited through related processes (e.g., through electroplating), and can have a greater degree of compressibility (i.e., a lower Young’s modulus). Accordingly, the mating metal joint structures formed from ED can have a degree of compliance that can enable effective metal-to-metal contact during subsequent jointing processes. Furthermore, the recrystallization of the chemically deposited metal material during an anneal process can result in shrinkage of the metal material and the formation of void regions between the metal joint and surrounding dielectric layers, thereby reducing stress on the surrounding dielectric and dielectric interfaces. Accordingly, jointing defects (e.g., metal disconnection defects and / or dielectric delamination defects) can be minimized, and the performance and yield of the vertically stacked semiconductor device can be improved.

[0068] Figures 1 to 8 is a sequential vertical cross-sectional view showing an intermediate structure during a process of fabricating a vertically stacked semiconductor device according to various embodiments of the present disclosure. Figure 1 is a vertical cross-sectional view showing a first device structure 100 according to various embodiments of the present disclosure. The first device structure 100 can include a first semiconductor substrate 101, which can include elemental semiconductors (e.g., silicon or germanium) and / or compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide) or the same combination. Other semiconductor substrate materials are also within the contemplation of the present disclosure. In some embodiments, the first semiconductor substrate 101 can be a semiconductor-on-insulator (SOI) substrate.

[0069] The first semiconductor substrate 101 can include a first major surface (i.e., front surface 117) and a second major surface (i.e., back surface 118). In some embodiments, the thickness of the first semiconductor substrate 101 between the front surface 117 and the back surface 118 can be between about 100 pm and about 800 pm, although semiconductor substrates 101 having greater or lesser thicknesses can also be utilized. A first device level 103 can be disposed on / in the front surface 117 of the first semiconductor substrate 101. The first device level 103 can include a plurality of devices, which can include active devices, passive devices, or combinations thereof. In some embodiments, the devices in the first device level 103 can include integrated circuit devices. Such devices can be, for example, transistors (e.g., field-effect transistors (FETs)), capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the first device level 103 can include gate electrodes, source / drain regions, spacers, etc.

[0070] The first semiconductor die 100 can also include a first interconnect structure over the first device level 103 on the front surface 117 of the first semiconductor substrate 101. The first interconnect structure can include first metal features 105 formed within a first dielectric material 104. The first dielectric material 104 can include one or more layers of dielectric material, such as at least one inter-layer dielectric (ILD) layer and / or at least one inter-metal dielectric (IMD) layer. The one or more layers of first dielectric material 104 can be formed from suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), silicon oxynitride, etc. Other dielectric materials are also within the contemplated scope of the present disclosure. Any suitable deposition process can be used to deposit the one or more layers of first dielectric material 104. Herein, a “suitable deposition process” can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma CVD (HDPCVD) process, a low pressure CVD process, a metal organic CVD (MOCVD) process, a plasma enhanced CVD (PECVD) process, a sputtering process, a laser ablation, etc.

[0071] The first semiconductor die 100 can also include a first interconnect structure over the first device level 103 on the front surface 117 of the first semiconductor substrate 101. The first interconnect structure can include first metal features 105 formed within a first dielectric material 104. The first dielectric material 104 can include one or more layers of dielectric material, such as at least one inter-layer dielectric (ILD) layer and / or at least one inter-metal dielectric (IMD) layer. The one or more layers of first dielectric material 104 can be formed from suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), silicon oxynitride, etc. Other dielectric materials are also within the contemplated scope of the present disclosure. Any suitable deposition process can be used to deposit the one or more layers of first dielectric material 104. Herein, a “suitable deposition process” can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma CVD (HDPCVD) process, a low pressure CVD process, a metal organic CVD (MOCVD) process, a plasma enhanced CVD (PECVD) process, a sputtering process, a laser ablation, etc.

[0072] In various embodiments, the first metal features 105 of the first interconnect structure can include a plurality of metal vias and metal lines extending within the first dielectric material 104. The first metal features 105 can be formed of any suitable conductive material, such as copper (Cu), tungsten (W), and aluminum (Al), including alloys and combinations thereof. Other conductive materials are also within the contemplation of the present disclosure. In some embodiments, a barrier layer (not shown) can be disposed between the first metal features 105 and the first dielectric material 104 to prevent the conductive material of the first metal features 105 from diffusing to surrounding features. The barrier layer can include, for example, Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other barrier layer materials are also within the contemplation of the present disclosure. The first metal features 105 and optional barrier layer can be formed using suitable deposition processes, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof. The first metal features 105 of the first interconnect structure can be configured to route electrical signals to, from, and / or between various elements of the first device structure 100, some or all of which can be located on the first device level 103. In addition, the first metal features 105 can route electrical signals to, from, and / or between various elements of the first device structure 100 to various devices of a subsequent stacked device structure (e.g., the second device structure 200). The first metal features 105 can include first top metal features 106 exposed in an upper surface of the first interconnect structure. The first top metal features 106 can include metal pads laterally surrounded by the first dielectric material 104. In some embodiments, the first top metal features 106 can form a periodic array of first top metal features 106 over the upper surface of the first interconnect structure of the first device structure 100.

[0073] In some embodiments, the first device structure 100 can be a semiconductor die. In other embodiments, the first device structure 100 can include a portion of a semiconductor substrate 101 (i.e., a semiconductor wafer) on which the first device and first interconnect structure are formed, which can be subsequently singulated (e.g., diced) to form one or more semiconductor dies.

[0074] Figure 2is a vertical cross-sectional view of a first device structure 100 showing a first dielectric layer 107 formed over a first interconnect structure in accordance with various embodiments of the present disclosure. The first dielectric layer 107 can comprise a suitable dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, etc., including various combinations thereof, and can be formed using a suitable deposition process as described above. In some embodiments described in further detail below, the first dielectric layer 107 can comprise a dielectric polymer material. The first dielectric layer 107 can have a planar upper surface as shown. Figure 2

[0075] Figure 3 is a vertical cross-sectional view of a first device structure 100 showing a patterned mask 109 formed over an upper surface of the first dielectric layer 107 in accordance with various embodiments of the present disclosure. Referring to Figure 3 The patterned mask 109 (which can comprise a photoresist and / or a hard mask) can be patterned using photolithography techniques to form a plurality of openings through the mask 109. Each opening through the patterned mask 109 can cover a respective first top metal feature 106 of the first interconnect structure of the first device structure 100.

[0076] Figure 4 is a vertical cross-sectional view of a first device structure 100 showing a plurality of openings in the first dielectric layer 107 in accordance with various embodiments of the present disclosure. Referring to Figure 4 An anisotropic etch process (such as a reactive ion etch process) can be performed to etch a plurality of portions of the first dielectric layer 107 exposed through the openings in the patterned mask 109 and thereby form openings through the first dielectric layer 107. The first top metal features 106 can be exposed at a bottom of each opening through the first dielectric layer 107. After the etch process, the patterned mask 109 can be removed using a suitable process such as through ashing or dissolution using a solvent.

[0077] Figure 5 is a vertical cross-sectional view of a first device structure 100 showing a plurality of first metal joint structures 108 formed within the openings in the first dielectric layer 107 in accordance with various embodiments of the present disclosure. Referring to Figure 5 A metal material can be deposited over the exposed first top metal features 106 at the bottom of the openings through the first dielectric layer 107 using a suitable deposition process. In some embodiments, the metal material can be deposited using an electroless deposition process as described in further detail below. The metal material can fill a volume of each opening through the first dielectric layer 107 to provide a plurality of first metal joint structures 108 laterally surrounded by the first dielectric layer 107. The first metal joint structures 108 can have a convex upper surface as shown. Figure 5 ​The upper surface of each first metal bonding structure 108 can extend a height h above the planar upper surface of the first dielectric layer 107. In some embodiments, the upper surface of the first metal bonding structure 108 can extend at least about 1 nm in height h above the planar upper surface of the first dielectric layer 107.

[0078] Referring again to FIG. 1A Figure 5 The first dielectric layer 107 and the plurality of first metal bonding structures 108 can form a first bonding layer 110 of the first device structure 100. The first bonding layer 110 can be configured to enable bonding of the first device structure 100 to a second device structure to form a vertically stacked semiconductor device via direct bonding techniques, such as metal-to-metal (M-M) and dielectric-to-dielectric (D-D) bonding techniques.

[0079] In various embodiments, the first metal bonding structures 108 of the first bonding layer 110 can have a relatively lower density and a higher degree of compressibility (e.g., have a lower Young’s modulus) than metal bonding structures used in related direct bonding. In some embodiments, an electroless deposition (ED) process can be used to form the first metal bonding structures 108 having a relatively low density and high compressibility. Electroless deposition is a process of depositing a material with the aid of a chemical reducing agent in solution. The ED process is based on redox chemistry, in which electrons are released from a reducing agent and metal ions (i.e., cations) within the solution are reduced to a metal or metal alloy that can be deposited on a target surface. The ED process is autocatalytic, meaning that the deposited metal material can act as a catalyst for further reduction reactions, enabling the deposition to continue in a self-sustaining manner. The ED process also does not require the application of external power or current.

[0080] In various embodiments, the surfaces of the first device structure 100 on which the metal bonding structure 108 will be deposited (e.g., the exposed upper surface of the first top metal pad 106 and / or the side surfaces of the first dielectric layer 107 within each opening of the first dielectric layer 107) may be pretreated (e.g., decontaminated) and optionally functionalized using a suitable catalyst (e.g., palladium). This can facilitate selective deposition of metallic material within the openings of the first dielectric layer 107, while deposition is minimal or absent in other areas of the first device structure 100 (e.g., above the upper surface of the first dielectric layer 107). The first device structure 100 may be immersed in a solution (i.e., an ED bath) comprising appropriate amounts of a reducing agent, a metal ion source (e.g., a metal salt), and optional other components (e.g., one or more complexing agents or stabilizers), a pH-adjusting buffer, and / or other suitable additives. Suitable reducing agents in the ED bath may include (but are not limited to) sodium hypophosphite, potassium hypophosphite, sodium borohydride, formaldehyde, hydrazine, dimethylamine borane, etc. Other suitable reducing agents are within the scope of this disclosure. Suitable metal ion sources in the ED bath may include (but are not limited to) nickel chloride, copper sulfate, palladium chloride, gold cyanide, gold chloride, silver nitrate, etc. Other suitable metal ion sources are also within the scope of this disclosure.

[0081] The first device structure 100 can be held in an ED bath until a desired amount of metal material is deposited within the openings through the first dielectric layer 107. In some embodiments, the deposited metal material can fill the entire volume of each opening through the first dielectric layer 107, such that the upper surface of the first metal bonding structure 108 can be coplanar with or extend above the upper surface of the first dielectric layer 107. In various embodiments, each first metal bonding structure 108 may include a convex upper surface that extends at least about 1 nm above the plane of the upper surface of the first dielectric layer 107, such as... Figure 5As shown. Because the first metal joint structure 108 can be selectively deposited within the opening through the first dielectric layer 107, a planarization process (e.g., a chemical mechanical planarization (CMP) process) can not be needed to remove excess metal material from above the upper surface of the first dielectric layer 107. This can be in contrast to related metal joint structures formed using an electroplating deposition process, which typically require a planarization operation to remove excess metal material. However, such a planarization process can result in the metal joint structure being overly “dished” (i.e., such that portions of the metal joint structure can be recessed relative to the upper surface of the first dielectric layer 107), which can increase the risk of metal disconnection defects occurring during subsequent joining of the first device structure 100 to a second device structure. Conversely, the first metal joint structure 108 according to various embodiments of the present disclosure can extend to or above the plane of the upper surface of the first dielectric layer 107, which can help ensure good metal-to-metal contact and mitigate metal disconnection defects during subsequent joining processes.

[0082] The metal joint structure 108 formed by ED can include suitable metal materials, such as copper, gold, silver, nickel, platinum, palladium, etc., including combinations and alloys thereof. Other suitable metal materials are also within the contemplation of the present disclosure. In one non-limiting embodiment, the metal joint structure 108 can include a gold / copper alloy finish to inhibit oxidation. The metal joint structure 108 can additionally include one or more non-metallic elements, such as boron, phosphorous, and / or sulfur. Such non-metallic elements can originate from the reducing agent used in the ED bath solution and can be incorporated into a coating deposited on the target surface. In some embodiments, the metal joint structure 108 can include at least about 1 at% (e.g.: ~1 at% to ~35 at%) of a non-metallic component, such as boron, phosphorous, and / or sulfur, including oxides thereof.

[0083] In various embodiments, the first metal joint structure 108 formed by the ED process can have a lower density than metal joint structures used in related direct bonding techniques using an electroplating deposition process. This can be due to the loose structure of the metal material formed by the ED process due to trapped impurities and vacancies. For example, a copper first metal joint structure 108 formed by the ED process can have a density between about 8.76 g / cm3and about 8.86 g / cm3, as compared to a density of about 8.96 g / cm3for an equivalent copper joint structure formed by an electroplating deposition process. In another example, a nickel first metal joint structure 108 formed by the ED process can have a density between about 8.76 g / cm3and about 8.86 g / cm3, as compared to a density of about 8.91 g / cm3for an equivalent nickel joint structure formed by an electroplating deposition process. 3 3 3 In various embodiments, the first metal joint structure 108 formed by the ED process can have a lower density than metal joint structures used in related direct bonding techniques using an electroplating deposition process. This can be due to the loose structure of the metal material formed by the ED process due to trapped impurities and vacancies. For example, a copper first metal joint structure 108 formed by the ED process can have a density between about 8.76 g / cm3and about 8.86 g / cm3, as compared to a density of about 8.96 g / cm3for an equivalent copper joint structure formed by an electroplating deposition process. In another example, a nickel first metal joint structure 108 formed by the ED process can have a density between about 8.76 g / cm3and about 8.86 g / cm3, as compared to a density of about 8.91 g / cm3for an equivalent nickel joint structure formed by an electroplating deposition process.​​3 Compared to other materials, the nickel first metal bonding structure 108 formed by the ED process can have a density of approximately 7.75 g / cm³. 3 With approximately 8.5 g / cm 3 The density between them. Generally speaking, the first metal bonding structure 108 formed by the ED process according to various embodiments can have a density at least about 1% lower than that of an equivalent metal bonding structure formed by the electroplating deposition process, including at least about 2%, at least about 4%, or at least about 10%. The lower density of the first metal bonding structure 108 according to various embodiments can provide a greater degree of compressibility. Therefore, during subsequent bonding processes, the mating metal bonding structures 108 can have a degree of compliance that enables effective metal-to-metal and dielectric-to-dielectric contact without causing high stress at the metal-to-metal interface, thereby reducing the risk of delamination defects during the bonding process.

[0084] Figure 6 This is a vertical cross-sectional view of a second device structure 200 aligned above the first device structure 100, according to an embodiment of this disclosure. Figure 6 In the illustrated embodiment, the second device structure 200 is a semiconductor die; however, it should be understood that in other embodiments, the second device structure 200 may be another structure, such as a semiconductor wafer. The second device structure 200 may have a structure similar to the first device structure 100. The second device structure 200 may include a second semiconductor substrate 201. The second semiconductor substrate 201 may be made of the same semiconductor material as the first semiconductor substrate 101, or may be made of a different semiconductor material. The second semiconductor substrate 201 may include a first main surface (i.e., front surface 217) and a second main surface (i.e., back surface 218). A second device layer 203 may be disposed on / in the front surface 217 of the second semiconductor substrate 201, and the second interconnect structure includes a second metal feature 205 (e.g., metal wires and vias) embedded in a second dielectric material 204, the second dielectric material 204 being located above the second device layer 203. The second device layer 203 and the second interconnect structure of the second device structure 200 may be similar to those referenced above. Figure 1 The first device structure 100 described includes a first device layer 103 and a first interconnection structure. Therefore, for the sake of brevity, repeated discussion of similar components is omitted.

[0085] The second device structure 200 may also include a second engagement feature disposed above the front surface 217 of the second device structure 200. Figure 6In the illustrated embodiment second device structure 200, the second bonding features include a second bonding layer 210 over the second interconnect structure. Like the first bonding layer 110 described above, the second bonding layer 210 can include a plurality of second metal bonding structures 208 laterally surrounded by a second dielectric layer 207. The second metal bonding structures 208 can have the same configuration as the first metal bonding structures 108 described above with reference to the first device structure 100. Thus, for the sake of brevity, repeated discussion of similar features is omitted. In some embodiments, the second metal bonding structures 208 can be formed using an electroless deposition (ED) process. The arrangement of the second metal bonding structures 208 in the second bonding layer 210 can correspond to the arrangement of the first metal bonding structures 108 in the first bonding layer 110. In some embodiments, the second metal bonding structures 208 can be formed using a physical vapor deposition (PVD) process. Figure 5 The second metal bonding structures 208 of the second bonding layer 210 can have the same size and shape as the first metal bonding structures 108 of the first bonding layer 110 in embodiments. The second bonding layer 210 can be configured to enable metal-to-metal (M-M) and dielectric-to-dielectric (D-D) direct bonding between the second bonding layer 210 of the second device structure 200 and the first bonding layer 110 of the first device structure 100 to bond the second device structure 200 and the first device structure 100 to form a vertically stacked semiconductor device. Figure 6 The second metal bonding structures 208 of the second bonding layer 210 can have the same size and shape as the first metal bonding structures 108 of the first bonding layer 110 in embodiments. The second bonding layer 210 can be configured to enable metal-to-metal (M-M) and dielectric-to-dielectric (D-D) direct bonding between the second bonding layer 210 of the second device structure 200 and the first bonding layer 110 of the first device structure 100 to bond the second device structure 200 and the first device structure 100 to form a vertically stacked semiconductor device.

[0086] Referring again to Figure 6 , the first device structure 100 and the second device structure 200 can be oriented in an "face-to-face" alignment such that the first bonding layer 110 of the first device structure 100 can face the second bonding layer 210 of the second device structure 200. Each of the first metal bonding structures 108 of the first bonding layer 110 can be aligned with a corresponding second metal bonding structure 208 of the second bonding layer 210. In some embodiments, the surface of the first bonding layer 110 on the first device structure 100 and / or the second bonding layer 210 on the second device structure 200 can optionally be subjected to a pre-treatment process (e.g., a plasma treatment process) to facilitate surface activation of the first bonding layer 110 and / or the second bonding layer 210 prior to bonding the first device structure 100 to the second device structure 200.

[0087] Figure 7is a vertical cross-sectional view showing a second device structure 200 placed on a first device structure 100 according to various embodiments of the present disclosure. In various embodiments, the second device structure 200 and the first device structure 100 can be placed together such that the first bonding layer 110 of the first device structure 100 contacts the second bonding layer 210 of the second device structure 200. The second device structure 200 can be aligned over a front surface of the first device structure 100 such that the second metal bonding structures 208 of the second bonding layer 210 of the second device structure 200 contact corresponding first metal bonding structures 108 of the first bonding layer 110 of the first device structure 100, and a surface of the second dielectric layer 207 of the second bonding layer 210 of the second device structure 200 contacts a surface of the first dielectric layer 107 of the first bonding layer 110 of the first device structure 100.

[0088] Referring again to Figure 7 In a direct bonding process, such as a metal-to-metal (M-M) and dielectric-to-dielectric (D-D) bonding process, having the second bonding layer 210 of the second device structure 200 contact the first bonding layer 110 of the first device structure 100 can result in a pre-bonding process in which chemical bonds (e.g., hydrogen bridge bonds) can form at the planar interface between the second dielectric layer 207 of the second bonding layer 210 and the first dielectric layer 107 of the first bonding layer 110. In some embodiments, the pre-bonding process can be performed at ambient temperature (e.g., ~20°C). In other embodiments, the pre-bonding process can be performed at an elevated temperature. In some embodiments, a compressive force can be applied to the first device structure 100 and the second device structure 200 during the pre-bonding process. In other embodiments, no compressive force can be applied during the pre-bonding process.

[0089] Figure 8 is a vertical cross-sectional view showing a vertically stacked semiconductor device 300 after an annealing process according to various embodiments of the present disclosure, which completes the bonding of the first metal bonding structures 108 of the first bonding layer 110 with the second metal bonding structures 208 of the second bonding layer 210. Referring to Figure 8 When the first bonding layer 110 of the first device structure 100 contacts the second bonding layer 210 of the second device structure 200, the first device structure 100 and the second device structure 200 can be subjected to an annealing process at an elevated temperature. In some embodiments, the peak temperature of the annealing process can be between about 250°C and about 350°C, although lower and higher temperatures can also be utilized. In some embodiments, a compressive force can be applied to the first device structure 100 and the second device structure 200 during the annealing process. In other embodiments, no compressive force can be applied during the annealing process.

[0090] In various embodiments, the annealing process can promote the interdiffusion of metallic materials at the interface 112 between the first metal bonding structure 108 of the first bonding layer 110 and the corresponding second metal bonding structure 208 of the second bonding layer 210, thereby forming a plurality of metal bondings 113 that mechanically and electrically couple the first device structure 100 to the second device structure 200 to provide a vertically stacked semiconductor device 300. Each metal bonding 113 may include a suitable metallic material and may also include at least about 1 at% (e.g., ~1 at% to ~35 at%) of a nonmetallic component, such as boron, phosphorus, and / or sulfur, including their oxides. The annealing process can also cause recrystallization of the metallic materials of the first metal bonding structure 108 and the second metal bonding structure 208, which can lead to shrinkage of the first metal bonding structure 108 and the second metal bonding structure 208. After the annealing process, the first metal bonding structure 108 and the second metal bonding structure 208 may have an increased density and may have lower compressibility (i.e., a higher Young's modulus) compared to before the annealing process. In some embodiments, the Young's modulus of the first metal bonding structure 108 and / or the second metal bonding structure 208 may increase by at least about 5% during the annealing process, including at least about 8%, at least about 10%, or at least about 15%.

[0091] After the annealing process, void region 301 may exist between the metal bond 113 and the side surfaces of the first dielectric layer 107 and the second dielectric layer 207 that laterally surround the metal bond 113, such as Figure 8 As shown. Due to the aforementioned shrinkage of the materials of the first metal bonding structure 108 and the second metal bonding structure 208 during the annealing process, a void region 301 may be formed. In some embodiments, the maximum width w of the void region 301 between the metal bonding 113 and the surrounding side surfaces of the first dielectric layer 107 and / or the second dielectric layer 207 may be at least about 100 nm. The void region 301 may be located at the planar interface between the first dielectric layer 107 of the first bonding layer 110 and the second dielectric layer 107 of the second bonding layer 210.

[0092] After bonding the first element structure 100 to the second element structure 200 to form a vertically stacked semiconductor device 300, additional operations can be performed, such as thinning the back surfaces 118, 218 of the first semiconductor substrate 101 and / or the second semiconductor substrate 201 to expose through-substrate vias (TSVs). Figure 8 (Not shown in the figure) An interconnect layer including dielectric material and metal features is formed on the back surface 118, 218 of the first semiconductor substrate 101 and / or the second semiconductor substrate 201, and a bonding feature (e.g., metal bonding pad) is formed on the interconnect layer, which is electrically coupled to the TSV through the metal feature of the interconnect layer.

[0093] Figure 9A is a vertical cross-sectional view showing the second device structure 200 placed on the first device structure 100 according to another embodiment of the disclosure. Figure 9A The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 9A The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The first device structure 100 and the second device structure 200 shown differ from the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The first device structure 100 and the second device structure 200 shown differ from the first device structure 100 and the second device structure 200 shown above with reference to

[0094] Figure 9B is a vertical cross-sectional view showing the second device structure 200 placed on the first device structure 100 according to another embodiment of the disclosure. Figure 9B The annealing process as described above with reference to Figure 8 may be performed to form a plurality of metal junctions 113 that mechanically and electrically couple the first device structure 100 to the second device structure 200 to provide a vertically stacked semiconductor device 300. A plurality of portions of the metal junctions 113 adjacent to the first top metal pads 106 of the first interconnect structures of the first device structure 100 can have a greater width than a plurality of portions of the metal junctions 113 adjacent to the second top metal junctions 206 of the second interconnect structures of the second device structure 200. Shrinkage of the metal material of the first metal junction structures 108 and the second metal junction structures 208 can cause void regions 301 to exist between the metal junctions 113 and side surfaces of the first dielectric layers 107 and the second dielectric layers 207 that laterally surround the metal junctions 113, as shown above with reference to Figure 9BThe maximum width of the void region 301 between the metal joint 113 and the surrounding side surface of the first dielectric layer 107 and / or the second dielectric layer 207 can be at least about 100 nm in some embodiments. The void region 301 can be located adjacent to the planar interface between the first dielectric layer 107 and the second dielectric layer 207. In Figure 9B some embodiments, the void region 301 can also expose a horizontally-extending surface of the second dielectric layer 207 that was in contact with the first metal joint structure 108 prior to the annealing process.

[0095] Figure 10A is a vertical cross-sectional view showing the second device structure 200 placed on the first device structure 100 according to another embodiment of the present disclosure. Figure 10A The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 10A The first device structure 100 and the second device structure 200 shown are similar to the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The first device structure 100 and the second device structure 200 shown differ from the first device structure 100 and the second device structure 200 shown above with reference to Figure 7 The second device structure 200 can be brought into contact with the first device structure 100 such that the second bonding layer 210 contacts the first bonding layer 110, as described above with reference to The second device structure 200 can be brought into contact with the first device structure 100 such that the second bonding layer 210 contacts the first bonding layer 110, as described above with reference to

[0096] The second device structure 200 can be brought into contact with the first device structure 100 such that the second bonding layer 210 contacts the first bonding layer 110, as described above with reference to Figure 10B is a vertical cross-sectional view showing the second device structure 200 placed on the first device structure 100 according to another embodiment of the present disclosure. Figure 10B The second device structure 200 can be brought into contact with the first device structure 100 such that the second bonding layer 210 contacts the first bonding layer 110, as described above with reference to Figure 8The annealing process forms a plurality of metal joints 113 that mechanically and electrically couple the first device structure 100 to the second device structure 200 to provide a vertically stacked semiconductor device 300. The metal joints 113 can extend at an oblique angle with respect to a planar interface between the first dielectric layer 107 and the second dielectric layer 207. Contraction of the metal material of the first metal joint structure 108 and the second metal joint structure 208 can cause a void region 301 to exist between the metal joint 113 and side surfaces of the first dielectric layer 107 and the second dielectric layer 207 that laterally surround the metal joint 113, as shown in Figure 10B In some embodiments, a maximum width of the void region 301 between the metal joint 113 and the surrounding side surfaces of the first dielectric layer 107 and / or the second dielectric layer 207 can be at least about 100 nm. The void region 301 can be located adjacent to the planar interface between the first dielectric layer 107 and the second dielectric layer 207. In Figure 10B embodiments, the void region 301 can also expose a horizontally extending surface of the second dielectric layer 207 that was in contact with the first metal joint structure 108 prior to the annealing process, in addition to a horizontally extending portion of the first dielectric layer 107 that was in contact with the second metal joint structure 208 prior to the annealing process.

[0097] Although Figure 10A and Figure 10B embodiments show the laterally offset first metal joint structure 108 and the second metal joint structure 208 having the same size and shape, it should be understood that the first metal joint structure 108 and the second metal joint structure 208 can have different sizes and / or shapes. For example, a width of the first metal joint structure 108 can not equal a width of the second metal joint structure 208, as shown in Figure 9A and Figure 9B .

[0098] Figures 11 to 15 is a sequence of vertical cross-sectional views showing an intermediate structure during a process of fabricating a vertically stacked semiconductor device according to another embodiment of the disclosure. Figure 11 is a vertical cross-sectional view showing a first device structure 100 that includes a first interconnect structure and a first dielectric layer 127 formed over the first interconnect structure according to various embodiments of the disclosure. Figure 11 The first device structure 100 of Figure 2 may be similar to the first device structure 100 described above with reference to Figure 11 . Accordingly, repeated discussion of similar features is omitted for the sake of brevity. Figure 2The first device structure 100 differs from the second device structure 200 in that the first dielectric layer 127 formed over the first interconnect structure includes a dielectric polymer material. Suitable dielectric polymer materials for the first dielectric layer 127 can include benzocyclobutene (BCB), parylene, and / or polyimide. Other suitable dielectric polymer materials are within the contemplation of the present disclosure. The first dielectric layer 127 can be formed using a suitable deposition process, such as spin coating, screen printing, spray coating, lamination, chemical vapor deposition (CVD), and the like. The first dielectric layer 127 including a dielectric polymer material can have a planar upper surface.

[0099] Figure 12 is a vertical cross-sectional view of the first device structure 100 showing a plurality of openings in the first dielectric layer 127 in accordance with various embodiments of the present disclosure. Reference is made to Figure 12 A plurality of openings can be formed through the first dielectric layer 127. Each opening can correspond to a location of a first metal joint structure to be subsequently formed. The first top metal feature 106 can be exposed at the bottom of each opening through the first dielectric layer 107.

[0100] In embodiments where the first dielectric layer 127 is composed of a photosensitive (i.e., photoimageable) dielectric polymer material, such as benzocyclobutene (BCB), parylene, and / or polyimide material, the openings through the first dielectric layer 127 can be formed using a photolithography process. In one non-limiting example, a continuous layer of the photosensitive dielectric polymer material 127 can be coated or deposited over the first interconnect structure of the first device structure 100. Selected portions of the photosensitive dielectric polymer material can be exposed to light radiation (e.g., UV radiation) through a patterned mask. Exposure to the light radiation can chemically alter the photosensitive dielectric polymer material by making the exposed portions of the photosensitive dielectric polymer material more or less soluble relative to the surrounding material not exposed to the light radiation. Thus, by selectively exposing a plurality of portions of the photosensitive dielectric polymer material to the light radiation through the patterned mask, the mask pattern can be transferred to the photosensitive dielectric polymer material. A developing process can be used to remove the more soluble portions of the photosensitive dielectric polymer material to provide a plurality of openings through the first dielectric layer 127. Other suitable methods for forming a plurality of openings through the first dielectric layer 127 can be utilized, such as a laser drilling process, an etching process through a photolithography patterned mask, and the like. In some embodiments, the first dielectric layer 127 can include a non-photosensitive dielectric polymer material.

[0101] Figure 13is a vertical cross-sectional view showing a first device structure 100 of a plurality of first metal bonding structures 108 formed within openings in a first dielectric layer 127 according to various embodiments of the present disclosure. Figure 13 The first metal bonding structures 108 can have a similar or identical construction as the first metal bonding structures 108 described above with reference to Figure 5 and can be formed using similar or identical methods. Accordingly, repeated discussion of similar features is omitted for the sake of brevity. In various embodiments, the first metal bonding structures 108 can include a low-density, high-compressibility metal material that can be deposited using an electroless deposition (ED) process as described above.

[0102] Figure 14 is a vertical cross-sectional view showing a second device structure 200 placed on the first device structure 100 according to various embodiments of the present disclosure. In Figure 14 embodiments, the second device structure 200 is a semiconductor die, but it should be understood that in other embodiments, the second device structure 200 can be another structure, such as a semiconductor wafer. The second device structure 200 can have a similar structure as the first device structure 100 and can include a second semiconductor substrate 201, a second device level 203 disposed on / in a front surface 217 of the second semiconductor substrate 201, a second interconnect structure including second metal features 205 (e.g., metal lines and vias) embedded in a second dielectric material 204 and a second top metal feature 206, and a second bonding layer 210 over the second interconnect structure. The second bonding layer 210 can include a plurality of second metal bonding structures 208 laterally surrounded by a second dielectric layer 227. The second metal bonding structures 208 can have a similar or identical construction as the first metal bonding structures 108 in the first bonding layer 110 of the first device structure 100. In some embodiments, the second dielectric layer 227 of the second bonding layer 210 can include a dielectric polymer material as described above with reference to Figure 11 .

[0103] Referring again to Figure 14 , the second device structure 200 and the first device structure 100 can be placed together such that the first bonding layer 110 of the first device structure 100 contacts the second bonding layer 210 of the second device structure 200. The second device structure 200 can be aligned over a front surface of the first device structure 100 such that the second metal bonding structures 208 of the second bonding layer 210 of the second device structure 200 contact corresponding first metal bonding structures 108 of the first bonding layer 110 of the first device structure 100, and a surface of the second dielectric layer 227 of the second bonding layer 210 of the second device structure 200 contacts a surface of the first dielectric layer 127 of the first bonding layer 110 of the first device structure 100. As described above with reference toFigure 7 The contacting of the second bonding layer 210 of the second device structure 200 with the first bonding layer 110 of the first device structure 100 can result in a pre-bonding process in which chemical bonds (e.g., hydrogen bridge bonds) can be formed at the planar interface between the second dielectric layer 227 of the second bonding layer 210 and the first dielectric layer 127 of the first bonding layer 110. In some embodiments, the pre-bonding process can be performed at ambient temperature (e.g., ~20°C). In other embodiments, the pre-bonding process can be performed at an elevated temperature. In some embodiments, a compressive force can be applied to the first device structure 100 and the second device structure 200 during the pre-bonding process. In other embodiments, no compressive force can be applied during the pre-bonding process.

[0104] Figure 15 is a vertical cross-sectional view of the vertically stacked semiconductor device 300 after an annealing process that bonds the first metal bonding structure 108 of the first bonding layer 110 to the second metal bonding structure 208 of the second bonding layer 210, in accordance with various embodiments of the present disclosure. Reference is made to Figure 15 The annealing process described above with reference to Figure 8 may be performed to form a plurality of metal bonds 113 that mechanically and electrically couple the first device structure 100 to the second device structure 200 to provide the vertically stacked semiconductor device 300. The shrinkage of the metal material of the first metal bonding structure 108 and the second metal bonding structure 208 can result in the presence of void regions 301 between the metal bonds 113 and the side surfaces of the first dielectric layer 127 and the second dielectric layer 227 that laterally surround the metal bonds 113, as shown in Figure 15 In some embodiments, the maximum width of the void regions 301 between the metal bonds 113 and the surrounding side surfaces of the first dielectric layer 127 and / or the second dielectric layer 227 can be at least about 100 nm. The void regions 301 can be located adjacent to the planar interface between the first dielectric layer 127 and the second dielectric layer 227. In embodiments in which the first dielectric layer 127 and the second dielectric layer 227 comprise a dielectric polymer material, the annealing process can also result in shrinkage of the first dielectric layer 127 and the second dielectric layer 227. This can be due to cross-linking of the functional groups of the dielectric polymer material during the high temperature annealing process, which can form a more compact structure of the first dielectric layer 127 and the second dielectric layer 227. Thus, in some embodiments, each void region 301 can be bounded by a first concave surface defined by the first dielectric layer 127 and the second dielectric layer 227 and a second concave surface defined by the corresponding metal bond 113, as shown in Figure 15

[0105] Figure 16 ​is a flowchart of a method 401 of fabricating a vertically-stacked semiconductor device 300 according to embodiments of the present disclosure. Reference is made to FIGS. 1-3 for elements of the method 401. Figure 2 , Figure 11 and Figure 16 In operation 402 of the method 401, a first dielectric layer 107, 127 can be formed over the first device structure 100. Reference is made to FIGS. 1-3 for elements of the method 401. Figure 3 , Figure 4 , Figure 12 and Figure 16 In operation 404 of the method 401, a plurality of openings can be formed through the first dielectric layer 107, 127. Reference is made to FIGS. 1-3 for elements of the method 401. Figure 5 , Figure 13 and Figure 16 In operation 406 of the method 401, a plurality of first metal bonding structures 108 can be formed within the openings through the first dielectric layer 107, 127 using an electroless deposition (ED) process. Reference is made to FIGS. 1-3 for elements of the method 401. Figure 7 , Figure 9A , Figure 10A , Figure 14 and Figure 16 In operation 408 of the method 401, the first device structure 100 can be brought into contact with the second device structure 200 such that the first dielectric layer 107, 127 contacts the second dielectric layer 207, 227 of the second device structure 200 and each first metal bonding structure 108 contacts a corresponding second metal bonding structure 208 of the second device structure 200. Reference is made to FIGS. 1-3 for elements of the method 401. Figure 8 , Figure 9B , Figure 10B , Figure 15 and Figure 16 In operation 410 of the method 401, an annealing process can be performed to form a plurality of metal bonds 113 between the first device structure 100 and the second device structure 200 and the metal bonds 113 have a void region 301 between each metal bond 113 and side surfaces of the first dielectric layer 107, 127 and the second dielectric layer 207, 227.

[0106] Referring to all drawings and in accordance with various embodiments of the present disclosure, a semiconductor device 300 includes a first device structure 100 including a first semiconductor substrate 101, a first device, a first interconnect structure, and first dielectric layers 107, 127, a second device structure 200 including a second semiconductor substrate 201, a second device, a second interconnect structure, and second dielectric layers 207, 227, wherein the first dielectric layers 107, 127 contact the second dielectric layers 207, 227, and metal joints 113 extending between the first device structure 100 and the second device structure 200, wherein a void region 301 is between each of the metal joints 113 and side surfaces of the first dielectric layers 107, 127 and the second dielectric layers 207, 227.

[0107] In one embodiment, a maximum lateral width w of each of the void regions 301 is 100 nm or more. In another embodiment, each of the void regions 301 is adjacent to a planar interface between the first dielectric layers 107, 127 and the second dielectric layers 207, 227. In another embodiment, each of the metal joints 113 extends between a first top metal pad 106 of the first interconnect structure and a second top metal pad 206 of the second interconnect structure. In another embodiment, a width of a portion of the first top metal pad 106 adjacent to an adjacent portion of the metal joint 113 is greater than a width of a portion of the second top metal pad 206 adjacent to the adjacent portion of the metal joint 113, and a horizontal surface of the second dielectric layers 207, 227 extending parallel to the planar interface between the first dielectric layers 107, 127 and the second dielectric layers 207, 227 is exposed in each of the void regions 301. In another embodiment, each of the metal joints extends at an oblique angle relative to the planar interface between the first dielectric layers 107, 127 and the second dielectric layers 207, 227 between the first top metal pad 106 of the first interconnect structure and the second top metal pad 206 of the second interconnect structure, and a horizontal surface of the first dielectric layers 107, 127 and the second dielectric layers 207, 227 extending parallel to the planar interface between the first dielectric layers 107, 127 and the second dielectric layers 207, 227 is exposed in each of the void regions 301. In another embodiment, the first dielectric layers 107, 127 and the second dielectric layers 207, 227 include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, and silicon oxynitride. In another embodiment, the first dielectric layers 107, 127 and the second dielectric layers 207, 227 include a dielectric polymeric material. In another embodiment, each of the void regions 301 is bounded by a first concave surface defined by the first dielectric layers 107, 127 and the second dielectric layers 207, 227 and a second concave surface defined by the metal joints 113. In another embodiment, each of the metal joints includes at least 1 at% of boron, phosphorus, and / or sulfur, including oxides thereof.

[0108] Another embodiment relates to a semiconductor device 300 comprising a first device structure 100 comprising a first semiconductor substrate 101, a first device, a first interconnect structure, and first dielectric layers 107, 127, a second device structure 200 comprising a second semiconductor substrate 201, a second device, a second interconnect structure, and second dielectric layers 207, 227, wherein the first dielectric layers 107, 127 contact the second dielectric layers 207, 227, and a plurality of metal joints 113 extending between the first device structure 100 and the second device structure 200, wherein each of the metal joints 113 comprises at least 1 at% of boron, phosphorous, and / or sulfur, including oxides thereof.

[0109] In one embodiment, the metal joints 113 further comprise at least one of copper, gold, silver, nickel, platinum, and palladium. In another embodiment, the metal joints 113 comprise a copper and gold alloy. Another embodiment relates to a method of manufacturing a vertically stacked semiconductor device 300, the method comprising forming first dielectric layers 107, 127 over a first device structure 100, forming a plurality of openings through the first dielectric layers 107, 127, forming a plurality of first metal joint structures 108 within the openings through the first dielectric layers 107, 127 using an electroless deposition process, contacting the first device structure 100 with a second device structure 100 such that the first dielectric layers 107, 127 contact second dielectric layers 207, 227 of the second device structure 200, and each of the first metal joint structures 108 contacts a corresponding second metal joint structure 208 of the second device structure 200, and performing an annealing process to promote interdiffusion between the first metal joint structures 108 and the corresponding second metal joint structures 208, and forming a plurality of metal joints 113 between the first device structure 100 and the second device structure 200, and the first device structure 100 and the second device structure 200 having a void region 301 between each of the metal joints 113 and side surfaces of the first dielectric layers 107, 127 and the second dielectric layers 207, 227. In one embodiment, the operation of forming a plurality of first metal joint structures 108 comprises forming the first metal joint structures 108 having convex upper surfaces extending 1 nm or more above a plane of an upper surface of the first dielectric layers 107, 127.

[0110] In another embodiment, a Young's modulus of the plurality of first metal joint structures 108 is at least 5% less than a Young's modulus of the metal joint 113 formed during the annealing process prior to the annealing process. In another embodiment, a maximum lateral width w of each of the void regions 301 is 100 nm or more. In another embodiment, each of the metal joints 113 includes at least 1 at% of boron, phosphorus, and / or sulfur, including oxides thereof. In another embodiment, the first dielectric layer 107, 127 includes a dielectric polymer material. In another embodiment, the operation of forming the plurality of openings through the first dielectric layer 107, 127 includes photo patterning the first dielectric layer 107, 127 by selectively exposing a plurality of regions of the dielectric polymer material to light radiation.

[0111] The foregoing summary of the disclosure is presented for the purpose of enabling those in the art to better understand the features of the many embodiments. Those skilled in the art will appreciate that other processes and structures can be readily devised or modified from the disclosure and that the same can achieve the same or similar results. Those skilled in the art will also appreciate that the many embodiments described herein with reference to the figures are illustrative in nature and that variations can be possible. Accordingly, the many embodiments disclosed herein are intended to be illustrative only and should not be construed in a limiting sense. The spirit and scope of the disclosure are to be determined by the appended claims.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a first device structure including a first semiconductor substrate, a plurality of first devices, a first interconnect structure, and a first dielectric layer; a second device structure including a second semiconductor substrate, a plurality of second devices, a second interconnect structure, and a second dielectric layer, wherein the first dielectric layer contacts the second dielectric layer; and a plurality of metal junctions extending between the first device structure and the second device structure, wherein a plurality of void regions are between each of the metal junctions and a plurality of side surfaces of the first dielectric layer and the second dielectric layer.

2. The semiconductor device according to claim 1, wherein Each of the void regions has a maximum lateral width of 100 nm or more.

3. The semiconductor device according to claim 1, wherein Each of the void regions is adjacent to a planar interface between the first dielectric layer and the second dielectric layer.

4. The semiconductor device according to claim 3, wherein Each of the metal junctions extends between a first top metal pad of the first interconnect structure and a second top metal pad of the second interconnect structure.

5. The semiconductor device according to claim 4, wherein A width of an adjacent portion of each of the metal junctions to the first top metal pad is greater than a width of an adjacent portion of each of the metal junctions to the second top metal pad, and a horizontal surface of the second dielectric layer extending parallel to the planar interface between the first dielectric layer and the second dielectric layer is exposed in each of the void regions.

6. The semiconductor device according to claim 4, wherein Each of the metal junctions extends between the first top metal pad of the first interconnect structure and the second top metal pad of the second interconnect structure at an oblique angle relative to the planar interface between the first dielectric layer and the second dielectric layer, and a plurality of horizontal surfaces of the first dielectric layer and the second dielectric layer extending parallel to the planar interface between the first dielectric layer and the second dielectric layer are exposed in each of the void regions.

7. The semiconductor device according to claim 1, wherein Each of the void regions is bounded by a first concave surface defined by the first dielectric layer and the second dielectric layer and a second concave surface defined by the metal junctions.

Images