Simple multi-input reset control signal circuit structure
By introducing a unidirectional level conversion circuit and multi-power supply PG output logic into the SOC reset circuit, the problem of SOC's inability to automatically reset is solved, enabling automatic reset of SOC under abnormal conditions and improving the reliability and stability of SOC.
Patent Information
- Application Number
- CN202423198044.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-24
AI Technical Summary
Existing SOC reset circuit designs have several issues, including the inability to automatically reset when the SOC is in the default running state, the existence of reverse logic in MCU control, the SOC power-on timing depending on MCU control, and the inability to automatically reset after a power supply failure.
A unidirectional level conversion circuit composed of transistors Q1 and Q2 and resistors R1, R2, R3, and R4 is connected between the GPIO pin of the MCU module and the REST pin of the SOC module to achieve unidirectional level conversion. Through the multi-channel power supply PG output and the logic of SOC REST control, the SOC is ensured to automatically reset in abnormal conditions.
This effectively avoids SOC reverse logic problems, ensures that the SOC automatically resets in case of power failure, prevents abnormal SOC startup, and improves the reliability and stability of the SOC.
Smart Images
Figure CN223729729U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to vehicle-mounted domain control related technical field especially, and relates to a simple and easy multiple input reset control signal circuit structure. BACKGROUND
[0002] With the requirement of vehicle-mounted domain control function safety, there are many deficiencies in the previous SOC end reset circuit design, and the circuit design such as Figure 4 As shown, such as: SOC reset design defaults to running state, MCU control exists reverse logic relationship, which will cause SOC to power up after SOC cannot automatically reset; SOC power-on sequence needs to depend on MCU control, needs to wait after SOC powers up to do reset again; SOC power supply abnormality restores normal, cannot automatically reset SOC etc. UTILITY MODEL CONTENTS
[0003] The main purpose of the utility model is to provide a simple and easy multiple input reset control signal circuit structure to solve the defects that the SOC reset design defaults to running state in the prior art, MCU control exists reverse logic relationship, which will cause SOC to power up after SOC cannot automatically reset; SOC power-on sequence needs to depend on MCU control, needs to wait after SOC powers up to do reset again; SOC power supply abnormality restores normal, cannot automatically reset SOC etc.
[0004] To achieve the above purpose, the utility model adopts the following technical scheme:
[0005] The utility model relates to a simple and easy multiple input reset control signal circuit structure, which comprises a unidirectional level conversion circuit composed of a triode Q1, a triode Q2 and resistors R1, R2, R3 and R4, and the unidirectional level conversion circuit is connected between the GPIO pin of the MCU module and the REST pin of the SOC module.
[0006] One end of the resistor R3 is connected to the E pole of the triode Q1, and the MCU power supply voltage of 3.3V is connected at the same time; the other end of the resistor R4 is connected to the GPIO pin of the MCU module.
[0007] One end of the resistor R2 is connected to the B pole of the triode Q2, and the other end of the resistor R2 is connected to the E pole of the triode Q2 and the ground at the same time; the C pole of the triode Q2 is connected to the REST pin of the SOC module.
[0008] The REST pin on the SOC module is connected with a resistor R5, the other end of the resistor R5 is connected with a 1.5V SOC power supply voltage, and the REST pin on the SOC module is provided with a resistor between the REST pin and a multipath power supply PG output end.
[0009] As a preferred technical scheme of the utility model, the REST pin on the SOC module is connected with a resistor R6 between the REST pin and a SOC_POWER1_PG, one end of the resistor R6 is connected with the REST pin on the SOC module, and the other end of the resistor R6 is connected with the SOC_POWER1_PG output end.
[0010] As a preferred technical scheme of the utility model, the REST pin on the SOC module is connected with a resistor R7 between the REST pin and a SOC_POWER2_PG, one end of the resistor R7 is connected with the REST pin on the SOC module, and the other end of the resistor R7 is connected with the SOC_POWER2_PG output end.
[0011] As a preferred technical scheme of the utility model, the REST pin on the SOC module is connected with a resistor R8 between the REST pin and a SOC_POWER3_PG, one end of the resistor R8 is connected with the REST pin on the SOC module, and the other end of the resistor R8 is connected with the SOC_POWER3_PG output end.
[0012] As a preferred technical scheme of the utility model, the REST pin on the SOC module is connected with a resistor Rm between the REST pin and a SOC_POWERx_PG, wherein n>3, one end of the resistor Rm is connected with the REST pin on the SOC module, and the other end of the resistor Rm is connected with the SOC_POWERx_PG output end, wherein m=n+5.
[0013] The utility model has the advantages of:
[0014] 1. The simple multi-input reset control signal circuit structure comprises a unidirectional level conversion circuit composed of triodes Q1 and Q2 and R1, R2, R3 and R4, the unidirectional level conversion circuit is connected between the GPIO pin of the MCU module and the REST pin on the SOC module, when the MCU GPIO is controlled to be low level, the SOC REST pin is low level, and the problem of reverse logic is effectively avoided.
[0015] 2、The simple multiple input reset control signal circuit structure is in SOC REST control with the multiple power supply PG output and logic, that is, one output is low level, and the SOC REST state is low level, since the power supply PG output is OD output (open drain output mode), when the power supply output is normal, the high level state is determined by the external pull-up resistor R5, when the power supply output is abnormal, the PG output is in low level state, and the SOC reset timing needs to wait for the power supply state to be normal, and then the reset is pulled high, so that the SOC abnormal start problem due to abnormal power supply of a certain power supply is avoided, and when the SOC runs, the SOC is automatically reset when a certain power supply is abnormal, so that the SOC is in an abnormal state. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to the structures shown in the drawings without creative labor for those skilled in the art.
[0017] Figure 1 is a structural schematic diagram of a simple multiple input reset control signal circuit structure of the present application;
[0018] Figure 2 is a point distribution diagram of a simple multiple input reset control signal circuit structure of the present application;
[0019] Figure 3 is a SOC power-on flow chart of a simple multiple input reset control signal circuit structure of the present application;
[0020] Figure 4 is a traditional SOC end reset circuit diagram.
[0021] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present application.
[0023] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.
[0024] Example 1
[0025] like Figures 1 to 3 As shown, this utility model discloses a simple multi-input reset control signal circuit structure, including a unidirectional level conversion circuit composed of transistors Q1 and Q2 and resistors R1, R2, R3, and R4. The unidirectional level conversion circuit is connected between the GPIO pin of the MCU module and the REST pin of the SOC module. When the MCU GPIO control is low, the SOC REST pin is low, effectively avoiding the problem of reverse logic.
[0026] The base (B) of transistor Q1 is connected to one end of resistor R4 and one end of resistor R3. Resistor R3 is connected to the emitter (E) of transistor Q1 and is also connected to the 3.3V MCU power supply voltage. The other end of resistor R4 is connected to the GPIO pin of the MCU module.
[0027] The collector (C) of transistor Q1 is connected to one end of resistor R1. The other end of resistor R1 is connected to both the base (B) of transistor Q2 and one end of resistor R2. The other end of resistor R2 is connected to the emitter (E) of transistor Q2 and is also grounded. The collector (C) of transistor Q2 is connected to the REST pin on the SOC module.
[0028] The REST pin on the SOC module is connected with a resistor R5, the other end of the resistor R5 is connected with a 1.5V SOC power supply voltage, and the REST pin on the SOC module and the multi-path power supply PG output end are both provided with resistors. In the simple multi-input reset control signal circuit structure, the SOC REST control is ANDed with the multi-path power supply PG output, that is, there is one output at a low level, and the SOC REST state is at a low level. Since the power supply PG output is an OD output (open drain output mode), when the power supply output is normal, the high level state is determined by the external pull-up resistor R5, and when the power supply output is abnormal, the PG output is at a low level state. The SOC reset timing needs to wait for the power supply state to be normal, and the reset will be pulled high, avoiding the problem of SOC abnormal start due to abnormal power supply. In the SOC operation, when a power supply is abnormal, the SOC will be automatically reset, avoiding the SOC in an abnormal state.
[0029] The REST pin on the SOC module is connected with a resistor R6, one end of the resistor R6 is connected with the REST pin on the SOC module, and the other end of the resistor R6 is connected with the SOC_POWER1_PG output end.
[0030] Among them, the REST pin on the SOC module is connected with a resistor R7 between the SOC_POWER2_PG, one end of the resistor R7 is connected with the REST pin on the SOC module, and the other end of the resistor R7 is connected with the SOC_POWER2_PG output end.
[0031] Among them, the REST pin on the SOC module is connected with a resistor R8 between the SOC_POWER3_PG, one end of the resistor R8 is connected with the REST pin on the SOC module, and the other end of the resistor R8 is connected with the SOC_POWER3_PG output end.
[0032] The REST pin on the SOC module is connected with a resistor Rm between the SOC_POWERx_PG, one end of the resistor Rm is connected with the REST pin on the SOC module, and the other end of the resistor Rm is connected with the SOC_POWERx_PG output end, where m=n+5.
[0033] Among them, as Figure 2As shown, a plurality of points are selected, point 1 is the power supply reference of MCU, point 2 is the result of voltage division through resistors R3 and R4, when point 5 is high level, Q1 is in the closed state, thereby causing point 3 and point 4 to be in low level state, Q2 is also in the closed state, point 6 is the same as point 5 due to point 7 being the power supply reference of SOC, so when point 8, point 9, point 10, point 11 are not low level, point 6 level and point 5 level state remain the same, that is, high level, otherwise, when point 5 is low level, point 6 level is low level, when any one of point 8, point 9, point 10, point 11 is low level, the level state of point 6 is low level state, the function of point 5 is: MCU controls SOC reset, mainly reset action when SOC is abnormal. Figure 3 is the power-on process of SOC.
[0034] The functions of points 8, 9 and 10 are: SOC power supply system resets SOC, mainly state synchronization; the function of point 11 is: used for expanding multiple power supply systems, the utility model only adopts three power supply system schemes, if multiple power supply systems are needed, the design scheme can be referred to.
[0035] In addition, if "and / or" or "and / or" appears in the whole text, its meaning includes three parallel schemes, for example, "A and / or B" includes A scheme, or B scheme, or A and B scheme. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled personnel in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor is it within the protection scope required by the utility model.
Claims
1. A simple multiple input reset control signal circuit structure, characterized by: A unidirectional level conversion circuit composed of triodes Q1, Q2 and resistors R1, R2, R3 and R4 is connected between the GPIO pin of the MCU module and the REST pin of the SOC module; The B electrode of the triode Q1 is connected with one end of the resistor R4 and one end of the resistor R3, the resistor R3 is connected with the E electrode of the triode Q1, and the 3.3V MCU supply voltage is connected at the same time; the other end of the resistor R4 is connected with the GPIO pin of the MCU module; The C electrode of the triode Q1 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the B electrode of the triode Q2 and one end of the resistor R2 at the same time, the other end of the resistor R2 is connected with the E electrode of the triode Q2 and connected with the ground at the same time; the C electrode of the triode Q2 is connected with the REST pin of the SOC module; The REST pin of the SOC module is connected with the resistor R5, the other end of the resistor R5 is connected with the 1.5V SOC supply voltage, and the REST pin of the SOC module and the multi-power PG output end are both provided with resistors.
2. The simple multiple input reset control signal circuit structure according to claim 1, wherein, The REST pin of the SOC module and the SOC_POWER1_PG are connected with the resistor R6, one end of the resistor R6 is connected with the REST pin of the SOC module, and the other end of the resistor R6 is connected with the SOC_POWER1_PG output end.
3. The simple multiple input reset control signal circuit structure according to claim 1, wherein, The REST pin of the SOC module and the SOC_POWER2_PG are connected with the resistor R7, one end of the resistor R7 is connected with the REST pin of the SOC module, and the other end of the resistor R7 is connected with the SOC_POWER2_PG output end.
4. The simple multiple input reset control signal circuit structure according to claim 1, wherein, The REST pin of the SOC module and the SOC_POWER3_PG are connected with the resistor R8, one end of the resistor R8 is connected with the REST pin of the SOC module, and the other end of the resistor R8 is connected with the SOC_POWER3_PG output end.
5. The simple multiple input reset control signal circuit structure according to claim 1, wherein, The REST pin of the SOC module and the SOC_POWERx_PG are connected with the resistor Rm, where x>3; one end of the resistor Rm is connected with the REST pin of the SOC module, and the other end of the resistor Rm is connected with the SOC_POWERx_PG output end, where m=x+5.