FPGA unit pin level switching circuit

Abstract

The utility model discloses an FPGA (Field Programmable Gate Array) unit pin level switching circuit, which comprises an FPGA unit and a level switching circuit, and the FPGA unit comprises a first bank area and a plurality of other bank areas. After the FPGA is powered on and works normally, according to a target level value IOVCC1 of external equipment connected with the FPGA, a PWM control signal with a corresponding duty ratio is generated in the FPGA through a logic control unit of the FPGA, the PWM control signal is output to a level conversion circuit through a certain IO pin of a first bank area of the FPGA, the level conversion circuit is controlled to output voltage with the level size being IOVCC1, and the voltage is output through a second bank area of the FPGA. The level conversion circuit is used as the power supply voltage of the Bank area connected with the output end of the level conversion circuit, so that the level of all IO pins in the Bank8 area is IOVCC1, and the function that the IO pin voltage of the Bank required for controlling the single IO pin of the FPGA is dynamically adjustable is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to digital communication technical field, concretely relates to a FPGA unit pin level switching circuit. BACKGROUND

[0002] IO pin is the interface part of chip and external circuit, in order to facilitate management and adapt to various electrical standards, the IO pin of FPGA is divided into several groups (bank), and the interface level of each bank is determined by the supply voltage VCCIO pin connected by its power supply pin, and a bank can only have one VCCIO pin, and only the ports of the same level can be connected together.

[0003] In order to meet the demand that a FPGA chip or even a certain bank interface on FPGA can communicate with external circuits of different level marks, the existing method carries out level conversion on the IO pin of FPGA through the level conversion chip outside the circuit, so that the IO pin reaches a specific level standard, but there are the following shortcomings: a level conversion chip is used for the conversion level of each FPGA, if multiple IO pins need to be converted, multiple level conversion chips need to be used, which increases the cost of the scheme. At the same time, in order to change the pin level of a FPGA and control the input and output direction of IO, an additional IO is needed to control the level conversion chip to determine, and the IO resource of FPGA is additionally consumed. In addition, the hardware circuit of level conversion is fixed, so the optional level of level conversion is less, and it can only be switched between two or three levels, such as 1.8V, 2.5V and 3.3V, and the use is limited. UTILITARIAN CONTENT

[0004] In order to overcome the above-mentioned shortcomings, the purpose of the utility model is to provide a FPGA unit pin level switching circuit to solve the problem of scheme cost caused by the level conversion of multiple IO pins of FPGA through multiple level conversion chips outside the circuit in the background art.

[0005] In order to achieve the above purpose, the utility model adopts the technical scheme of a FPGA unit pin level switching circuit, the FPGA unit is connected with external equipment, and the external equipment includes target level value. The FPGA unit pin level switching circuit includes a level conversion circuit, wherein:

[0006] The FPGA unit includes a first bank region and a plurality of other bank regions, any IO pin in the first bank region is electrically connected with an input end of the level conversion circuit, for generating a PWM control signal with a duty cycle corresponding to the target level value in the FPGA through a logic control unit thereof, and outputting to the level conversion circuit.

[0007] The utility model provides a kind of FPGA unit pin level switching circuit, including FPGA unit and level conversion circuit, the FPGA unit includes first bank region and a plurality of other bank regions.FPGA is normally operated after power-on, according to the target level value IOVCC1 of the external equipment connected with FPGA, the PWM control signal of corresponding duty cycle is generated in FPGA through its logic control unit, and the voltage of the level conversion circuit is output to the level conversion circuit by the IO pin of the first bank region of FPGA, the voltage of IOVCC1 is output as the power voltage of bank region connected with the output end of level conversion circuit, so that the level of all IO pins in this Bank8 region is IOVCC1, so that the function of IO pin voltage dynamically adjustable of required bank by FPGA single IO pin is realized.

[0008] Preferably, the level conversion circuit includes an RC low-pass filter, the input end of the RC low-pass filter is connected with the first bank region, for smoothing the PWM control signal and converting into an equivalent voltage signal.

[0009] Preferably, the level conversion circuit further includes an operational amplifier U5 and a linear voltage regulator U14, the input end of the operational amplifier U5 is connected with the output end of the RC low-pass filter, the input end of the linear voltage regulator U14 is connected with the output end of the operational amplifier U5, for converting and stably outputting the voltage signal as the target level value through the operational amplifier U5 and the linear voltage regulator U14.

[0010] Preferably, the model of the linear voltage regulator U14 is SGM2053-ADJ.

[0011] Preferably, the model of the operational amplifier U5 is SGM8541XN5 / TR.

[0012] Preferably, the range of the level value of the bank region connected with the FPGA unit and outputted from the output end of the level conversion circuit is 0V-3.3V.

[0013] The FPGA unit pin level switching circuit provided by the application has the following advantages compared with the prior art.

[0014] 1. The design is simple, flexible and convenient to use, the FPGA itself is used as a control chip for dynamic switching of the level, no other control chip is needed, and no manual switching is needed to obtain different Bank power supply voltages, and all are automatically and dynamically switched by software.

[0015] 2. No other control chip and voltage conversion chip is needed, which shortens the development cycle and saves the development cost.

[0016] 3. The FPGA only needs to use one IO pin as a control signal to dynamically adjust the IO pin level of other Banks, which greatly saves the IO pin resources of the FPGA.

[0017] 4. The dynamic switching has more selectable level options, wider application range and more flexible design. The IO pin level of the FPGA supports 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.3V and other level standards, and the PWM control signal generated by the FPGA program can switch the IO pin of the FPGA to any voltage between 0V and 3.3V. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural block diagram of an embodiment of the FPGA unit pin level switching circuit of the utility model;

[0019] Figure 2 is a schematic diagram of the first bank area (Bank1) in the FPGA unit of an embodiment of the FPGA unit pin level switching circuit of the utility model;

[0020] Figure 3 is a circuit diagram of the level conversion circuit of an embodiment of the FPGA unit pin level switching circuit of the utility model;

[0021] Figure 4 is a schematic diagram of the eighth bank area (Bank8) in the FPGA unit of an embodiment of the FPGA unit pin level switching circuit of the utility model. DETAILED DESCRIPTION

[0022] The preferred embodiments of the utility model will be described in detail below with reference to the drawings, so that the advantages and features of the utility model can be more easily understood by those skilled in the art, and the protection scope of the utility model can be more clearly and explicitly defined.

[0023] Reference Figure 1 and Figure 2 ,Figure 1 A structural schematic diagram of the FPGA unit pin level switching circuit is shown. Figure 2 A perspective view of the FPGA unit pin level switching circuit is shown.

[0024] As shown in Figures 1 to 4 , a FPGA unit pin level switching circuit, the FPGA unit is connected with an external device, and the external device includes a target level value. The FPGA unit pin level switching circuit includes a level conversion circuit, wherein:

[0025] The FPGA unit includes a first bank region and a plurality of other bank regions, any IO pin in the first bank region is electrically connected with an input end of the level conversion circuit, for generating a PWM control signal with a duty cycle corresponding to the target level value in the FPGA through a logic control unit thereof, and outputting to the level conversion circuit. The output end of the level conversion circuit is connected with any one of the plurality of other bank regions, for converting the PWM control signal into the target level value, and outputting to the bank region connected with the output end of the level conversion circuit.

[0026] The FPGA unit pin level switching circuit provided by the present application includes a FPGA unit and a level conversion circuit, the FPGA unit includes a first bank region and a plurality of other bank regions, i.e. Bank1, Bank2, …, BankN-1, BankN. For the convenience of subsequent description, Bank8 is set to be connected with the output end of the level conversion circuit. After the FPGA normally works, according to the target level value IOVCC1 of the external device connected with the FPGA, a PWM control signal with a corresponding duty cycle is generated in the FPGA through a logic control unit thereof, the PWM control signal is output to the level conversion circuit through a certain IO pin of Bank1 of the FPGA, the level conversion circuit is controlled to output a voltage with a level size of IOVCC1 as a power supply voltage of Bank8, so that the level size of all IO pins on Bank8 is IOVCC1, thereby realizing the function of dynamically adjustable IO pin voltage of the required bank controlled by a single IO pin of the FPGA.

[0027] In some embodiments, referring to Figure 1 and Figure 2 , the range of the level value output from the output end of the level conversion circuit to the bank region connected with the FPGA unit is 0V-3.3V.

[0028] Exemplarily, referring to Figure 2The GPIO pin named H7_PWM1_3V3 on Bank1 is connected with the level conversion circuit, and the FPGA controls H7_PWM1_3V3 to generate a corresponding PWM control signal through logic programming. The PWM signal controls the level conversion circuit to output a voltage at a required level. The supply voltage VDDIO pin_1 of the Bank is 3.3V, so the level of H7_PWM1_3V3 is 3.3V, and the level of the PWM control signal is 0V to 3.3V. Referring to the figure, when the supply voltage of the Bank needs to be dynamically adjustable, the power supply pins VDDIO pin_8_1 to 3 of the Bank are connected with the output voltage IOVCC1 of the level conversion circuit, so that the voltage of all IO pins on the Bank is IOVCC1.

[0029] In some embodiments, referring to Figure 1 and Figure 2 The level conversion circuit includes an RC low-pass filter. The input end of the RC low-pass filter is connected with the first bank area, for smoothing the PWM control signal and converting it into an equivalent voltage signal. The level conversion circuit further includes an operational amplifier U5 and a linear voltage regulator U14. The input end of the operational amplifier U5 is connected with the output end of the RC low-pass filter, and the input end of the linear voltage regulator U14 is connected with the output end of the operational amplifier U5, for converting and stabilizing the voltage signal output to a target level value through the operational amplifier U5 and the linear voltage regulator U14.

[0030] Exemplarily, the level conversion circuit outputs a voltage IOVCC1 at a required level according to the level of the PWM control signal, as the supply voltage of the Bank8 with dynamically adjustable supply voltage in the FPGA.

[0031] In some embodiments, the model of the linear voltage regulator U14 is SGM2053-ADJ. The model of the operational amplifier U5 is SGM8541XN5 / TR.

[0032] SGM2053-ADJ is a low-power, low-noise, fast transient response and low-dropout linear voltage regulator designed with CMOS technology. It can provide an output current of up to 500mA. The working input voltage range of the regulator is 1.5V to 5.5V, and the adjustable output voltage range is between 0.8V and 5.0V.

[0033] SGM8541XN5 / TR is a low-cost voltage feedback amplifier that supports single power supply operation at 2.1V to 5.5V, and each amplifier only consumes 46μA of static current, and has rail-to-rail input capability, wide input common-mode voltage range and rail-to-rail output voltage swing.

[0034] The FPGA unit pin level switching circuit provided in the application has the following specific working process:

[0035] After the FPGA normally works, the supply voltage of the Bank 8 is 0V, and the IO pin level of all IO pins on the Bank is 0V. The FPGA calculates the duty cycle of the PWM control signal according to the IOVCC1 level standard of the connected external device circuit, generates the PWM control signal with the corresponding duty cycle through the logic code, the PWI signal controls the level conversion circuit to output the voltage of IOVCC1, IOVCC1 is input to the power supply pin of the Bank 8, and the IO pin level of all IO pins of the Bank 8 is IOVCC1. The PWM control signal output by the FPGA dynamically changes the Bank supply voltage, thereby realizing dynamic adjustment of the IO pin level on the corresponding Bank.

[0036] The above embodiments are only for illustrating the technical concept and characteristics of the application, and the purpose is to enable those skilled in the art to understand the content of the application and implement it, and cannot limit the protection scope of the application. Any equivalent changes or modifications made according to the spirit and essence of the application shall be covered within the protection scope of the application.

Claims

1. An FPGA cell pin level switching circuit, the FPGA cell being connected with an external device, the external device including a target level value; characterized in that, The FPGA unit pin level switching circuit comprises a level conversion circuit, wherein: The FPGA unit comprises a first bank region and a plurality of other bank regions, any IO pin in the first bank region is electrically connected with an input end of the level conversion circuit, a PWM control signal with a duty cycle corresponding to the target level value is generated in the FPGA through a logic control unit thereof and is output to the level conversion circuit; an output end of the level conversion circuit is connected with any one of the plurality of other bank regions, for converting the PWM control signal into the target level value and outputting to the bank region connected with the output end of the level conversion circuit.

2. The FPGA cell pin level shifter circuit of claim 1, wherein, The level conversion circuit comprises an RC low-pass filter, an input end of the RC low-pass filter is connected with the first bank region, for smoothing the PWM control signal and converting into an equivalent voltage signal.

3. The FPGA cell pin level shifter circuit of claim 2, wherein, The level conversion circuit further comprises an operational amplifier U5 and a linear voltage regulator U14, an input end of the operational amplifier U5 is connected with an output end of the RC low-pass filter, an input end of the linear voltage regulator U14 is connected with an output end of the operational amplifier U5, for converting and stably outputting the voltage signal into the target level value through the operational amplifier U5 and the linear voltage regulator U14.

4. The FPGA cell pin level shifter circuit of claim 3, wherein, The model of the linear voltage regulator U14 is SGM2053-ADJ.

5. The FPGA cell pin level shifter circuit of claim 3, wherein, The model of the operational amplifier U5 is SGM8541XN5 / TR.

6. The FPGA cell pin level shifter circuit of claim 1, wherein, The output end of the level conversion circuit outputs to the bank region connected with the FPGA unit, and the range of the level value of the bank region is 0V-3.3V.

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