Latch for solving output failure
By introducing two latch components and logic gates with different failure input signals, a switching component was designed to automatically switch the latch components, which solved the problem of unstable output of the latch under specific input conditions and achieved the stability of the latch output.
Patent Information
- Application Number
- CN202520029848.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2035-01-07
AI Technical Summary
Existing latches have the problem of output failure under certain input conditions, especially when both inputs are 0 or both are 1, the output is unstable and may oscillate between the two states.
Two latch components (a first latch component and a second latch component) with different failure input signals are used. Through the design of logic gate circuits and switching components, the latch component automatically switches to the other latch component when one latch component fails, thus ensuring the stability of the latch output.
This achieves stability of the latch output under different input conditions, avoids output uncertainty and oscillation, and solves the problem of latch output failure.
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Figure CN223729741U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the latch field, especially a latch that solves output failure. BACKGROUND
[0002] Latch is a kind of pulse level sensitive storage unit circuit, they can change state under the action of specific input pulse level.Latch is to store signal to maintain certain level state.The most important function of latch is cache, secondly, it is to solve the different synchronization problems of high-speed controller and slow peripheral equipment, thirdly, it is to solve the driving problem, finally, it is to solve the problem that an I / O port can both output and input.
[0003] In prior art, latch has the problem of output failure.For example, according to the truth table of low level effective input latch, when two inputs are both 0, output invalid condition appears, in this case, the output of flip-flop is unstable, and may oscillate between 2 states.Similarly, when two inputs of high level effective input latch are both 1, output invalid condition also appears.
[0004] Therefore, it is necessary to provide a latch that solves output failure, to solve the output failure of latch. SUMMARY
[0005] The utility model provides a latch that solves output failure, including first input, second input, first latch component, second latch component, logic gate circuit, switch component and latch output, wherein, first input and second input are electrically connected with two input terminals of first latch component respectively, first input and second input are electrically connected with two input terminals of second latch component respectively, the output of first latch component and second latch component is electrically connected with the input of logic gate circuit, switch component is electrically connected with the output of first latch component, second latch component and logic gate circuit, latch output is electrically connected with switch component, switch component is used to according to the input signal of first input and second input, the output of latch output and first latch component, second latch component in the output effective latch component of switch component, the invalid input signal corresponding to first latch component and the invalid input signal corresponding to second latch component are different.
[0006] Further, the first latch component is composed of NOR gate, and the second latch component is composed of NAND gate.
[0007] Further, the switch component is configured to connect the latch output and the second latch component when both the first input and the second input are low, and the switch component is configured to connect the latch output and the first latch component when at least one of the first input and the second input is high.
[0008] Further, the logic gate circuit includes a first logic gate sub-circuit and a second logic gate sub-circuit, wherein an input of the first logic gate sub-circuit is electrically connected to an output of the first latch component, and an input of the second logic gate sub-circuit is electrically connected to an output of the second latch component.
[0009] Further, the first latch component includes a first NOR gate and a second NOR gate, wherein the first input is electrically connected to one input of the first NOR gate and one input of the second NOR gate, another input of the first NOR gate is electrically connected to an output of the second NOR gate, and another input of the second NOR gate is electrically connected to an output of the first NOR gate.
[0010] Further, the second latch component includes a first NAND gate and a second NAND gate, wherein the first input is electrically connected to one input of the first NAND gate and one input of the second NAND gate, another input of the first NAND gate is electrically connected to an output of the second NAND gate, and another input of the second NAND gate is electrically connected to an output of the first NAND gate.
[0011] Further, the first logic gate sub-circuit and the second logic gate sub-circuit have the same structure.
[0012] Further, the first logic gate sub-circuit includes a first XOR gate and a first inverter, wherein one input of the first XOR gate is electrically connected to an output of the first NOR gate, another input of the first XOR gate is electrically connected to an output of the second NOR gate, and an output of the first XOR gate is electrically connected to an input of the first inverter.
[0013] Further, the second logic gate sub-circuit includes a second XOR gate and a second inverter, wherein one input of the second XOR gate is electrically connected to an output of the first NAND gate, another input of the second XOR gate is electrically connected to an output of the second NAND gate, and an output of the second XOR gate is electrically connected to an input of the second inverter.
[0014] Further, the switch assembly comprises a first switch, a second switch and a third switch, wherein the first switch and the third switch are connected in series between the first latch assembly and the latch output, the second switch is connected in series between the second latch assembly and the latch output, a first control end of the first switch is electrically connected with the output end of the first XOR gate, a second control end of the first switch is electrically connected with the output end of the first inverter, a first control end of the second switch is electrically connected with the output end of the second XOR gate, a second control end of the second switch is electrically connected with the output end of the second inverter, a second control end of the third switch is electrically connected with the output end of the second XOR gate, and a first control end of the third switch is electrically connected with the output end of the second inverter.
[0015] Compared with the prior art, the latch provided by the utility model has at least the following beneficial effects:
[0016] By introducing two latch assemblies (a first latch assembly and a second latch assembly) with different failure input signals, the latch can automatically switch to another latch assembly when one latch assembly fails, thereby solving the technical problem of latch output failure. BRIEF DESCRIPTION OF DRAWINGS
[0017] The present specification will be further illustrated in the form of exemplary embodiments, which will be described in detail with reference to the drawings. These embodiments are not restrictive, and in these embodiments, the same numbers represent the same structures, wherein:
[0018] Figure 1 is a module schematic view of a latch for solving output failure according to some embodiments of the present specification;
[0019] Figure 2 is a circuit structure schematic view of a latch for solving output failure according to some embodiments of the present specification. DETAILED DESCRIPTION
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings needed to be used in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some examples or embodiments of the present specification, and for those skilled in the art, the present specification can also be applied to other similar scenarios without creative labor. Unless it is obvious from the language environment or otherwise stated, the same numbers in the drawings represent the same structures or operations.
[0021] Figure 1 is a module schematic view of a latch for solving output failure according to some embodiments of the present specification, as Figure 1As shown in the first aspect, a latch for solving output failure can include a first input, a second input, a first latch component, a second latch component, a logic gate circuit, a switch component, and a latch output, wherein the first input and the second input are electrically connected to two inputs of the first latch component, the first input and the second input are electrically connected to two inputs of the second latch component, outputs of the first latch component and the second latch component are electrically connected to an input of the logic gate circuit, the switch component is electrically connected to outputs of the first latch component, the second latch component, and the logic gate circuit, the latch output is electrically connected to the switch component, the switch component is configured to connect the latch output and an output effective latch component between the first latch component and the second latch component according to input signals of the first input and the second input, and the failure input signal corresponding to the first latch component and the failure input signal corresponding to the second latch component are different. For example, when both inputs are 0, output failure occurs.
[0022] Specifically, by setting the logic gate circuit and the switch component, the latch output and the output effective latch component between the first latch component and the second latch component can be connected, and effective output of the latch can be realized, thereby solving the problem of output failure of the existing latch.
[0023] Figure 2 As shown in the first aspect, a latch for solving output failure can include a first input, a second input, a first latch component, a second latch component, a logic gate circuit, a switch component, and a latch output, wherein the first input and the second input are electrically connected to two inputs of the first latch component, the first input and the second input are electrically connected to two inputs of the second latch component, outputs of the first latch component and the second latch component are electrically connected to an input of the logic gate circuit, the switch component is electrically connected to outputs of the first latch component, the second latch component, and the logic gate circuit, the latch output is electrically connected to the switch component, the switch component is configured to connect the latch output and an output effective latch component between the first latch component and the second latch component according to input signals of the first input and the second input, and the failure input signal corresponding to the first latch component and the failure input signal corresponding to the second latch component are different. For example, when both inputs are 0, output failure occurs. Figure 2 As shown in the first aspect, a latch for solving output failure can include a first input, a second input, a first latch component, a second latch component, a logic gate circuit, a switch component, and a latch output, wherein the first input and the second input are electrically connected to two inputs of the first latch component, the first input and the second input are electrically connected to two inputs of the second latch component, outputs of the first latch component and the second latch component are electrically connected to an input of the logic gate circuit, the switch component is electrically connected to outputs of the first latch component, the second latch component, and the logic gate circuit, the latch output is electrically connected to the switch component, the switch component is configured to connect the latch output and an output effective latch component between the first latch component and the second latch component according to input signals of the first input and the second input, and the failure input signal corresponding to the first latch component and the failure input signal corresponding to the second latch component are different. For example, when both inputs are 0, output failure occurs.
[0024] Specifically, when the first input IN1 and the second input IN2 are both low, the first latch component remains the current state unchanged, i.e., the latch function. When the first input IN1 and the second input IN2 are both high, the state of the first latch component is uncertain, i.e., output failure.
[0025] The second latch component works in a similar way as the first latch component, but the trigger condition is opposite. When the first input IN1 and the second input IN2 of the second latch component are both high, the second latch component keeps the current state unchanged. When the first input IN1 and the second input IN2 are both low, the state of the second latch component is also uncertain, i.e. the output is invalid.
[0026] In some embodiments, a switch component is used to connect the latch output and the second latch component when the first input IN1 and the second input IN2 are both low, and the switch component is also used to connect the latch output and the first latch component when at least one of the first input IN1 and the second input IN2 is high.
[0027] As shown in Figure 2 , the logic gate circuit comprises a first logic gate sub-circuit and a second logic gate sub-circuit, wherein the input of the first logic gate sub-circuit is electrically connected with the output of the first latch component, and the input of the second logic gate sub-circuit is electrically connected with the output of the second latch component.
[0028] As shown in Figure 2 , the first logic gate sub-circuit and the second logic gate sub-circuit have the same structure. The first logic gate sub-circuit comprises a first exclusive OR gate X1 and a first inverter, wherein one input of the first exclusive OR gate X1 is electrically connected with the output of the first NOR gate, the other input of the first exclusive OR gate X1 is electrically connected with the output of the second NOR gate, and the output of the first exclusive OR gate is electrically connected with the input of the first inverter. The second logic gate sub-circuit comprises a second exclusive OR gate X2 and a second inverter, wherein one input of the second exclusive OR gate X2 is electrically connected with the output of the first NAND gate, the other input of the second exclusive OR gate X2 is electrically connected with the output of the second NAND gate, and the output of the second exclusive OR gate X2 is electrically connected with the input of the second inverter.
[0029] As shown in Figure 2As shown, the switch assembly includes a first switch S1, a second switch S2 and a third switch S3, wherein the first switch S1 and the third switch S3 are connected in series between the first latch assembly and the latch output OUT, the second switch S2 is connected in series between the second latch assembly and the latch output, the first control end G of the first switch S1 is electrically connected with the output end of the first exclusive-OR gate X1, the second control end GB of the first switch S1 is electrically connected with the output end of the first inverter, the first control end G of the second switch S2 is electrically connected with the output end of the second exclusive-OR gate X2, the second control end GB of the second switch S2 is electrically connected with the output end of the second inverter, the second control end GB of the third switch S3 is electrically connected with the output end of the second exclusive-OR gate X2, and the first control end G of the third switch S3 is electrically connected with the output end of the second inverter. When the first control end G of the switch is 1, the switch is closed, and when the first control end G of the switch is 0, the switch is opened. The second control end GB and the first control end G of the switch are inverse signals of each other, that is, when the first control end G of the switch is 0, the second control end GB of the switch is 1.
[0030] Specifically, Figure 2 As shown, the working process of the latch with output failure solution is as follows: when the inputs of the first input end IN1 and the second input end IN2 are 11 or 01 or 10, the output of the second latch assembly is valid, and the two outputs are different, so that the output of the first exclusive-OR gate X1 is 1, the second switch S2 is closed, the third switch S3 is opened, and the latch output OUT outputs the output of the second latch assembly; when the inputs of the first input end IN1 and the second input end IN2 are 00, the state of the second latch assembly is uncertain, that is, the output is invalid, the second switch S2 is opened, and the third switch S3 is closed, so that the output of the first latch assembly maintains the previous state, the first switch S1 is closed, and the latch output OUT outputs the output of the first latch assembly.
[0031] Finally, it should be understood that the embodiments described in the specification are only used to illustrate the principles of the embodiments of the specification. Other variations can also belong to the scope of the specification. Therefore, as an example but not limitation, alternative configurations of the embodiments of the specification can be considered consistent with the teachings of the specification. Accordingly, the embodiments of the specification are not limited to the embodiments explicitly introduced and described in the specification.
Claims
1. A latch to resolve an output failure, the latch comprising: The application relates to a latch circuit, which comprises a first input end, a second input end, a first latch component, a second latch component, a logic gate circuit, a switch component and a latch output end, wherein the first input end and the second input end are electrically connected with two input ends of the first latch component respectively, the first input end and the second input end are electrically connected with two input ends of the second latch component respectively, the output ends of the first latch component and the second latch component are electrically connected with input ends of the logic gate circuit, the switch component is electrically connected with the output ends of the first latch component, the second latch component and the logic gate circuit, the switch component is electrically connected with the latch output end, the switch component is used for connecting the latch output end with the output effective latch component among the first latch component and the second latch component according to input signals of the first input end and the second input end, and the invalid input signal corresponding to the first latch component is different from the invalid input signal corresponding to the second latch component.
2. The latch circuit of claim 1, wherein, The first latch component is composed of an OR NOT gate, and the second latch component is composed of an AND NOT gate.
3. The latch circuit of claim 2, wherein, The switch component is used for connecting the latch output end with the second latch component when low levels are input in the first input end and the second input end, and the switch component is also used for connecting the latch output end with the first latch component when high levels are input in at least one of the first input end and the second input end.
4. The latch circuit of claim 3, wherein, The logic gate circuit comprises a first logic gate sub-circuit and a second logic gate sub-circuit, wherein the input end of the first logic gate sub-circuit is electrically connected with the output end of the first latch component, and the input end of the second logic gate sub-circuit is electrically connected with the output end of the second latch component.
5. The latch circuit of claim 4, wherein, The first latch component comprises a first OR NOT gate and a second OR NOT gate, one input end of the first OR NOT gate and one input end of the second OR NOT gate are electrically connected with the first input end, the other input end of the first OR NOT gate is electrically connected with the output end of the second OR NOT gate, and the other input end of the second OR NOT gate is electrically connected with the output end of the first OR NOT gate.
6. The latch circuit of claim 5, wherein, The second latch component comprises a first AND NOT gate and a second AND NOT gate, one input end of the first AND NOT gate and one input end of the second AND NOT gate are electrically connected with the first input end, the other input end of the first AND NOT gate is electrically connected with the output end of the second AND NOT gate, and the other input end of the second AND NOT gate is electrically connected with the output end of the first AND NOT gate.
7. The latch circuit of claim 6, wherein, The first logic gate sub-circuit and the second logic gate sub-circuit are consistent in structure.
8. The latch circuit of claim 7, wherein, The first logic gate sub-circuit comprises a first exclusive OR gate and a first inverter, one input end of the first exclusive OR gate is electrically connected with the output end of the first OR NOT gate, the other input end of the first exclusive OR gate is electrically connected with the output end of the second OR NOT gate, and the output end of the first exclusive OR gate is electrically connected with the input end of the first inverter.
9. The latch circuit of claim 8, wherein, The second logic gate sub-circuit comprises a second exclusive OR gate and a second inverter, wherein one output end of the second exclusive OR gate is electrically connected with the output end of the first NAND gate, one output end of the second exclusive OR gate is electrically connected with the output end of the second NAND gate, and the output end of the second exclusive OR gate is electrically connected with the input end of the second inverter.
10. The latch circuit of claim 9, wherein, The switch assembly comprises a first switch, a second switch and a third switch, wherein the first switch and the third switch are connected in series between the first latch assembly and the latch output end, the second switch is connected in series between the second latch assembly and the latch output end, the first control end of the first switch is electrically connected with the output end of the first exclusive OR gate, the second control end of the first switch is electrically connected with the output end of the first inverter, the first control end of the second switch is electrically connected with the output end of the second exclusive OR gate, the second control end of the second switch is electrically connected with the output end of the second inverter, the second control end of the third switch is electrically connected with the output end of the second exclusive OR gate, and the first control end of the third switch is electrically connected with the output end of the second inverter.