Driving circuit of synchronous focusing lens

Abstract

The utility model provides a driving circuit of a synchronous focusing lens, which has low performance requirements on a driving chip. The circuit comprises an interface, a driving chip, a first filter capacitor, a first driving resistor, a second driving resistor, a filter capacitor group and a bootstrap capacitor. A GND pin of the driving chip is grounded, a VIN pin is connected with a positive electrode of a power supply, a VDD pin is grounded through a first filter capacitor, an SENA pin is grounded through a first driving resistor, an SENB pin is grounded through a second driving resistor, an OUT pin is connected with an interface, and a BST pin is connected with the VIN pin through a bootstrap capacitor; one end of the filter capacitor bank is connected with the VIN pin of the driving chip and the positive electrode of the power supply, the other end of the filter capacitor bank is grounded, and a plurality of second filter capacitors arranged in parallel are arranged in the filter capacitor bank.

Description

TECHNICAL FIELD

[0001] The utility model relates to a drive circuit of synchronous focusing lens. BACKGROUND

[0002] In the prior art, in the process that the lens of a digital video camera automatically tracks the movement of a target object (such as the face of a moving person), in order to maintain the visibility of the picture, in addition to the up-down and left-right movement of the lens body, zooming of the lens is also needed, which inevitably causes the picture to be blurred, that is, the lens is out of focus after zooming. In order to solve this problem, a synchronous focusing lens technology is proposed, which is a lens product with a large depth of field that completely relies on optical principles to ensure the clarity of the image throughout the process.

[0003] At present, the drive circuit for driving the action of the synchronous focusing lens mostly adopts the existing automatic focusing lens drive circuit technology, and the overall circuit is relatively complex, and the performance requirement of the drive chip is high. UTILITY MODEL CONTENTS

[0004] The utility model aims at overcoming the above-mentioned deficiencies in the prior art, and provides a drive circuit of synchronous focusing lens with a reasonable structure design, which has a low performance requirement for the drive chip.

[0005] The utility model provides a drive circuit of synchronous focusing lens, which comprises an interface and a drive chip, and is characterized in that: the drive circuit further comprises a first filter capacitor, a first drive resistor, a second drive resistor, a filter capacitor group and a bootstrap capacitor; the GND pin of the drive chip is grounded, the VIN pin is connected with the positive electrode of a power supply, the VDD pin is grounded through the first filter capacitor, the SENA pin is grounded through the first drive resistor, the SENB pin is grounded through the second drive resistor, the OUT pin is connected with the interface, and the BST pin is connected to the VIN pin through the bootstrap capacitor; one end of the filter capacitor group is connected with the VIN pin of the drive chip and the positive electrode of the power supply, and the other end is grounded, and a plurality of second filter capacitors are arranged in parallel in the filter capacitor group.

[0006] The model of the drive chip is mp6507.

[0007] The NSLEEP signal pin of the drive chip is a normal working / standby state control pin, which controls the drive chip to be in a normal working state or a standby state.

[0008] The filter capacitor group is provided with three second filter capacitors arranged in parallel.

[0009] Compared with the prior art, the utility model has the following advantages and effects: because the synchronous focusing lens can ensure the whole image clear by the optical principle, so the utility model discloses simple circuit, but the synchronous focusing lens can be combined, and the clear image under most depth of field can be realized, so the utility model discloses can reduce the performance requirement of the driving chip, and the development and production cost are saved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 The circuit schematic diagram of the utility model embodiment. DETAILED DESCRIPTION

[0011] The utility model will be further explained in detail in combination with the drawings and through the embodiment, and the following embodiment is the explanation of the utility model, and the utility model is not limited to the following embodiment.

[0012] The utility model embodiment includes driving chip U4, and the model number of driving chip U4 is mp6507.The NSLEEP signal pin of driving chip U4 is normal working / standby state control pin, and the program control can be realized on the circuit, controls driving chip U4 to be in normal working state or standby state, to reach the purpose of saving power when hibernation, and the high level in the drawing indicates that it is powered all the time.The GND pin of driving chip U4 is grounded.

[0013] The VDD pin of driving chip U4 is grounded through first filter capacitor C37, and first filter capacitor C37 is used for power filtering.

[0014] The SENA pin of driving chip U4 is grounded through first driving resistor R27, and the SENB pin is grounded through second driving resistor R31.First driving resistor R27 and second driving resistor R31 are used for setting driving current.

[0015] The OUT pin of driving chip U4 is connected with interface J3, and interface J3 is connected with synchronous focusing lens.

[0016] The VIN pin of driving chip U4 is connected with the positive pole of power supply, and 3.3V power supply is input.

[0017] One end of filter capacitor group is connected with the VIN pin of driving chip U4 and the positive pole of power supply, and the other end is grounded.A plurality of second filter capacitors arranged in parallel are arranged in filter capacitor group, to realize the filtering effect of different frequency bands.In the embodiment, three second filter capacitors C39, C40 and C41 are arranged.

[0018] The BST pin of driving chip U4 is connected to the VIN pin through bootstrap capacitor C39, and bootstrap capacitor C39 is used for driving the gate of high-side MOS tube in driving chip U4, and bootstrap capacitor C39 is refreshed and charged when the high-side MOS tube is off and the low-side diode is on.

[0019] The utility model discloses through the control signal of received GPIO1-GPIO4, output 4 ZOOM signals A+, A-, B+, B- to control the action of synchronous focusing lens zoom motor.

[0020] In addition, it needs to explain that the specific embodiments described in the specification, the shape of zero, component, the name taken etc. can be different, the above contents described in the specification are only the example of the structure of the utility model. The equivalent change or simple change of the structure, feature and principle according to the utility model patent concept is included in the protection scope of the utility model patent.

Claims

1. A driving circuit of a synchronous focusing lens, comprising an interface and a driving chip, characterized in that: Also include the first filter capacitor, the first drive resistance, the second drive resistance, filter capacitor group and bootstrap capacitor; the GND pin of the drive chip is grounded, the VIN pin is connected with the positive pole of the power supply, the VDD pin is grounded through the first filter capacitor, the SENA pin is grounded through the first drive resistance, the SENB pin is grounded through the second drive resistance, the OUT pin is connected with the interface, and the BST pin is connected to the VIN pin through the bootstrap capacitor; One end of the filter capacitor group is connected with the VIN pin of the drive chip and the positive pole of the power supply, and the other end is grounded, and a plurality of second filter capacitors arranged in parallel are arranged in the filter capacitor group.

2. The driving circuit of a synchronous focus lens according to claim 1, wherein: The model of the drive chip is mp6507.

3. The driving circuit of a synchronous focus lens according to claim 1, wherein: The NSLEEP signal pin of the drive chip is a normal working / standby state control pin, which controls the drive chip to be in a normal working state or a standby state.

4. The driving circuit of a synchronous focus lens according to claim 1, wherein: The filter capacitor group is provided with three second filter capacitors arranged in parallel.

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