Variable capacitance diode
By designing an oblique groove and an anode field plate structure in the GaN diode, the problem of insufficient varactor capability of traditional GaN diodes is solved, achieving a wide range of stable capacitance changes and controllability, making it suitable for high-power applications.
Patent Information
- Application Number
- CN202423323508.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Traditional grooved anode GaN diodes have insufficient varactor capability, with rapid capacitance changes and poor controllability, making them unsuitable for use as varactor diodes.
By designing an oblique groove structure and setting an obtuse angle between the sidewall and bottom wall of the etched groove, and setting an anode field plate on the passivation layer, the two-dimensional electron gas is gradually depleted, thereby controlling the capacitance change.
The range of varactor diodes has been increased, and the capacitance has been changed smoothly, which improves the controllability and high-power performance of the varactor diodes.
Smart Images
Figure CN223730187U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of diodes, in particular to a varactor diode. BACKGROUND
[0002] As a wide band gap semiconductor material, GaN material has great electrical performance advantages. The AlGaN / GaN heterojunction structure can induce a high concentration of two-dimensional electron gas on the GaN side near the interface due to its strong spontaneous polarization and piezoelectric polarization effect. Since the electrons are confined in the potential well and the impurity doping in this region is very small, ionized impurity scattering and alloy disorder scattering are small, and the two-dimensional electron gas has extremely high mobility and electron saturation rate. Moreover, due to the wide band gap property of GaN material, the critical breakdown field strength is extremely large, which is suitable for making high-power voltage-resistant diodes. However, in the preparation of the traditional recessed anode GaN diode, due to the requirement of process stability, the range of the anode metal evaporation is slightly larger than the anode recess, and the metal edge position is on the AlGaN to form a field plate structure, which introduces the capacitance generated by the overlap of the Schottky anode and the two-dimensional electron gas.
[0003] The traditional recessed anode GaN diode is mostly a microwave diode, which requires as small a capacitance as possible. An etching recess is introduced below the anode. Since the heterojunction structure is destroyed, the etching recess area capacitance is eliminated, and the device capacitance is greatly reduced. Moreover, the traditional recessed anode GaN diode has a certain varactor capacity under negative voltage bias. However, since the etching angle of the etching recess is close to vertical, the capacitance changes rapidly, and often drops sharply when the two-dimensional electron gas is depleted, which has poor controllability. Moreover, the field plate length is generally small, the formed capacitance is not large, and the capacitance variable range is limited, which cannot be used as a varactor diode. CONTENT OF THE INVENTION
[0004] The purpose of the present application is to provide a varactor diode which can not only increase the varactor range, but also realize large-range smooth capacitance change.
[0005] The embodiment of the present application is implemented as follows:
[0006] In a first aspect, the application provides a variable capacitance diode, comprising a substrate, a channel layer, a barrier layer and a cap layer which are sequentially stacked on the substrate, a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer, the cap layer is divided into a first region and a second region, a cathode is arranged in the first region, and a passivation layer is arranged between the cathode and the second region; the passivation layer in the second region is etched to sequentially penetrate the cap layer and the barrier layer to expose the inside of the channel layer, so that the bottom wall of the etched groove is located in the inside of the channel layer, and the included angle between the side wall of the etched groove and the bottom wall is an obtuse angle, and an anode is arranged on the bottom wall, the side wall of the etched groove and the passivation layer in the second region.
[0007] As an implementable manner, the distance between the bottom wall of the etched groove and the surface of the channel layer away from the substrate is 5nm-25nm.
[0008] As an implementable manner, the included angle between the side wall of the etched groove and the bottom wall is 110°-150°.
[0009] As an implementable manner, the length of the field plate of the anode is 0.5μm-50μm.
[0010] As an implementable manner, the passivation layer is a silicon nitride passivation layer with a thickness of 50nm-500nm, a silicon oxide passivation layer, a double-layer composite passivation layer of aluminum oxide with a thickness of 10nm-40nm and silicon nitride with a thickness of 50nm-500nm, or a double-layer composite passivation layer of silicon nitride with a thickness of 10nm-40nm and silicon oxide with a thickness of 50nm-500nm.
[0011] As an implementable manner, the substrate is a silicon carbide substrate with a thickness of 100μm-600μm, a sapphire substrate with a thickness of 100μm-600μm, a silicon substrate with a thickness of 100μm-1000μm, or a gallium nitride substrate with a thickness of 100μm-600μm.
[0012] As an implementable manner, the channel layer is an unintentionally doped gallium nitride channel layer with a thickness of 100nm-400nm.
[0013] As an implementable manner, the anode is a metal laminated anode of tungsten or molybdenum or nickel with a thickness of 30nm-200nm and gold with a thickness of 0nm-200nm.
[0014] As an implementable manner, a buffer layer is arranged between the substrate and the channel layer.
[0015] As an implementable manner, the buffer layer is a gallium nitride buffer layer with a thickness of 1-6 μm or an aluminum gallium nitride buffer layer with a thickness of 1-6 μm or an aluminum nitride buffer layer with a thickness of 0.2-1 μm.
[0016] The beneficial effects of the embodiments of the present application include:
[0017] The varactor diode comprises a substrate, a channel layer, a barrier layer and a cap layer which are sequentially arranged on the substrate, a two-dimensional electron gas is formed at the interface of the channel layer and the barrier layer, the cap layer is divided into a first region and a second region, a cathode is arranged in the first region, and a passivation layer is arranged between the cathode and the second region; the passivation layer in the second region is etched and sequentially penetrates the cap layer and the barrier layer to expose the inside of the channel layer, so that the bottom wall of the etching groove is located in the inside of the channel layer, the included angle between the side wall and the bottom wall of the etching groove is obtuse, and an anode is arranged on the bottom wall, the side wall of the etching groove and the passivation layer in the second region. The varactor diode provided in the present application can make the anode gradually deplete the two-dimensional electron gas of the device, so as to effectively control the capacitance of the device and realize a stable and controllable high-power varactor diode. In addition, the varactor diode provided in the present application further comprises an anode field plate structure arranged above the passivation layer in the second region, or the passivation layer medium is filled below the anode field plate structure, so that the capacitance of the device changes gently and the capacitance change range of the varactor diode is regulated. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.
[0019] Figure 1 One of the preparation schematic diagrams of the varactor diode provided in the embodiments of the present application;
[0020] Figure 2 The second preparation schematic diagram of the varactor diode provided in the embodiments of the present application;
[0021] Figure 3 The third preparation schematic diagram of the varactor diode provided in the embodiments of the present application;
[0022] Figure 4 The fourth preparation schematic diagram of the varactor diode provided in the embodiments of the present application;
[0023] Figure 5Figure 5 is a schematic diagram of a preparation of a varactor diode according to an embodiment of the present application;
[0024] Figure 6 Figure 6 is a schematic diagram of a preparation of a varactor diode according to an embodiment of the present application;
[0025] Figure 7 Figure 7 is a schematic diagram of a preparation of a varactor diode according to an embodiment of the present application.
[0026] Legend: 10 - substrate; 20 - buffer layer; 30 - channel layer; 40 - barrier layer; 50 - cap layer; 60 - cathode; 70 - passivation layer; 80 - anode; 81 - anode with slanted recesses; 82 - anode field plate. DETAILED DESCRIPTION
[0027] The implementations set forth below represent the necessary information for enabling those skilled in the art to practice the implementations and illustrate best modes of practicing them. Upon reading the following description, one skilled in the art will understand how to implement the concepts described herein with appropriate hardware, software, and firmware. The concepts described herein can be implemented with or without employing any hardware, software, and firmware described below. The described implementations are to be considered in a descriptive sense only and not limiting. Furthermore, the described implementations can be implemented in any number of ways, and are not limited to the described implementations.
[0028] It should be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0029] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extended to" another element, it can be directly on or extended to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly extended to" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
[0030] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" can be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures.
[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0033] In order to overcome the problems of insufficient varactor capability, rapid change of capacitance and poor controllability of conventional recessed anode diodes, please refer to the following Figures 1 to 7The application provides a varactor diode, by designing an included angle between a side wall and a bottom wall of an etching groove as an obtuse angle to form an inclined groove, which can not only increase a varactor range of the device, but also realize a large range of smooth capacitance change.
[0034] Specifically, as shown in the first aspect of the embodiment of the application, Figure 7 a varactor diode includes a substrate 10, a channel layer 30, a barrier layer 40 and a cap layer 50 which are sequentially stacked on the substrate 10, a two-dimensional electron gas is formed at an interface of the channel layer 30 and the barrier layer 40, the cap layer 50 is divided into a first region and a second region, a cathode 60 is arranged in the first region, and a passivation layer 70 is arranged between the cathode 60 and the second region; the passivation layer 70 in the second region is etched and sequentially penetrates the cap layer 50 and the barrier layer 40 to expose the inside of the channel layer 30, so that the bottom wall of the formed etching groove is located in the inside of the channel layer 30, the included angle between the side wall and the bottom wall of the etching groove is an obtuse angle, and an anode 80 is arranged on the bottom wall, the side wall of the etching groove and the passivation layer 70 in the second region.
[0035] It should be noted that, as shown in the first aspect of the embodiment of the application, Figures 1 to 7 the varactor diode includes a substrate 10, which serves as a material basis of the varactor diode to support and protect other levels, a channel layer 30 is arranged on the upper surface of the substrate 10, and a barrier layer 40 is arranged on the upper surface of the channel layer 30; along the stacking direction of the multiple levels on the substrate 10, since the upper surface of the channel layer 30 and the lower surface of the barrier layer 40 are in contact with each other, a heterojunction will be formed at the interface of the channel layer 30 and the barrier layer 40, and since a two-dimensional electron gas (2DEG) inherently exists at the heterojunction, electrons can move freely along the interface.
[0036] A cap layer 50 is arranged on the upper surface of the barrier layer 40, the upper surface of the cap layer 50 is divided into a first region and a second region according to actual needs, a cathode 60 is arranged in the first region, and a passivation layer 70 is arranged between the cathode 60 and the second region; after the growth of the passivation layer 70 is completed, the passivation layer 70 in the second region is etched and sequentially penetrates the cap layer 50 and the barrier layer 40 until the inside of the channel layer 30 is exposed, so that the bottom wall of the formed etching groove is located in the inside of the channel layer 30, and the included angle between the side wall and the bottom wall of the etching groove is designed as an obtuse angle, and then an anode 80 is arranged on the bottom wall, the side wall of the etching groove and the passivation layer 70 in the second region, wherein the anode 80 includes an inclined groove anode 81 located on the bottom wall and the side wall of the etching groove and an anode field plate 82 located on the passivation layer 70 in the second region.
[0037] The variable capacitance diode provided in the application can make the anode 80 gradually deplete the two-dimensional electron gas of the device by designing the included angle between the sidewall and the bottom wall of the etched groove as an obtuse angle, so as to effectively control the capacitance of the device, realize a stable and controllable large-power variable capacitance diode; in addition, the variable capacitance diode provided in the application is also provided with an anode field plate 82 structure above the passivation layer 70 located in the second region, or in other words, the passivation layer 70 medium is filled below the anode field plate 82 structure, so as to make the capacitance of the device change gently, and realize the regulation and control of the capacitance change range of the variable capacitance diode.
[0038] As an implementable manner, the distance between the bottom wall of the etched groove and the surface of the channel layer 30 away from the substrate 10 (i.e. the upper surface of the channel layer 30) is 5nm-25nm. As an implementable manner, the included angle between the sidewall and the bottom wall of the etched groove is 110°-150°. As an implementable manner, the length of the anode field plate 82 is 0.5μm-50μm. As an implementable manner, the passivation layer 70 is a silicon nitride passivation layer or a silicon oxide passivation layer with a thickness of 50nm-500nm, or a double-layer composite passivation layer of aluminum oxide with a thickness of 10nm-40nm and silicon nitride with a thickness of 50nm-500nm, or a double-layer composite passivation layer of silicon nitride with a thickness of 10nm-40nm and silicon oxide with a thickness of 50nm-500nm. As an implementable manner, the substrate 10 is a silicon carbide substrate with a thickness of 100μm-600μm, or a sapphire substrate with a thickness of 100μm-600μm, or a silicon substrate with a thickness of 100μm-1000μm, or a gallium nitride substrate with a thickness of 100μm-600μm. As an implementable manner, the channel layer 30 is an unintentionally doped gallium nitride channel layer with a thickness of 100nm-400nm. As an implementable manner, the anode 80 is a metal laminated anode of tungsten or molybdenum or nickel with a thickness of 30nm-200nm and gold with a thickness of 0nm-200nm. As an implementable manner, a buffer layer 20 is arranged between the substrate 10 and the channel layer 30, and the buffer layer 20 helps to form a high-quality channel layer 30. As an implementable manner, the buffer layer 20 is a gallium nitride buffer layer with a thickness of 1μm-6μm, or a gallium aluminum nitride graded buffer layer with a thickness of 1μm-6μm, or an aluminum nitride buffer layer with a thickness of 0.2μm-1μm.
[0039] In summary, the variable capacitance diode provided by the application changes the vertical groove of the traditional recessed anode diode into an inclined groove, and increases the length of the device anode field plate 82. The main source of the device capacitance is the flat plate capacitance generated by the overlap of the anode field plate 82 and the two-dimensional electron gas. Therefore, increasing the length of the anode field plate 82 can effectively increase the capacitance. In addition, when a negative voltage is applied to the inclined groove anode 81, the two-dimensional electron gas is gradually depleted as the negative voltage gradually increases, which is equivalent to the gradual reduction of the facing area of the flat plate capacitance. Therefore, stable control of the capacitance can be achieved. Meanwhile, the passivation layer 70 is filled below the anode field plate 82. The filling of the passivation layer 70 increases the distance between the field plate and the two-dimensional electron gas, and weakens the control ability of the field plate on the two-dimensional electron gas. Therefore, the device capacitance can change more smoothly and stably. In addition, the thickness of the passivation layer 70 can be changed to adjust the size of the device capacitance. The length of the anode field plate 82 and the thickness of the passivation layer 70 jointly adjust the capacitance variation range.
[0040] As shown in Figures 1 to 7 Figures 1 to 7 the second aspect of the embodiment of the application, a preparation method of a variable capacitance diode is provided. The technical key of the preparation method is to grow a passivation layer 70 dielectric after the ohmic contact of the cathode 60 and the mesa isolation treatment, to etch an inclined groove with a large inclination angle by using slow etching, to form an anode field plate 82 with a large length after the evaporation of the anode 80 metal, and finally to etch and open the dielectric on the ohmic contact of the cathode 60 to complete the preparation of the inclined groove anode 81 high-power variable capacitance diode. The preparation method of the variable capacitance diode provided by the application is simple to operate, and has the advantages of strong feasibility and high yield. The preparation method specifically includes the following steps.
[0041] S100, cleaning the epitaxial wafer:
[0042] The AlGaN / GaN structure epitaxial wafer is first soaked in an HF acid solution or an HCl acid solution for 30 s, and then sequentially placed in an acetone solution, an isopropyl alcohol solution, an anhydrous ethanol solution and deionized water for ultrasonic cleaning for 5 min each time, and then dried with nitrogen;
[0043] S200, manufacturing a high-power GaN variable capacitance diode cathode 60:
[0044] S201, sequentially performing uniform glue application, glue baking, device cathode 60 area photolithography and development on a clean epitaxial wafer, and depositing a Ti / Al / Ni / Au metal stack on the epitaxial wafer by using an electron beam evaporation device;
[0045] S202, first soaking the epitaxial wafer on which the Ti / Al / Ni / Au metal stack is deposited in an acetone solution to strip the metal in the photoresist area, and then sequentially placing the epitaxial wafer in an acetone solution, an isopropyl alcohol solution, an anhydrous ethanol solution and a deionized water solution for ultrasonic cleaning for 5 min each time, and then drying with nitrogen and placing in a rapid annealing furnace for annealing to form the device cathode 60;
[0046] S300, making mesa isolation:
[0047] S301, performing uniform glue, baking glue, mesa isolation photoetching and developing, and hardening film on the epitaxial wafer after making cathode 60 ohm contact;
[0048] S302, etching GaN mesa outer area using ICP etching machine;
[0049] S303, placing the epitaxial wafer after etching into clean acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and blowing dry with nitrogen, to form device isolation;
[0050] S400, medium deposition:
[0051] Depositing SiN or SiO2 medium with thickness of 50nm-500nm on the epitaxial wafer after making mesa isolation using plasma enhanced chemical vapor deposition equipment;
[0052] S500, making anode 80 groove:
[0053] S501, performing uniform glue, baking glue, anode 80 groove photoetching and developing, and hardening film on the epitaxial wafer after medium deposition in sequence;
[0054] S502, first etching SiN or SiO2 medium in anode 80 opening area of the epitaxial wafer to the upper surface of barrier layer 40 at a slow speed using RIE etching machine, then etching barrier layer 40 and channel layer 30 to 5nm-25nm below AlGaN / GaN interface at a slow speed using ICP etching machine, to form a slanting groove, and placing the epitaxial wafer into acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and blowing dry with nitrogen, to complete the making of slanting groove anode 81;
[0055] S600, making high-power GaN varactor diode anode 80:
[0056] S601, performing uniform glue, baking glue, device anode 80 area photoetching and developing on the epitaxial wafer after etching anode 80 groove in sequence, and depositing low work function metal W or Mo or Ni with thickness of 30nm-200nm on the epitaxial wafer first, and then depositing metal Au with thickness of 0nm-200nm using magnetron sputtering equipment or electron beam evaporation equipment;
[0057] S602, immersing the epitaxial wafer after step S601 operation into acetone solution, so that the metal on the photoresist area is stripped, to form anode 80 metal field plate with thickness of 0.5μm-50μm, and then placing the epitaxial wafer into clean acetone, isopropyl alcohol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and blowing dry with nitrogen.
[0058] S700, cathode 60 medium opening:
[0059] S701, after the epitaxial wafer of anode 80 is done, uniform glue, baking, via lithography, development and film are sequentially performed, and RIE etching machine is used to etch the via area to the surface of cathode 60 metal;
[0060] S702, the epitaxial wafer after step S701 operation is sequentially put into acetone, isopropyl alcohol, anhydrous ethanol, deionized water solution and ultrasonic cleaning for 5 minutes, and nitrogen is used to dry, so that the production of variable capacitance diode with inclined groove anode 81 is completed.
[0061] The above only describes optional embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.
[0062] In addition, it should be noted that various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again in the present application.
Claims
1. A varactor diode, characterized by, The device comprises a substrate, a channel layer, a barrier layer and a cap layer which are sequentially stacked on the substrate, a two-dimensional electron gas is formed at the interface of the channel layer and the barrier layer, the cap layer is divided into a first region and a second region, a cathode is arranged in the first region, and a passivation layer is arranged between the cathode and the second region; The passivation layer in the second region is etched to sequentially penetrate the cap layer and the barrier layer to expose the inside of the channel layer, so that the bottom wall of the formed etching groove is located in the inside of the channel layer, the included angle between the side wall of the etching groove and the bottom wall is obtuse, and an anode is arranged on the bottom wall, the side wall of the etching groove and the passivation layer in the second region.
2. The varactor diode of claim 1, wherein The distance between the bottom wall of the etching groove and the surface of the channel layer away from the substrate is 5nm-25nm.
3. The varactor diode of claim 1, wherein The included angle between the side wall of the etching groove and the bottom wall is 110°-150°.
4. The varactor diode of claim 1, wherein The length of the field plate of the anode is 0.5μm-50μm.
5. The varactor diode of claim 1, wherein The passivation layer is a silicon nitride passivation layer with a thickness of 50nm-500nm, a silicon oxide passivation layer, a double-layer composite passivation layer of aluminum oxide with a thickness of 10nm-40nm and silicon nitride with a thickness of 50nm-500nm, or a double-layer composite passivation layer of silicon nitride with a thickness of 10nm-40nm and silicon oxide with a thickness of 50nm-500nm.
6. The varactor diode of claim 1, wherein The substrate is a silicon carbide substrate with a thickness of 100μm-600μm, a sapphire substrate with a thickness of 100μm-600μm, a silicon substrate with a thickness of 100μm-1000μm, or a gallium nitride substrate with a thickness of 100μm-600μm.
7. The varactor diode of claim 1, wherein The channel layer is an unintentionally doped gallium nitride channel layer with a thickness of 100nm-400nm.
8. The varactor diode of claim 1, wherein The anode is a metal stack anode of tungsten or molybdenum or nickel with a thickness of 30nm-200nm and gold with a thickness of 0nm-200nm.
9. The varactor diode of claim 1, wherein, A buffer layer is arranged between the substrate and the channel layer.
10. The varactor diode of claim 9, wherein The buffer layer is a gallium nitride buffer layer with a thickness of 1μm-6μm, a gallium aluminum nitride buffer layer with a thickness of 1μm-6μm, or an aluminum nitride buffer layer with a thickness of 0.2μm-1μm.