Semiconductor device with near-gate field plate

Abstract

The utility model provides a semiconductor device with a near-gate field plate, which comprises a substrate, an epitaxial layer, a first dielectric layer, a basic dielectric layer, a first metal layer, a second dielectric layer and a second metal layer, and is characterized in that the basic dielectric layer is provided with a source metal hole and a drain metal hole which penetrate through the first dielectric layer and the second dielectric layer; forming a source electrode on the source electrode metal hole, forming a drain electrode on the drain electrode metal hole, and forming a first field plate on the second dielectric layer; a gate metal hole penetrating through the second dielectric layer and the basic dielectric layer is formed in the second dielectric layer, so that a gate is formed in the gate metal hole.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic device technical field, especially a kind of semiconductor device with near gate field plate. BACKGROUND

[0002] Gallium nitride high electron mobility transistor (High Electron Mobility Transistors, GaN HEMT) as the representative of wide band gap (WBG) power semiconductor device, it has huge potential in high-frequency power application. In the design of lateral GaN HEMT switching device, the withstand voltage capability of switching device is a very important performance parameter, when the switching device is off, the main withstand voltage structure of lateral GaN HEMT switching device is the depletion region between gate (G) and drain (D), under the same depletion region size, the electric field distribution determines the size of withstand voltage, and there is an electric field concentration effect in the gate corner near the drain side, which causes an electric field peak to exist here, when the electric field peak reaches a certain critical value, electric field breakdown occurs, thereby affecting the reliability of the device, and even irreversible damage occurs.

[0003] In order to improve the withstand voltage capability of semiconductor device, field plate structure is generally used, the main function of field plate is to adjust the electric field distribution of drift region, to weaken the electric field peak originally existing near the gate, and to improve the withstand voltage of semiconductor device. The introduction of field plate can reduce the original electric field peak, but a new electric field peak exists at the end of field plate. For high-voltage semiconductor devices, a single field plate often cannot achieve ideal electric field distribution. Generally, high-voltage semiconductor devices have multi-stage field plate structure for modulating electric field distribution. Using this method, each layer of field plate from the gate to the drain direction will further modulate the electric field peak generated by the previous field plate, and by adjusting the length and height of each stage of field plate, an optimized electric field distribution is obtained, and higher withstand voltage and reliability are achieved.

[0004] In order to realize multi-layer field plate in semiconductor device, multiple etching of dielectric layer and metal and multiple photolithography steps are often required in existing structures, and with the increase of the number of field plate layers, the process cost and time cost will also increase significantly. For example, in the current mainstream 650V gallium nitride HEMT chip, generally 3-4 layers of field plate are required, so the production of gate and field plate metal needs to be performed 4-5 times of photolithography, which accounts for 20%-30% of the process cost and time cost in the whole chip flow process. SUMMARY

[0005] The semiconductor device with near gate field plate provided by the embodiment of the utility model simplifies the implementation cost and time of setting field plate in semiconductor device.

[0006] The utility model embodiment provides a kind of semiconductor device with near gate field plate, comprising:

[0007] Substrate;

[0008] Epitaxial layer, disposed on the substrate;

[0009] First dielectric layer and base dielectric layer, disposed on the epitaxial layer, the base dielectric layer is provided with source metal hole, drain metal hole through the first dielectric layer and the base dielectric layer;

[0010] First metal layer, disposed on the base dielectric layer, to form source on the source metal hole, form drain on the drain metal hole, and form second layer field plate on the base dielectric layer;

[0011] Second dielectric layer, disposed on the first metal layer, the second dielectric layer is provided with gate metal hole through the second dielectric layer and the base dielectric layer, and at least one first layer field plate area through the second dielectric layer and part of the base dielectric layer;And

[0012] Second metal layer, disposed on the second dielectric layer, to form gate on the gate metal hole and form first layer field plate in the first layer field plate area.

[0013] The utility model embodiment provides a kind of semiconductor device with near gate field plate, comprising:

[0014] Substrate;

[0015] Epitaxial layer, disposed on the substrate;

[0016] First dielectric layer and base dielectric layer, disposed on the epitaxial layer, the base dielectric layer is provided with source metal hole, drain metal hole through the first dielectric layer and the base dielectric layer;

[0017] First metal layer, disposed on the base dielectric layer, to form source on the source metal hole, form drain on the drain metal hole, and form second layer field plate on the base dielectric layer;

[0018] Second dielectric layer, disposed on the first metal layer;

[0019] Second metal layer, disposed on the second dielectric layer, to form third layer field plate on the second dielectric layer, the third layer field plate is above the second layer field plate, and the third layer field plate and second layer field plate in the projection of substrate direction have overlapping region;

[0020] a third dielectric layer disposed on the second metal layer, the third dielectric layer having a gate metal hole penetrating through the third dielectric layer, the second dielectric layer and the base dielectric layer, and at least one first layer field plate region penetrating through the third dielectric layer, the second dielectric layer and part of the base dielectric layer; and

[0021] a third metal layer disposed on the third dielectric layer to form a gate on the gate metal hole and a first layer field plate on the first layer field plate region.

[0022] It can be seen that, in the process of manufacturing the semiconductor device with the near-gate field plate, the second layer field plate, the source and the drain in the semiconductor device are formed in the same step, so that the source, the drain and the second layer field plate are formed on the same layer, and the gate and the first layer field plate and even the third layer field plate are formed in the same step, so that the manufacturing steps of the semiconductor device with the near-gate field plate are simplified, and the implementation cost and time of the field plate in the semiconductor device are simplified. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0024] Figure 1 is a flow chart of a manufacturing method of a semiconductor device with a near-gate field plate provided by the embodiments of the present application;

[0025] Figure 2a is a sectional view of a semiconductor device with three layer field plates in the embodiments of the present application;

[0026] Figure 2b is a sectional view of a semiconductor device in the process of metal deposition and metal etching in the embodiments of the present application;

[0027] Figure 2c is a schematic view of a source, a drain and a second layer field plate formed after the process of metal deposition and metal etching in the embodiments of the present application;

[0028] Figure 3 is a sectional view of another semiconductor device with three layer field plates in the embodiments of the present application;

[0029] Figure 4 is a sectional view of a semiconductor device with four layer field plates in the embodiments of the present application;

[0030] Figure 5a is a sectional view of another semiconductor device including four-layer field plates in an embodiment of the present application;

[0031] Figure 5b is a sectional view of another semiconductor device including four-layer field plates in an embodiment of the present application;

[0032] Figure 6 is a flowchart of another manufacturing method of a semiconductor device having near-gate field plates in an embodiment of the present application;

[0033] Figure 7 is a sectional view of a semiconductor device including four-layer field plates in an embodiment of the present application;

[0034] Figure 8 is a sectional view of another semiconductor device including four-layer field plates in an embodiment of the present application;

[0035] Figure 9a is a sectional view of another semiconductor device including four-layer field plates in an embodiment of the present application;

[0036] Figure 9b is a sectional view of another semiconductor device including four-layer field plates in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] The terms "first", "second", "third", "fourth" and the like (if any) in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0039] The semiconductor device with the near-gate field plate provided by the embodiment of the utility model includes MIS-HEMT device, P-GaN HEMT device, SBD-Gate HEMT and the like, and these semiconductor devices can be various semiconductor materials, for example, gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO) and the like.

[0040] The semiconductor device includes a substrate, an epitaxial layer, and a first dielectric layer, a base dielectric layer, a first metal layer, a second dielectric layer and a second metal layer arranged on the epitaxial layer in sequence.

[0041] The epitaxial layer is arranged on the substrate, the first dielectric layer and the base dielectric layer are arranged on the epitaxial layer, the base dielectric layer is provided with a source metal hole and a drain metal hole penetrating the first dielectric layer and the base dielectric layer, the first metal layer is arranged on the base dielectric layer to form a source on the source metal hole, a drain on the drain metal hole and a second layer field plate on the base dielectric layer, the second dielectric layer is arranged on the first metal layer, the second dielectric layer is provided with a gate metal hole penetrating the second dielectric layer and the base dielectric layer and at least one first layer field plate region penetrating the second dielectric layer and part of the base dielectric layer, and the second metal layer is arranged on the second dielectric layer to form a gate on the gate metal hole and a first layer field plate on the first layer field plate region.

[0042] Specifically, as shown in the figure, Figure 1 the manufacturing method of the semiconductor device with the near-gate field plate includes:

[0043] In step 101, a first dielectric layer and a base dielectric layer are deposited on an epitaxial layer of a substrate, the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and the first dielectric layer and the base dielectric layer are subjected to dielectric etching to form a source-drain dielectric.

[0044] Generally, in the manufacturing process of a semiconductor device, various parts included in the semiconductor device, such as a source, a gate, a drain and a field plate, are arranged on an epitaxial layer of a substrate to obtain the semiconductor device.

[0045] In this embodiment, the fabrication of a semiconductor device involves multiple processes on the epitaxial layer of a substrate to form the final semiconductor device. First, a first dielectric layer is deposited on the epitaxial layer of the substrate. This first dielectric layer primarily serves as insulation and isolation. A base dielectric layer is then deposited on the first dielectric layer, comprising multiple dielectric layers and at least one barrier layer sandwiched between the dielectric layers. Further, when the semiconductor device includes a source and a drain, the first dielectric layer and the base dielectric layer need to be etched to form the source and drain dielectrics, ensuring that the subsequently formed source and drain are on the same layer.

[0046] Dielectric etching is mainly a process of selectively removing unwanted materials from the wafer surface (specifically, the first dielectric layer and the base dielectric layer in this embodiment). This process can be achieved by various methods, including physical means (such as ion milling) and chemical means (such as plasma etching). During dielectric etching, a mask is used to protect the materials that need to be retained, while the exposed materials are removed.

[0047] It should be noted that in this embodiment, the source and gate of the semiconductor device are placed in different layers, that is, the depths of the source and gate are different, which can effectively prevent short circuits between the source and gate. In order to facilitate the layering of the source and gate, a first dielectric layer and a base dielectric layer need to be set on the epitaxial layer. When the first dielectric layer and the base dielectric layer are etched to form the source and drain dielectric, it is necessary to etch through the first dielectric layer and the base dielectric layer to expose the epitaxial layer of the source and drain regions. When the gate dielectric is subsequently etched to form the gate dielectric, it is not necessary to etch through the first dielectric layer, but only to etch through the base dielectric layer to expose the first dielectric layer of the gate region.

[0048] The fabrication processes of adjacent dielectric layers can differ, such as the dielectric layers in the first dielectric layer and the base dielectric layer. The dielectric layers become denser towards the bottom, resulting in a slower etching rate. This slows down the etching rate at the interface between two adjacent dielectric layers, allowing for better control of the etching depth. Furthermore, in this embodiment, at least one barrier layer in the base dielectric layer protects the etching interface; materials such as AlN can be used as the barrier layer.

[0049] like Figure 2a The diagram shows a cross-sectional view of a semiconductor device with a near-gate field plate. On the epitaxial layer 11 of the substrate 10, the portion includes: a source 110, a gate 111, a drain 112, and a multilayer field plate near the gate 111 (the diagram illustrates a three-layer field plate as an example). The first field plate 1131 in the multilayer field plate is connected to the gate 111, the second field plate 1132 is on the same layer as the source 110 and the drain 112, and the third field plate 1133 is connected to a first field plate 1131.

[0050] In this embodiment, a first dielectric layer 12 (the part filled with diagonal lines in the figure) and a base dielectric layer 13, in which a first sub-dielectric layer 133, a first barrier layer 132 and a second sub-dielectric layer 131 are included, are deposited on the epitaxial layer 11 of the substrate 10 in sequence. Then, a via hole is formed by etching the first dielectric layer 12 and the base dielectric layer 13, so that the source region and the drain region of the epitaxial layer 11 are exposed.

[0051] In step 102, metal deposition and metal etching are performed on the source-drain dielectric layer to form the source, the drain and the second layer field plate of the semiconductor device, and the reserved positions of the gate and at least one first layer field plate are reserved between the source and the second layer field plate.

[0052] Specifically, for example, Figure 2b As shown in the figure, a metal layer 150 can be deposited on the source-drain dielectric layer during metal deposition, and then metal etching is performed on the metal layer 150 to form the source 110 (such as the ohmic metal of the source, etc.), the drain 112 (such as the ohmic metal of the drain, etc.) and the second layer field plate 1132, and the reserved positions of the gate and at least one first layer field plate are reserved between the source 110 and the second layer field plate 1132, and the positions of other multi-layer field plates (such as the third layer field plate 1133 and the fourth layer field plate 1134, etc.) are reserved between the drain 112 and the second layer field plate 1132. In this way, the formation of the source 110, the drain 112 and the second layer field plate 1132 is concentrated in the same step, which simplifies the steps of arranging each part on the epitaxial layer 11, and the finally formed source 110, drain 112 and second layer field plate 1132 are on the same layer.

[0053] In the metal etching process, a photoresist 151 can be arranged at the positions where the metal needs to be reserved, and then the metal layer 150 is etched. In this way, the metal at the positions where the photoresist 151 is arranged is reserved, and the metal at other positions is etched. Finally, the photoresist 151 is removed, and the source 110, the drain 112 and the second layer field plate 1132 as shown in the figure are formed. Figure 2c As shown in the figure, the distance between the source 110 and the second layer field plate 1132 needs to be sufficient to accommodate the gate 111 and the first layer field plate formed later, and the distance between the second layer field plate 1132 and the drain 112 also needs to be sufficient to accommodate the other several layers of field plates formed later.

[0054] Step 103: Deposit a second dielectric layer, and perform dielectric etching on the second dielectric layer and the base dielectric layer at the reserved positions to form a gate dielectric and at least one first field plate dielectric, wherein any first field plate dielectric is under a corresponding barrier layer. Thus, the number of first field plate dielectrics can be the same as the number of barrier layers included in the base dielectric layer.

[0055] like Figure 2a As shown, after the source 110, drain 112, and second field plate 1132 are formed, a second dielectric layer 14 can be deposited. Then, dielectric etching is performed at the reserved position between the source 110 and the second field plate 1131 to form a gate dielectric and at least one first field plate dielectric (the figure illustrates one first field plate dielectric as an example). Specifically, when forming the first field plate dielectric, the second dielectric layer 14 needs to be etched through both sides of the gate dielectric position and etched under a certain barrier layer in the base dielectric layer 13, for example, etching through a dielectric layer 133 and a barrier layer 132 from top to bottom in the base dielectric layer 13 to form the first field plate dielectric. When forming the gate dielectric, the second dielectric layer 14 and the base dielectric layer 13 need to be etched through the gate dielectric position and the first dielectric layer 12 needs to be exposed to form the gate dielectric. The first field plate dielectric and the dielectric layer 133 and barrier layer 132 corresponding to the gate dielectric can be etched simultaneously.

[0056] This creates a certain depth difference between the gate dielectric and the first field plate dielectric, i.e., the distance to the substrate 10. The dielectric layers 131 and 133 are made of SiN, and the barrier layer 132 is made of AlN. Since the etching methods of these two materials are different, etching the barrier layer will not affect the bottom first dielectric layer, and etching the second dielectric layer 14 will not affect the barrier layer either, thus ensuring the flatness of the subsequent gate and the first field plate.

[0057] In this way, by providing at least one barrier layer in the base dielectric layer 13, the formation of the gate and the first field plate can be concentrated in one step, while ensuring that there is a certain depth difference between the gate and the first field plate.

[0058] Step 104: Metal deposition and metal etching are performed on the gate dielectric and at least one first field plate dielectric to form the gate and the first field plate of the semiconductor device.

[0059] Specifically, in this embodiment, the first field plate and the gate are connected together as a whole. Under normal circumstances, the field plate is connected to a low potential, thereby inducing an equivalent negative charge. This allows the electric field lines of the positive charge in the depletion region to terminate at the equivalent negative charge in the field plate, thereby alleviating the electric field spikes caused by the accumulation of electric field lines in the gate. By treating the first field plate and the gate as a whole, the electric field lines emitted by the positive charge in the depletion region can smoothly transition from the corner of the gate to the first field plate.

[0060] It should be noted that the methods in steps 101 to 104 above mainly involve setting two field plates in a semiconductor device. In other embodiments, multiple field plates can also be set in the semiconductor device, such as a third field plate, a fourth field plate, etc. Specifically:

[0061] (1) When forming the third layer of the field plate:

[0062] When metal deposition and etching are performed on the gate dielectric and the first field plate dielectric, a third field plate can also be formed. The third field plate is on top of the second field plate, and the projections of the third field plate and the second field plate in the substrate direction have an overlapping region. The first field plate and the third field plate are connected, or the first field plate and the third field plate are disconnected.

[0063] For example Figure 2a As shown, metal deposition and etching are performed on the gate dielectric and the first field plate dielectric to simultaneously form the gate 111, the first field plate 1131, and the third field plate 1133, with the first field plate 1131 and the third field plate 1133 interconnected. In other embodiments, such as Figure 3 As shown, the first field plate 1131 and the third field plate 1133 can be disconnected, allowing for more flexible connection of the independent third field plate 1133 to the source 110 or the gate 111 via subsequent metal interconnect processes. The third field plate 1133 and the second field plate 1132 have an overlapping region when projected onto the substrate 10.

[0064] (2) When forming the fourth layer of the field plate:

[0065] A third dielectric layer is deposited, and metal deposition and etching are performed on the third dielectric layer to form a fourth field plate. The fourth field plate is on top of the third field plate, and the projections of the fourth field plate and the third field plate in the substrate direction have an overlapping area.

[0066] For example Figure 4 As shown, after the third field plate 1133 is formed, a third dielectric layer 15 can be deposited, and metal deposition and metal etching can be performed on the third dielectric layer 15 to form a fourth field plate 1134. The fourth field plate 1134 and the third field plate 1133 have an overlapping region in the projection of the third field plate 1133 in the direction of the substrate 10.

[0067] It can be seen that in the process of manufacturing the semiconductor device with the near-gate field plate, the formation of the second layer field plate, the source and the drain in the semiconductor device is concentrated in the same step, so that the formed source, drain and second layer field plate are on the same layer, and the formation of the gate and the first layer field plate and even the third layer field plate is concentrated in the same step, so that the manufacturing steps of the semiconductor device with the near-gate field plate can be simplified, and thus the implementation cost and time of the field plate in the semiconductor device are simplified.

[0068] In addition, it should be noted that the semiconductor device described in the above Figure 2a 、 Figure 3 and Figure 4 is mainly that the first barrier layer 132 is included in the base dielectric layer 13 deposited on the basis of the first dielectric layer 12 in the process of manufacturing the semiconductor device, and in other specific embodiments, a plurality of barrier layers can be included in the base dielectric layer 13, and here two barrier layers are taken as an example for description, specifically:

[0069] When the above step 101 is performed, the base dielectric layer deposited on the first dielectric layer includes the first sub-dielectric layer 131, the first barrier layer 132, the second sub-dielectric layer 133, the second barrier layer 134 and the third sub-dielectric layer 135 arranged in turn from top to bottom.

[0070] For example Figure 5a As shown in the figure, in the present embodiment, the first dielectric layer 12 (the part filled with diagonal lines in the figure) and the base dielectric layer 13 are deposited on the epitaxial layer 11 of the substrate 10 in turn, and the base dielectric layer 13 includes the first sub-dielectric layer 131, the second sub-dielectric layer 133 and the third sub-dielectric layer 135, the first barrier layer 132 sandwiched between the first sub-dielectric layer 131 and the second sub-dielectric layer 133, and the second barrier layer 134 sandwiched between the second sub-dielectric layer 133 and the third sub-dielectric layer 135.

[0071] Further, when the above step 102 is performed, when the source and the second layer field plate of the semiconductor device are formed, the reserved positions of the gate and the two first layer field plates need to be reserved between the source and the second layer field plate.

[0072] Specifically, for example Figure 5aAs shown, when the metal is deposited, a metal layer can be deposited on the source electrode dielectric, and then the metal layer is etched to form the source electrode 110, the drain electrode 112 and the second layer field plate 1132, leaving the reserved positions of the gate and the two first layer field plates between the source electrode 110 and the second layer field plate 1132, and leaving the positions of the other multi-layer field plates (such as the third layer field plate 1133 and the fourth layer field plate 1134, etc.) between the drain electrode 112 and the second layer field plate 1132. In this way, the formation of the source electrode 110, the drain electrode 112 and the second layer field plate 1132 is concentrated into the same step, simplifying the steps of arranging the various parts on the epitaxial layer 11, and finally forming the source electrode 110, the drain electrode 112 and the second layer field plate 1132 on the same layer.

[0073] Further, when the above step 103 is performed, the gate dielectric, the upper first layer field plate dielectric (upper first layer field plate region) and the lower first layer field plate dielectric (lower first layer field plate region) are formed.

[0074] For example Figure 5a As shown, after the source electrode 110, the drain electrode 112 and the second layer field plate 1132 are formed, the second dielectric layer 14 can be deposited, and then dielectric etching is performed in the reserved positions between the source electrode 110 and the second layer field plate 1132 to form the gate dielectric, the upper first layer field plate dielectric and the lower first layer field plate dielectric. Specifically, when forming the upper first layer field plate dielectric, the second dielectric layer 14 needs to be etched through on both sides of the position of the lower first layer field plate dielectric and etched through the barrier layer 134 in the base dielectric layer 13, i.e. etching through the dielectric layer 135 and the barrier layer 134 from top to bottom in the base dielectric layer 13, to form the upper first layer field plate dielectric; when forming the lower first layer field plate dielectric, the second dielectric layer 14 needs to be etched through on both sides of the position of the gate dielectric and etched through the barrier layer 132 in the base dielectric layer 13, i.e. etching through the dielectric layer 135, 133 and the barrier layer 134 and 132 from top to bottom in the base dielectric layer 13, to form the lower first layer field plate dielectric; and when forming the gate dielectric, the second dielectric layer 14 and the base dielectric layer 13 need to be etched at the position of the gate dielectric, and the first dielectric layer 12 is exposed to form the gate dielectric.

[0075] Among them, the second dielectric layer 14, the dielectric layer 135 and the barrier layer 134 corresponding to the upper first layer field plate dielectric, the lower first layer field plate dielectric and the gate dielectric can be etched at the same time; the dielectric layer 133 and the barrier layer 132 corresponding to the lower first layer field plate dielectric and the gate dielectric can be etched at the same time.

[0076] In this way, a certain depth difference is formed between the gate dielectric, the upper first layer field plate dielectric and the lower first layer field plate dielectric.

[0077] Finally, when the above step 104 is performed, the gate and the two first layer field plates of the semiconductor device are formed.

[0078] Further, when metal deposition and metal etching are performed on the second dielectric layer 14, a third layer field plate can also be formed, the third layer field plate is above the second layer field plate, and the projection of the third layer field plate and the second layer field plate in the direction of the substrate has an overlapping area, wherein the first layer field plate and the third layer field plate are connected, or the first layer field plate and the third layer field plate are disconnected.

[0079] For example Figure 5a As shown, metal deposition and metal etching are performed on the gate dielectric, the upper first layer field plate dielectric, the lower first layer field plate dielectric, and the second dielectric layer, the gate 111, the two first layer field plates 1131 and the third layer field plate 1133 can be formed at the same time, and the first layer field plate 1131 and the third layer field plate 1133 are connected. Figure 5b As shown, the first layer field plate 1131 and the third layer field plate 1133 can be disconnected, so that the third layer field plate 1133 of this layer can be connected to the source 110 or the gate 111 through subsequent metal interconnection processes more flexibly.

[0080] An embodiment of the utility model provides another semiconductor device with near gate field plate, which includes but is not limited to MIS-HEMT device, P-GaN HEMT device, SBD-Gate HEMT, etc., and these semiconductor devices can be various semiconductor materials, such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO) and other semiconductor materials.

[0081] The semiconductor device of the embodiment includes a substrate, an epitaxial layer, and a first dielectric layer, a base dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a third dielectric layer and a third metal layer arranged in sequence on the epitaxial layer.

[0082] The epitaxial layer is arranged on the substrate, the first dielectric layer and the base dielectric layer are arranged on the epitaxial layer, the base dielectric layer is provided with the source metal hole and the drain metal hole penetrating through the first dielectric layer and the base dielectric layer, the first metal layer is arranged on the base dielectric layer to form the source on the source metal hole, the drain on the drain metal hole and the second layer field plate on the base dielectric layer, the second dielectric layer is arranged on the first metal layer, the second metal layer is arranged on the second dielectric layer to form the third layer field plate on the second dielectric layer, the third layer field plate is above the second layer field plate, and the projection of the third layer field plate and the second layer field plate in the direction of the substrate has an overlapping area, the third dielectric layer is arranged on the second metal layer, the third dielectric layer is provided with the gate metal hole penetrating through the third dielectric layer, the second dielectric layer and the base dielectric layer and at least one first layer field plate area penetrating through the third dielectric layer, the second dielectric layer and part of the base dielectric layer, and the third metal layer is arranged on the third dielectric layer to form the gate on the gate metal hole and the first layer field plate on the first layer field plate area.

[0083] The manufacturing method of the semiconductor device with the near-gate field plate in the embodiment is similar to the manufacturing method shown in the above Figure 1 The manufacturing method of the semiconductor device with the near-gate field plate in the embodiment is similar to the manufacturing method shown in the above

[0084] Specifically, as shown in the above Figure 6 The manufacturing method of the semiconductor device with the near-gate field plate in the embodiment is similar to the manufacturing method shown in the above

[0085] In step 201, the first dielectric layer and the base dielectric layer are deposited on the epitaxial layer of the substrate, the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, the first dielectric layer and the base dielectric layer are subjected to dielectric etching to form the source-drain dielectric.

[0086] Generally, in the manufacturing process of the semiconductor device, the various parts included in the semiconductor device, including the source, the gate, the drain, the field plate and the like, are arranged on the epitaxial layer of the substrate, and then the semiconductor device is obtained.

[0087] In the embodiment, when the semiconductor device is manufactured, first, the first dielectric layer and the base dielectric layer are deposited on the epitaxial layer of the substrate, further, when the semiconductor device includes the source and the drain, the first dielectric layer and the base dielectric layer are subjected to dielectric etching to form the source-drain dielectric, so that the source and the drain formed later are in the same layer.

[0088] As shown in the above Figure 7A cross-sectional view of a semiconductor device with a near-gate field plate is shown. The device includes a source 210, a gate 211, a drain 212, and a multi-layer (three layers are shown as an example) field plate near the gate 211 on an epitaxial layer 21 of a substrate 20. At least one first layer field plate 2131 of the multi-layer field plate is connected to the gate 211. A second layer field plate 2132 and a third layer field plate 2133 are on the same layer as the source 210 and the drain 212. A fourth layer field plate 2134 is connected to the first layer field plate 2131.

[0089] In this embodiment, a first dielectric layer 22 (the hatched part in the figure) and a base dielectric layer 23 (including a first sub-dielectric layer 233, a first barrier layer 232, and a second sub-dielectric layer 231) are deposited on the epitaxial layer 21 of the substrate 20 in sequence. Then, a via is formed by dielectric etching through the first dielectric layer 22 and the base dielectric layer 23 to expose the epitaxial layer 21 of the source region and the drain region.

[0090] In step 202, metal deposition and metal etching are performed on the source-drain dielectric to form the source, the drain, and the second layer field plate of the semiconductor device. The gate and at least one first layer field plate are reserved between the source and the second layer field plate.

[0091] Specifically, for example, Figure 7 As shown, a metal layer can be deposited on the source-drain dielectric during metal deposition, and then metal etching is performed on the metal layer. Specifically, photoresist can be provided at positions where metal is to be reserved, and then the metal layer is etched. The metal at the positions provided with photoresist is reserved, and the metal at other positions is etched. Finally, the photoresist is removed to form the source 210 (e.g., the ohmic metal of the source), the drain 212 (e.g., the ohmic metal of the drain), and the second layer field plate 2132. The gate and at least one first layer field plate are reserved between the source 210 and the second layer field plate 2132, and the positions of other multi-layer field plates (e.g., the third layer field plate 2133 and the fourth layer field plate 2134) are reserved between the drain 212 and the second layer field plate 2132.

[0092] In this way, the formation of the source 210, the drain 212, and the second layer field plate 2132 is concentrated in the same step, simplifying the steps of providing each part on the epitaxial layer 21. Finally, the source 210, the drain 212, and the second layer field plate 2132 are formed on the same layer.

[0093] In step 203, a second dielectric layer is deposited, and then metal deposition and metal etching are performed on the second dielectric layer to form a third layer field plate, the third layer field plate being above the second layer field plate, and the third layer field plate and the second layer field plate having an overlapping area in the projection of the substrate.

[0094] As shown in FIG. 2B, after the source 210, the drain 212 and the second layer field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third layer field plate 2133, the third layer field plate 2133 being above the second layer field plate 2132, and the third layer field plate 2133 and the second layer field plate 2132 having an overlapping area in the projection of the substrate 20. Figure 7

[0095] As shown in FIG. 2B, after the source 210, the drain 212 and the second layer field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third layer field plate 2133, the third layer field plate 2133 being above the second layer field plate 2132, and the third layer field plate 2133 and the second layer field plate 2132 having an overlapping area in the projection of the substrate 20.

[0096] As shown in FIG. 2B, after the source 210, the drain 212 and the second layer field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third layer field plate 2133, the third layer field plate 2133 being above the second layer field plate 2132, and the third layer field plate 2133 and the second layer field plate 2132 having an overlapping area in the projection of the substrate 20. Figure 7 As shown in FIG. 2B, after the source 210, the drain 212 and the second layer field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third layer field plate 2133, the third layer field plate 2133 being above the second layer field plate 2132, and the third layer field plate 2133 and the second layer field plate 2132 having an overlapping area in the projection of the substrate 20.

[0097] As shown in FIG. 2B, after the source 210, the drain 212 and the second layer field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third layer field plate 2133, the third layer field plate 2133 being above the second layer field plate 2132, and the third layer field plate 2133 and the second layer field plate 2132 having an overlapping area in the projection of the substrate 20.

[0098] It should be noted that the above steps 201 to 205 are mainly methods for setting three layer field plates in a semiconductor device, and in other embodiments, a fourth layer field plate or the like can also be set in the semiconductor device. When the fourth layer field plate is formed, the fourth layer field plate is formed on the third layer field plate, and the fourth layer field plate and the third layer field plate have an overlapping area in the projection of the substrate.

[0099] ​Metal deposition and etching are performed on the gate dielectric and at least one first field plate dielectric, and a fourth field plate is formed on top of the third field plate, wherein the fourth field plate and the third field plate have an overlapping region in the substrate direction, wherein one of the first field plates and the fourth field plate are connected, or one of the first field plates and the fourth field plate are disconnected.

[0100] For example Figure 7 As shown, metal deposition and etching are performed on the gate dielectric and the first field plate dielectric to simultaneously form the gate 211, the first field plate 2131, and the fourth field plate 2134, with the first field plate 2131 and the fourth field plate 2134 interconnected. In other embodiments, such as Figure 8 As shown, the first field plate 2131 and the fourth field plate 2134 can be disconnected, allowing for more flexible connection of the independent fourth field plate 2134 to the source 210 or the gate 211 through subsequent metal interconnect processes. The fourth field plate 2134 and the third field plate 2133 have an overlapping region when projected onto the substrate 20.

[0101] As can be seen, in the embodiments of this utility model, in the process of fabricating a semiconductor device with a near-gate field plate, the formation of the second field plate and the source in the semiconductor device is concentrated in the same step, so that the formed source and the second field plate are on the same layer. Furthermore, the formation of the gate and the first field plate, and even the fourth field plate, are concentrated in the same step, and the third field plate is formed before the gate is formed. This simplifies the fabrication steps of the semiconductor device with a near-gate field plate, thereby reducing the implementation cost and time of setting the field plate in the semiconductor device.

[0102] Furthermore, the method for fabricating the semiconductor device in this embodiment is the same as described above. Figure 1 Compared to the method for fabricating semiconductor devices shown above, the above-mentioned Figure 1 The method shown in the figure is used to fabricate semiconductor devices. Since only the first and second field layers are formed before the gate dielectric is formed, the dielectric etching depth required to form the gate dielectric is relatively low. It only needs to etch the dielectric to penetrate the second dielectric layer 14 and the base dielectric layer 13 and expose the first dielectric layer 22. This can reduce the dielectric etching time and better control the gate morphology. It is generally suitable for chip designs with small circuit board sizes.

[0103] Additionally, it should be noted that the above Figure 7 and Figure 8The semiconductor device described in the above embodiment includes a barrier layer 232 in the base dielectric layer 23 deposited on the first dielectric layer 22 in the process of manufacturing the semiconductor device, and in other embodiments, the base dielectric layer 23 can include multiple barrier layers, and in this embodiment, two barrier layers are described in detail, and specifically:

[0104] In the step 201, the base dielectric layer deposited on the first dielectric layer includes a first sub-dielectric layer 231, a first barrier layer 232, a second sub-dielectric layer 233, a second barrier layer 234, and a third sub-dielectric layer 235 arranged from top to bottom.

[0105] For example Figure 9a As shown in the above embodiment, the first dielectric layer 22 (the part filled with diagonal lines in the figure) and the base dielectric layer 23 are deposited on the epitaxial layer 21 of the substrate 20 in the above embodiment, and the base dielectric layer 23 includes the first sub-dielectric layer 231, the second sub-dielectric layer 233, and the third sub-dielectric layer 235, the first barrier layer 232 between the first sub-dielectric layer 231 and the second sub-dielectric layer 233, and the second barrier layer 234 between the second sub-dielectric layer 233 and the third sub-dielectric layer 235.

[0106] Further, in the step 202, when the source and the second layer field plate of the semiconductor device are formed, the reserved positions of the gate and the two first layer field plates need to be reserved between the source and the second layer field plate.

[0107] Specifically, for example Figure 9a As shown in the above embodiment, a metal layer can be deposited on the source dielectric during metal deposition, and then metal etching is performed on the metal layer to form the source 210, the drain 212, and the second layer field plate 2132, and the reserved positions of the gate and the two first layer field plates are reserved between the source 210 and the second layer field plate 2132, and the positions of other multi-layer field plates (such as the third layer field plate 2133 and the fourth layer field plate 2134, etc.) are reserved between the drain 212 and the second layer field plate 2132. In this way, the formation of the source 210, the drain 212, and the second layer field plate 2132 is concentrated in the same step, which simplifies the steps of arranging each part on the epitaxial layer 21, and finally the source 210, the drain 212, and the second layer field plate 2132 are formed on the same layer.

[0108] Further, in the step 204, the gate dielectric, the upper first layer field plate dielectric (the upper first layer field plate region), and the lower first layer field plate dielectric (the lower first layer field plate region) are formed.

[0109] As Figure 9aAs shown, after forming the source 210, the drain 212 and the second layer field plate 2132, and forming the third layer field plate 2133, the third dielectric layer 25 can be deposited, and then dielectric etching is performed on the reserved position between the source 210 and the second layer field plate 2132 to form the gate dielectric and the two first layer field plate dielectrics. Specifically, when forming the upper first layer field plate dielectric, the third dielectric layer 25, the second dielectric layer 24 and the barrier layer 234 in the base dielectric layer 23 need to be etched through from top to bottom, i.e., the upper first layer field plate dielectric is formed by etching through the dielectric layer 235 and the barrier layer 234 in the base dielectric layer 23 from top to bottom; when forming the lower first layer field plate dielectric, the third dielectric layer 25, the second dielectric layer 24 and the barrier layer 232 in the base dielectric layer 23 need to be etched through from top to bottom, i.e., the lower first layer field plate dielectric is formed by etching through the dielectric layer 235, 233 and the barrier layer 234 and 232 in the base dielectric layer 23 from top to bottom; and when forming the gate dielectric, the third dielectric layer 25, the second dielectric layer 24 and the base dielectric layer 23 need to be etched at the position of the gate dielectric, and the first dielectric layer 22 is exposed to form the gate dielectric.

[0110] The third dielectric layer 25, the second dielectric layer 24, the dielectric layer 235 and the barrier layer 234 corresponding to the upper first layer field plate dielectric, the lower first layer field plate dielectric and the gate dielectric can be etched at the same time; and the dielectric layer 233 and the barrier layer 232 corresponding to the lower first layer field plate dielectric and the gate dielectric can be etched at the same time.

[0111] In this way, a certain depth difference is formed between the gate dielectric, the lower first layer field plate dielectric and the upper first layer field plate dielectric.

[0112] Finally, when performing the above step 205, the gate and the two first layer field plates of the semiconductor device are formed.

[0113] Further, when performing metal deposition and metal etching on the third dielectric layer 25, a fourth layer field plate can also be formed, the fourth layer field plate is above the third layer field plate, and the projection of the fourth layer field plate and the third layer field plate in the substrate direction has an overlapping area, wherein the first layer field plate and the fourth layer field plate are connected, or the first layer field plate and the fourth layer field plate are disconnected.

[0114] For example Figure 9a As shown, after forming the gate dielectric, the upper first layer field plate dielectric, the lower first layer field plate dielectric and the third dielectric layer, metal deposition and metal etching can be performed to simultaneously form the gate 211, the two first layer field plates 2131 and the fourth layer field plate 2134, and the first layer field plate 2131 and the fourth layer field plate 1134 are connected. In other embodiments, as shown in FIG. 6, the first layer field plate 2131 and the fourth layer field plate 1134 are disconnected. Figure 9bAs shown, a first layer field plate 2131 and a fourth layer field plate 2134 can be disconnected, so that the layer independent fourth layer field plate 2134 can be connected to the source 210 or the gate 211 through subsequent metal interconnection processes more flexibly.

[0115] The above has carried out the detailed introduction to the semiconductor device with the near gate field plate provided by the embodiment of the utility model, the principle and implementation mode of the utility model have been described in this paper by applying specific examples, the above embodiment explanation is only for helping understanding the core idea of the utility model; simultaneously, for the general technical personnel of the field, according to the idea of the utility model, there will be changes in specific implementation mode and application range, and the above is described, the content of the specification should not be understood as the limitation of the utility model.

Claims

1. A semiconductor device having a near-gate field plate, characterized by, The semiconductor device comprises: a substrate; an epitaxial layer disposed on the substrate; a first dielectric layer and a base dielectric layer disposed on the epitaxial layer, the base dielectric layer being provided with a source metal hole and a drain metal hole penetrating through the first dielectric layer and the base dielectric layer; a first metal layer disposed on the base dielectric layer to form a source electrode on the source metal hole, a drain electrode on the drain metal hole, and a second layer field plate on the base dielectric layer; a second dielectric layer disposed on the first metal layer, the second dielectric layer being provided with a gate metal hole penetrating through the second dielectric layer and the base dielectric layer, and at least one first layer field plate region penetrating through the second dielectric layer and part of the base dielectric layer; and a second metal layer disposed on the second dielectric layer to form a gate electrode on the gate metal hole and a first layer field plate on the first layer field plate region. The base dielectric layer comprises a first sub-dielectric layer, a first barrier layer, and a second sub-dielectric layer disposed in sequence from top to bottom.

2. The semiconductor device having a near-gate field plate according to claim 1, wherein The second dielectric layer comprises a first layer field plate region penetrating through the second dielectric layer, the first sub-dielectric layer, and the first barrier layer and disposed on both sides of the gate metal hole. The base dielectric layer comprises a first sub-dielectric layer, a first barrier layer, a second sub-dielectric layer, a second barrier layer, and a third sub-dielectric layer disposed in sequence from top to bottom.

3. The semiconductor device with a near-gate field plate according to claim 1, wherein The second dielectric layer comprises: a lower first layer field plate region penetrating through the second dielectric layer, the first sub-dielectric layer, the first barrier layer, the second sub-dielectric layer, and the second barrier layer and disposed on both sides of the gate metal hole; and an upper first layer field plate region penetrating through the second dielectric layer, the first sub-dielectric layer, and the first barrier layer and disposed on both sides of the lower first layer field plate region. The second metal layer further comprises a third layer field plate, the third layer field plate being above the second layer field plate, and the projection of the third layer field plate and the second layer field plate in the substrate direction has an overlapping region.

4. The semiconductor device having a near-gate field plate according to any one of claims 1 to 3, wherein The first layer field plate is connected with the third layer field plate, or the first layer field plate is disconnected with the third layer field plate. The semiconductor device further comprises:

5. The semiconductor device having a near-gate field plate according to claim 4, wherein a third dielectric layer disposed on the second metal layer; and a third metal layer disposed on the third dielectric layer to form a fourth layer field plate on the third dielectric layer, the fourth layer field plate being above the third layer field plate, and the projection of the fourth layer field plate and the third layer field plate in the substrate direction has an overlapping region. The semiconductor device comprises:

6. A semiconductor device having a near-gate field plate, characterized by a substrate; an epitaxial layer disposed on the substrate; a first dielectric layer and a base dielectric layer disposed on the epitaxial layer, the base dielectric layer being provided with a source metal hole and a drain metal hole penetrating through the first dielectric layer and the base dielectric layer; a first metal layer disposed on the base dielectric layer to form a source electrode on the source metal hole, a drain electrode on the drain metal hole, and a second layer field plate on the base dielectric layer; a second dielectric layer disposed on the first metal layer; ​ a second metal layer disposed on the second dielectric layer to form a third layer field plate on the second dielectric layer, the third layer field plate being above the second layer field plate, and a projection of the third layer field plate and the second layer field plate in the substrate direction having an overlapping area; a third dielectric layer disposed on the second metal layer, the third dielectric layer being provided with a gate metal hole penetrating through the third dielectric layer, the second dielectric layer and the base dielectric layer, and at least one first layer field plate region penetrating through the third dielectric layer, the second dielectric layer and part of the base dielectric layer; and a third metal layer disposed on the third dielectric layer to form a gate on the gate metal hole and a first layer field plate on the first layer field plate region.

7. The semiconductor device having a near-gate field plate according to claim 6, wherein The base dielectric layer comprises a first sub-dielectric layer, a first barrier layer and a second sub-dielectric layer disposed in sequence from top to bottom; The third dielectric layer comprises a first layer field plate region disposed on both sides of the gate metal hole and penetrating through the third dielectric layer, the second dielectric layer, the first sub-dielectric layer and the first barrier layer.

8. The semiconductor device with a near-gate field plate according to claim 6, wherein The base dielectric layer comprises a first sub-dielectric layer, a first barrier layer, a second sub-dielectric layer, a second barrier layer and a third sub-dielectric layer disposed in sequence from top to bottom; The third dielectric layer comprises: a lower first layer field plate region disposed on both sides of the gate metal hole and penetrating through the third dielectric layer, the second dielectric layer, the first sub-dielectric layer, the first barrier layer, the second sub-dielectric layer and the second barrier layer; and an upper first layer field plate region disposed on both sides of the lower first layer field plate region and penetrating through the third dielectric layer, the second dielectric layer, the first sub-dielectric layer and the first barrier layer.

9. The semiconductor device having a near-gate field plate according to any one of claims 6 to 8, wherein The third metal layer further comprises a fourth layer field plate, the fourth layer field plate being above the third layer field plate, and a projection of the fourth layer field plate and the third layer field plate in the substrate direction having an overlapping area; wherein the fourth layer field plate is connected with the first layer field plate, or the fourth layer field plate is disconnected with the first layer field plate.

10. The semiconductor device with a near-gate field plate according to claim 6, wherein The semiconductor device includes but is not limited to MIS-HEMT device, P-GaN HEMT device and SBD-Gate HEMT device; the material of the semiconductor device includes but is not limited to gallium nitride, silicon, silicon carbide, gallium arsenide and gallium oxide.

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