Semiconductor device

Abstract

A semiconductor device includes a first two-dimensional semiconductor layer over a substrate, a first source / drain contact structure in contact with a first region of the first two-dimensional semiconductor, and a second source / drain contact structure in contact with a second region of the first two-dimensional semiconductor layer, the second region of the first two-dimensional semiconductor layer being spaced apart from the first region. The first source / drain contact structure includes an antimony layer in contact with the first region of the first two-dimensional semiconductor layer, and a platinum layer over the antimony layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, and particularly, to semiconductor devices having two-dimensional materials and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials on a semiconductor substrate, and patterning the various material layers using lithography to form the circuit components and elements thereon.

[0003] The semiconductor industry has continued to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the individual components that are formed on a given area of a semiconductor substrate. SUMMARY

[0004] In some embodiments, a semiconductor device includes an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET). The NFET includes a first two-dimensional (2D) semiconductor layer and a plurality of first source / drain contact structures on opposite sides of the first 2D semiconductor layer. The PFET includes a second 2D semiconductor layer and a plurality of second source / drain contact structures on opposite sides of the second 2D semiconductor layer. Each of the plurality of first source / drain contact structures includes a first semimetal layer and a second semimetal layer over the first semimetal layer, and each of the plurality of second source / drain contact structures includes a third semimetal layer and a fourth semimetal layer over the third semimetal layer, wherein a thickness ratio of the first semimetal layer to the second semimetal layer in the NFET is greater than a thickness ratio of the third semimetal layer to the fourth semimetal layer in the PFET.

[0005] In some embodiments, a semiconductor device includes a first two-dimensional (2D) semiconductor layer, a first source / drain contact structure, and a second source / drain contact structure. The first 2D semiconductor layer is over a substrate. The first source / drain contact structure is in contact with a first region of the first 2D semiconductor layer. The second source / drain contact structure is in contact with a second region of the first 2D semiconductor layer. The second region is spaced apart from the first region of the first 2D semiconductor layer. The first source / drain contact structure includes a first antimony layer in contact with the first region of the first 2D semiconductor layer and a first platinum layer over the first antimony layer.

[0006] In some embodiments, a semiconductor device includes a dielectric layer over a substrate; a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer over the dielectric layer; a first antimony layer and a second antimony layer in contact with opposite sides of the first two-dimensional semiconductor layer; a third antimony layer and a fourth antimony layer in contact with opposite sides of the second two-dimensional semiconductor layer, wherein the third antimony layer has a thickness greater than a thickness of the first antimony layer; and a first platinum layer, a second platinum layer, a third platinum layer, and a fourth platinum layer over the first antimony layer, the second antimony layer, the third antimony layer, and the fourth antimony layer, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. It is also to be understood that the terminology used herein is for the purpose of describing specific aspects only and is not intended to be limiting.

[0008] FIG. 1A FIG. 1 illustrates a cross-sectional view of a two-dimensional semiconductor device according to some embodiments of the present disclosure;

[0009] FIG. 1B FIG. 2 illustrates a schematic diagram of a single layer of an example TMD according to some example embodiments;

[0010] FIG. 2 FIG. 3 is a plot illustrating Raman spectroscopy results under different conditions according to some embodiments of the present disclosure;

[0011] FIG. 3A FIG. 4 illustrates an example band diagram of a semimetal-semiconductor junction between WSe2 and pristine Sb according to some embodiments of the present disclosure;

[0012] FIG. 3B FIG. 5 illustrates an example band diagram of a semimetal-semiconductor junction between WSe2 and pristine Pt according to some embodiments of the present disclosure;

[0013] FIG. 4A FIG. 6 is a plot illustrating current-voltage (I-V) characteristics of a WSe2 channel FET according to some embodiments of the present disclosure;

[0014] FIG. 4B FIG. 7 is a plot illustrating on-current behavior of a WSe2 channel FET as a function of Sb to Pt thickness ratio according to some embodiments of the present disclosure;

[0015] FIG. 5 FIG. 8 illustrates a cross-sectional view of a two-dimensional semiconductor device according to some embodiments of the present disclosure;

[0016] FIG. 6is a graph showing NFET drain current improvement attributed to an n-type drain current improvement layer according to some embodiments of the present disclosure;

[0017] FIG. 7 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure;

[0018] FIG. 8 is a graph showing PFET drain current improvement attributed to a p-type drain current improvement layer according to some embodiments of the present disclosure;

[0019] FIG. 9 to FIG. 28A is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure;

[0020] FIG. 28B is an example top view of a structure in FIG. 28A according to some embodiments of the present disclosure;

[0021] FIG. 29 to FIG. 33 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device according to some embodiments of the present disclosure;

[0022] FIG. 34 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0023] FIG. 35 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0024] FIG. 36 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0025] FIG. 37 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0026] FIG. 38 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0027] FIG. 39 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure;

[0028] FIG. 40 is an illustrative cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure.

[0029]

Notation

[0030] 102: substrate

[0031] 104: dielectric layer

[0032] 106: two-dimensional semiconductor layer

[0033] 106C: 2D channel region

[0034] 107M: transition metal atom

[0035] 107X: chalcogen atom

[0036] 108: source / drain contact structure

[0037] 110: first semimetal layer

[0038] 112: second semimetal layer 113:

[0040] 114N: n-type drain current improvement layer

[0041] 114P: p-type drain current improvement layer

[0042] 600A-B: gate structure

[0043] 600N: N well region

[0044] 600P: P well region

[0045] 602: gate dielectric

[0046] 604: gate electrode

[0047] 605: isolation structure

[0048] 610: substrate

[0049] 612: gate spacer

[0050] 620N: n-type source / drain region

[0051] 620P: p-type source region

[0052] 625: cap layer

[0053] 630: CESL

[0054] 640: ILD layer

[0055] 650: source / drain contact structure

[0056] 652: barrier layer

[0057] 654: contact plug

[0058] 700: ESL

[0059] 705: IMD layer

[0060] 710: liner layer

[0061] 712: fill metal layer

[0062] 714: metal wire

[0063] 716: ESL

[0064] 718: IMD layer

[0065] 720: back gate structure

[0066] 722: high-k dielectric layer

[0067] 722g: gate dielectric region

[0068] 724: ILD layer

[0069] 726: transition metal layer

[0070] 728: TMD layer

[0071] 730: patterned mask layer

[0072] 734a-c: first half metal layer

[0073] 736: patterned mask layer

[0074] 738a-b: first half metal layer 742a-d: second half metal layer

[0075] 750a-b: second half metal layer

[0076] 752: patterned mask layer

[0077] 754a-b: first half metal layer

[0078] 756: patterned mask layer

[0079] 760N: n-type drain current improvement layer

[0080] 760P: p-type drain current improvement layer

[0081] 762-764: back gate structure

[0082] 766-768: front gate structure

[0083] 800N: NFET

[0084] 800P: PFET

[0085] BG: back gate

[0086] 01: trench

[0087] 02: opening

[0088] O3: Source / drain contact structure openings DETAILED DESCRIPTION

[0089] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present disclosure. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features do not directly contact. Additionally, the present disclosure can refer to a number of functional units and / or components. Such units can be implemented by hardware, software, or combinations thereof, and can be referred to herein as units, components, or modules. Unless otherwise specified, any functional unit or component can be implemented by one or more hardware units, one or more software units, or one or more hardware units in combination with one or more software units. For example, any of the units described herein can be implemented by one or more circuits, and / or one or more processors of one or more devices. The term "processor" refers to one or more devices that are capable of executing a program or machine executable instruction. A processor can include any suitable processing unit, such as a central processing unit (CPU), processor core, or the like. The term "software" refers to machine-executable instructions or a set of instructions that are executed by one or more processors. The software may

[0090] Furthermore, to facilitate description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for describing the inventive concept, including the orientation of one element or features relative to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, "about", "approximately", "substantially", or "essentially" generally mean within 20%, or within 10%, or within 5% of a given value or range. Numerical amounts given herein are approximations, which vary by at least 20%, or at least 10%, or at least 5% of the given value or range. However, those skilled in the art will recognize that the values or ranges given throughout this specification are only examples within the scope of the disclosure, and that the actual values or ranges can vary as such technology evolves.

[0091] As transistor process technology advances, the size of transistors shrinks, thus the number of transistors per unit area of an integrated circuit increases accordingly. However, off-current increases significantly as the channel length of a transistor is further reduced, i.e., short channel effect. This effect is a major challenge to further increasing the density of transistors. Reducing the thickness of the channel is one way to suppress the short channel effect. Two-dimensional (2D) semiconductors can be a candidate for ultra-thin semiconductor channel material to suppress the short channel effect. One advantageous feature of 2D semiconductor material is a high electron mobility value, which is in the range of 50-1000 cm2 / Vs, which is much higher than that of bulk silicon (1-15 cm2 / Vs). Another advantageous feature of 2D semiconductor material is a high on-off ratio, which is in the range of 105-109, which is much higher than that of bulk silicon (103-104). 2V-sec or even higher. It should be appreciated that when silicon is formed in a low thickness comparable to the thickness of the two-dimensional semiconductor film (e.g., about 3 nm or lower), its mobility can decrease drastically. Therefore, the scaling down of the two-dimensional semiconductor channel thickness has a less impact on carrier mobility compared to silicon, and in turn, a channel thickness of only a few nanometers (e.g., less than 3 nm) can achieve satisfactory channel mobility. For example, tungsten diselenide (WSe2) can be used as a two-dimensional (2D) semiconductor channel material, with a palladium (Pd) contact structure disposed on the WSe2 layer to serve as a source / drain electrode. However, it has been observed that the junction formed between Pd and WSe2 is susceptible to a significant Fermi level pinning (FLP) effect, which is a phenomenon where the Fermi level becomes "pinned" to a particular energy level at the junction. This issue adversely affects the performance of the device. In addition, the junction formed between Pd and WSe2 exhibits unsatisfactory band alignment for hole conduction, resulting in increased Schottky barrier, increased contact resistance, and reduced current transport capability. Therefore, this structure is not suitable for implementation in a p-type transistor.

[0092] In various embodiments, the present disclosure provides an improved source / drain contact structure that includes an antimony (Sb) layer in contact with a WSe2 layer and a platinum (Pt) layer over the Sb layer. The Sb-Pt contact structure alleviates the Fermi level pinning issue commonly seen when using a Pd contact structure in a two-dimensional semiconductor device. In addition, by varying the thickness ratio between the Sb and Pt layers, the effective work function of the Sb-Pt contact structure is tunable. This unique feature advantageously improves the performance of p-type and n-type field effect transistors (p-FET and n-FET).

[0093] FIG. 1AA cross-sectional view of a two-dimensional semiconductor device according to some embodiments of the present disclosure is illustrated. The two-dimensional semiconductor device includes a substrate 102. In some embodiments, the substrate 102 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 102 can be a wafer, e.g., a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, such as a silicon or glass substrate. Other substrates, such as a multilayer or graded substrate, can also be used. In some embodiments, the semiconductor material of the substrate 102 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; combinations thereof; or the like.

[0094] The two-dimensional semiconductor device further includes a dielectric layer 104 formed over the substrate 102. In some embodiments, the dielectric can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials can include silicon nitride (SiN x ), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), high-k dielectrics, or the like. Other insulating materials formed by any acceptable process can be used. In certain embodiments, the dielectric layer 104 is a nitride-based material, such as silicon nitride (SiN x ).

[0095] The two-dimensional semiconductor device further includes a two-dimensional semiconductor layer 106 formed over the dielectric layer 104. The two-dimensional semiconductor material of the two-dimensional semiconductor layer 106 is typically only a few layers thick and exists in a stacked form with strong bonding layers having weak interlayer van der Waals attraction, allowing these layers to physically or chemically exfoliate into individually atomically thin layers. Two-dimensional semiconductor materials are suitable candidates for channel, source, drain materials of transistors. Examples of two-dimensional semiconductor materials include transition metal dichalcogenides (TMDs), graphene, layered III-V chalcogenides, graphene, hexagonal boron nitride (h-BN), black phosphorous, or the like. The two-dimensional semiconductor can include one or more layers, and in some embodiments, can have a thickness in the range of about 0.5-100 nm. One advantageous feature of a few-layer thick two-dimensional semiconductor is a high electron mobility value, which is in the range of about 50-1000 cm 2 / V-sec or even higher. It should be appreciated that when bulk silicon is cut into a low thickness comparable to the thickness of a 2D material film (e.g., about 3 nm), its mobility can decrease dramatically.

[0096] In some embodiments, the two-dimensional semiconductor layer 106 is a transition metal dichalcogenide (TMD) material with a chemical formula of MX2, where M is a transition metal element such as titanium, vanadium, cobalt, nickel, zirconium, molybdenum, technetium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, platinum, and X is a chalcogen element such as sulfur, selenium, or tellurium. Examples of suitable dichalcogenide materials for the two-dimensional semiconductor layer 106 include WSe2, WS2, MoS2, MoSe2, MoTe2, WTe2, the like, or combinations thereof. However, any suitable transition metal dichalcogenide material can be used instead. Once formed, the transition metal chalcogenide material exhibits a layered structure with multiple two-dimensional layers, generally in the form of X-M-X, with chalcogen atoms located between two planes separated by metal atoms.

[0097] The two-dimensional semiconductor layer 106 can be a single layer or can include several single layers. FIG. 1B A schematic diagram of a single layer 107 of an example TMD is illustrated in accordance with some example embodiments. In FIG. 1B A monolayer of TMD material includes transition metal atoms 107M and chalcogen atoms 107X. The transition metal atoms 107M can form a layer in the middle region of the monolayer of TMD material, and the chalcogen atoms 107X can form a first layer over the layer of transition metal atoms 107M and a second layer under the layer of transition metal atoms 107M. The transition metal atoms 107M can be W atoms or Mo atoms, and the chalcogen atoms 107X can be Se atoms, S atoms, or Te atoms. In FIG. 1BIn an example of a TMD, each of the transition metal atoms 107M is bonded (e.g., by a covalent bond) to six chalcogen atoms 107X, each of the chalcogen atoms 107X is bonded (e.g., by a covalent bond) to three transition metal atoms 107M. Throughout the specification, the interbonding layer consisting of one layer of transition metal atoms 107M and two layers of chalcogen atoms 107X is referred to as a monolayer 107 of a TMD.

[0098] In some embodiments, the two-dimensional semiconductor layer 106 is formed by depositing a transition metal layer (e.g., a tungsten (W) layer) over the dielectric layer 104, followed by selenization of the transition metal layer into a transition metal dichalcogenide (TMD) layer 106. In some other embodiments, the two-dimensional semiconductor layer 106 is formed by an inductively-coupled-plasma (ICP) CVD process using a transition metal-containing precursor (e.g., WF6) and a selenium-containing precursor (e.g., H2Se). In some embodiments, the two-dimensional semiconductor layer 106 can be deposited to have a thickness ranging from about 1 nm to about 10 nm, depending on the total number of monolayers. Process conditions are controlled to achieve the desired total number of monolayers 107 in the two-dimensional semiconductor layer 106.

[0099] In some other embodiments, the two-dimensional semiconductor layer 106 is formed using a lift-off and transfer method. For example, a two-dimensional semiconductor layer can be grown on another crystalline substrate having a desired crystal direction by using a suitable deposition technique, followed by transferring the two-dimensional semiconductor layer 106 onto the dielectric layer 104. For example, a two-dimensional semiconductor layer grown on a crystalline substrate can be covered with a protective film (e.g., PMMA) and a thermal release tape, then the two-dimensional semiconductor layer is lifted off from the crystalline substrate by mechanical or chemical means, followed by transferring onto the dielectric layer 104. Next, the thermal release tape can be removed by, for example, baking the thermal release tape so that the thermal release tape loses adhesion. Next, the protective film can be removed by, for example, etching or dissolving. After the protective film is removed, the two-dimensional semiconductor layer 106 remains on the dielectric layer 104 and is ready for subsequent processing for Sb-Pt contact structure formation.

[0100] The two-dimensional semiconductor device further includes multilayer source / drain contact structures 108 formed over the source / drain regions of the two-dimensional semiconductor layer 106. The source / drain contact structures 108 and the two-dimensional semiconductor layer 106 can collectively function as a field effect transistor (FET) that uses the 2D channel region 106C as the transistor channel. In some embodiments, the 2D channel region 106C laterally extends between the source / drain contact structures 108 and is controlled by a transistor gate, such as a back gate BG disposed under the dielectric layer 104. In some embodiments where the two-dimensional semiconductor layer 106 is WSe2, the resulting transistor can be referred to as a WSe2 channel FET. In some embodiments, each multilayer contact structure 108 includes a first semimetal layer 110 in contact with the source / drain regions of the two-dimensional semiconductor layer 106, and a second semimetal layer 112 over the first semimetal layer 110. In some embodiments, the material used for the first semimetal layer 110 is selected to be antimony (Sb), while the material for the overlying second semimetal layer 112 is platinum (Pt). In semimetals, the valence and conduction bands slightly overlap or touch at some point, resulting in a zero or near-zero band gap. Both electrons and holes exist at the Fermi energy level of the semimetal, and the dominant charge carrier depends on the band structure at the semimetal-semiconductor interface between the semimetal and the two-dimensional semiconductor layer 106.

[0101] The Sb layer 110 performs a dual function: first, it serves as an interlayer or buffer layer between the high work function Pt layer 112 and the two-dimensional semiconductor layer 106, effectively reducing potential damage to the two-dimensional semiconductor layer 106; second, it weakens the interaction between the two-dimensional semiconductor and the adjoining metal, thereby mitigating issues related to Fermi level pinning (FLP), which are prevalent in two-dimensional semiconductor interfaces that employ palladium (Pd) contact structures.

[0102] A source of defects in the use of Pd contact structures in two-dimensional semiconductor devices stems from the strong Fermi level pinning effect, which is mainly caused by defect-induced gap states (DIGS) and metal-induced gap states (MIGS). These phenomena collectively impair the tunability of the effective work function at the metal-semiconductor interface. By introducing the Sb buffer layer 110, the present disclosure overcomes this limitation. Compared to Pd deposition, the Sb buffer layer 110 can be deposited under relatively milder conditions, particularly at lower temperatures, which minimizes the thermal stress and lattice damage to the two-dimensional semiconductor layer 106, thereby reducing defects at the interface between the Sb buffer region 110 and the two-dimensional semiconductor layer 106, which in turn at least reduces defect-induced gap states (DIGS). The relatively lower sublimation point of Sb compared to Pd ensures minimal thermal disturbance by the evaporation deposition technique, thereby preserving the integrity of the two-dimensional semiconductor layer 106.

[0103] FIG. 2 is a plot illustrating the results of Raman spectroscopy analysis under different conditions. These Raman spectra were obtained by Raman spectroscopy measurements on structures with varying compositions. In condition #1, a structure comprising a WSe2 layer formed on a SiN x layer. In condition #2, a Raman spectroscopy measurement was performed on a structure comprising a bilayer stack formed on a SiN x layer, where the bilayer stack comprises a WSe2 layer and a Sb layer formed on the WSe2 layer. In condition #3, a Raman spectroscopy measurement was performed on a structure comprising a bilayer stack formed on a SiN x layer, where the bilayer stack comprises a WSe2 layer and a Pd layer formed on the WSe2 layer. In condition #4, a Raman spectroscopy measurement was performed on a structure comprising a trilayer stack formed on a SiN x layer, where the trilayer stack comprises a WSe2 layer, a polystyrene and poly(methyl methacrylate) (PMMA) layer formed on the WSe2 layer, and a Pd layer formed on the PMMA layer.

[0104] As FIG. 2A comparative analysis of the Raman shift curves shown in FIG. 6 reveals the following insights. Comparing Condition #2 to Condition #1, it can be observed that the bilayer stack of Sb / WSe2 has the same or similar Raman shift curves as the original WSe2. Comparing Condition #3 to Condition #1, it can be observed that the bilayer stack of Pd / WSe2 has significantly different Raman shift curves than the original WSe2. Comparing Condition #4 to Condition #1, it can be observed that the trilayer stack of Pd / PMMA / WSe2 has the same or similar Raman shift curves as the original WSe2. Based on these observations, it can be concluded that forming Sb directly on WSe2 reduces lattice damage to WSe2 compared to the lattice damage caused by forming Pd directly on WSe2.

[0105] FIG. 3A An example band diagram of a semimetal-semiconductor junction between WSe2 and pristine Sb is shown in accordance with some embodiments of the present disclosure. In FIG. 3A , Ec represents the conduction band edge of WSe2, Ev represents the valence band edge of WSe2, E F1 represents the Fermi energy level within Sb. The work function (Φ1) can be the minimum thermodynamic work (energy) required to remove an electron from a solid to a point outside the solid surface in a vacuum. The vacuum level (E0) represents the minimum energy required for an electron to be completely released from a semimetal or semiconductor. As shown in FIG. 3A , due to the semimetallic nature of Sb, the Fermi energy level E F1 is located at the point where the valence band and conduction band of Sb touch or exhibit a slight overlap, also known as Dirac points. In some embodiments, Sb has a work function Φ1 of about 4.4 eV ± 0.3 eV, such as about 4.4 eV. Thus, the work function Φ1 allows the Fermi energy level E F1 to be closer to the conduction band Ec than to the valence band Ev, which facilitates electrons to act as the main carriers flowing through the channel region of WSe2, allowing the WSe2 channel FET to operate as an n-type field effect transistor (NFET).

[0106] FIG. 3B An example band diagram of a semimetal-semiconductor junction between WSe2 and pristine Pt is shown in accordance with some embodiments of the present disclosure. In FIG. 3B , Ec represents the conduction band edge of WSe2, Ev represents the valence band edge of WSe2, E F2 represents the Fermi energy level within Pt. The work function (Φ2) can be the minimum thermodynamic work (energy) required to remove an electron from a solid to a point outside the solid surface in a vacuum. The vacuum level (E0) represents the minimum energy required for an electron to be completely released from a semimetal or semiconductor. As shown in FIG. 3B , due to the semimetallic nature of Pt, the Fermi energy level EF2 at a point where the valence band of Pt slightly overlaps with the conduction band. In some embodiments, Pt has a work function Φ2of about 5.6 eV ± 0.3 eV, such as about 5.6 eV. Thus, the work function Φ2allows the Fermi level E F2 closer to the valence band Evthan to the conduction band Ec, resulting in a hole-dominant carrier transport, allowing the WSe2channel FET to operate as a p-type field effect transistor (PFET).

[0107] In some embodiments, the multi-layer source / drain contact structure 108 each comprises a stack of Sb and Pt. These materials exhibit work functions of about 4.4 eV and 5.6 eV, respectively, allowing an effective work function in the range of about 4.4 eV to 5.6 eV. By adjusting the thickness ratio of Sb to Pt, it is possible to adjust the effective work function of the multi-layer source / drain contact structure 108, and thus to change the carrier polarity of the WSe2channel FET. For example, if the thickness ratio of Sb to Pt exceeds 100%, the resulting WSe2channel FET is primarily used as an NFET; if the thickness ratio of Sb to Pt is less than 100%, the resulting WSe2channel FET can primarily operate as a PFET.

[0108] FIG. 4A and FIG. 4B is a plot illustrating experimental results of device performance of various WSe2channel FETs with different thickness ratios of Sb to Pt, showing the relationship between drain current / on-state current improvement and the thickness ratio of Sb to Pt. FIG. 4A depicts current-voltage (I-V) characteristics of a WSe2channel FET according to some embodiments of the present disclosure. In FIG. 4A , the drain current (I d ) is shown on the vertical axis, and the gate voltage (V G) are shown on the horizontal axis. I-V curve C41 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure having a Sb to Pt thickness ratio of about 10:25 (e.g., a source / drain contact structure having 10 nm thick Sb and 25 nm thick Pt). I-V curve C42 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure having a Sb to Pt thickness ratio of about 10:12 (e.g., a source / drain contact structure having 10 nm thick Sb and 12 nm thick Pt). I-V curve C43 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure having a Sb to Pt thickness ratio of about 20:12 (e.g., a source / drain contact structure having 20 nm thick Sb and 12 nm thick Pt). I-V curve C44 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure having a Sb to Pt thickness ratio of about 30:12 (e.g., a source / drain contact structure having 30 nm thick Sb and 12 nm thick Pt). I-V curve C45 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure formed of 30 nm thick Pd.

[0109] As shown in FIG. 4B, I-V curve C44 exhibits superior drain current behavior to the other I-V curves under positive gate voltage conditions, while I-V curve C42 exhibits superior drain current behavior to the other I-V curves under negative gate voltage conditions. These observations indicate that the resulting WSe2 channel FETs have optimized NFET performance when the source / drain contact structure has a Sb-Pt thickness ratio of about 30:12 (e.g., a source / drain contact structure having 30 nm thick Sb and 12 nm thick Pt), and optimized PFET performance when the source / drain contact structure has a Sb-Pt thickness ratio of about 10:12 (e.g., a source / drain contact structure having 10 nm thick Sb and 12 nm thick Pt). FIG. 4A As shown in FIG. 4B, I-V curve C44 exhibits superior drain current behavior to the other I-V curves under positive gate voltage conditions, while I-V curve C42 exhibits superior drain current behavior to the other I-V curves under negative gate voltage conditions. These observations indicate that the resulting WSe2 channel FETs have optimized NFET performance when the source / drain contact structure has a Sb-Pt thickness ratio of about 30:12 (e.g., a source / drain contact structure having 30 nm thick Sb and 12 nm thick Pt), and optimized PFET performance when the source / drain contact structure has a Sb-Pt thickness ratio of about 10:12 (e.g., a source / drain contact structure having 10 nm thick Sb and 12 nm thick Pt).

[0110] FIG. 4B FIG. 4C depicts the on-current behavior of WSe2 channel FETs as a function of Sb to Pt thickness ratio, according to some embodiments of the present disclosure. Plot C46 represents the NFET on-current levels when WSe2 channel FETs having different Sb to Pt thickness ratios are operated in NFET mode (i.e., under positive gate voltage), and plot C47 represents the PFET on-current levels when WSe2 channel FETs having different Sb to Pt thickness ratios are operated in PFET mode (i.e., under negative gate voltage). As shown in FIG. 4C, the WSe2 channel FETs having a Sb to Pt thickness ratio of about 30:12 (e.g., a source / drain contact structure having 30 nm thick Sb and 12 nm thick Pt) exhibit the highest on-current levels in both NFET and PFET modes. FIG. 4BAs shown, the maximum NFET on-state current is achieved when the Sb to Pt thickness ratio exceeds 200% (e.g., about 30:12); the maximum PFET on-state current is achieved when the Sb to Pt thickness ratio is in the range of about 75% to about 100% (e.g., about 10:12).

[0111] FIG. 5 A cross-sectional view of a two-dimensional semiconductor device according to some embodiments of the present disclosure is shown. FIG. 5 The structure shown is similar to FIG. 1A The structure is different in that FIG. 5 The structure further includes an n-type drain current improvement layer 114N (also referred to as a capping layer in this context) covering the source / drain contact structure 108 and the 2D channel region 106C. When the WSe2 channel FET operates in NFET mode (i.e., under positive gate voltage conditions), the n-type drain current improvement layer 114N has a material suitable for increasing the drain current. In some embodiments, the n-type drain current improvement layer 114N is silicon oxynitride (SiON). x ) layer, hafnium oxide (HfO) x ) layer, aluminum oxide (AlO) x ) layer, titanium oxide (TiO) x The n-type drain current improvement layer 114N, or a combination thereof, is deposited over the source / drain contact structure 108 and the 2D channel region 106C using suitable deposition techniques such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the n-type drain current improvement layer 114N has a thickness in the range of about 1 nm to 50 nm.

[0112] like FIG. 5 As shown, the source / drain contact structure 108 for the NFET has a first half-metal layer 110 that is thicker than the second half-metal layer 112. Therefore, the interface formed between the n-type drain current improvement layer 114N and the sidewall of the first half-metal layer 110 is larger than the interface formed with the sidewall of the second half-metal layer 112. For example, the area ratio of the sidewall interface between the first half-metal layer 110 and the n-type drain current improvement layer 114N to the sidewall interface between the second half-metal layer 112 and the n-type drain current improvement layer 114N is approximately 30:12.

[0113] FIG. 6 This is a graph showing the improvement in NFET drain current caused by the n-type drain current improvement layer 114N according to some embodiments of this disclosure. In detail, FIG. 6Experimental results illustrating the current-voltage (IV) characteristics of different WSe2 channel FETs are presented, where the differences between these WSe2 channel FETs lie in the presence of the n-type drain current improvement layer 114N. Curve C61 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure with a Sb:Pt thickness ratio of approximately 30:12 (e.g., a source / drain contact structure with 30 nm thick Sb and 12 nm thick Pt) but without the n-type drain current improvement layer 114N. Curve C62 represents the current-voltage characteristics of a WSe2 channel FET including the n-type drain current improvement layer 114N (e.g., SiON). x The current-voltage characteristics of a WSe2 channel FET with a source / drain contact structure having an Sb:Pt thickness ratio of approximately 30:12 (e.g., a source / drain contact structure with a 30 nm thick Sb and a 12 nm thick Pt). For example... FIG. 6 As shown, under positive gate voltage conditions, the drain current behavior of IV curve C62 is superior to that of IV curve C61. These data confirm that the integration of the n-type drain current improvement layer 114N covering the source / drain contact structure 108 and the 2D channel region 106C can increase the drain current when the WSe2 channel FET operates in NFET mode. Furthermore, it can be observed that the drain current of the n-type WSe2 channel FET with an Sb-Pt contact structure covered by the n-type drain current improvement layer 114N is greater than that of the n-type WSe2 channel field-effect transistor with other metal contact structures (e.g., Ag contact structure, Au contact structure, In contact structure, Ni contact structure, Ti contact structure, or combinations thereof). In some embodiments, the WSe2 channel FET with the n-type drain current improvement layer 114N has a drain current of approximately 7.5 cm⁻¹. 2 / vs to approximately 8.2cm 2 / vs range (e.g., approximately 7.8cm) 2 The effective mobility (μeff) of / vs, and the contact resistance (R) in the range of about 1.5kΩ·μm to about 2.0kΩ·μm (e.g., about 1.8kΩ·μm). c ).

[0114] FIG. 7 A cross-sectional view of a two-dimensional semiconductor device according to some embodiments of the present disclosure is shown. FIG. 7 The structure shown is similar to FIG. 1A The structure is different in that FIG. 7The structure further includes a p-type drain current improvement layer 114P (also referred to as a capping layer) covering the source / drain contact structure 108 and the 2D channel region 106C. The p-type drain current improvement layer 114P has a material suitable for increasing the drain current when the WSe2 channel FET operates in PFET mode (i.e., under negative gate voltage conditions). In some embodiments, the p-type drain current improvement layer 114P is molybdenum oxide (MoO₂). x ) layer, nitrogen dioxide (NO2) layer, tungsten oxide (WO3) layer x An iodine (I2) layer, a combination thereof, or the like, is deposited over the source / drain contact structure 108 and the 2D channel region 106C using a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the p-type drain current improvement layer 114P has a thickness in the range of about 1 nm to 50 nm.

[0115] like FIG. 7 As shown, the source / drain contact structure 108 for the PFET has a first half-metal layer 110 that is thinner than the second half-metal layer 112. Therefore, the interface formed between the p-type drain current improvement layer 114P and the sidewall of the first half-metal layer 110 is smaller than the interface formed with the sidewall of the second half-metal layer 112. For example, the area ratio of the sidewall interface between the first half-metal layer 110 and the p-type drain current improvement layer 114P to the sidewall interface between the second half-metal layer 112 and the p-type drain current improvement layer 114P is approximately 10:12.

[0116] FIG. 8 This is a graph showing the improvement in PFET drain current caused by the p-type drain current improvement layer 114P according to some embodiments of this disclosure. In detail, FIG. 8 Experimental results illustrating the current-voltage (IV) characteristics of different WSe2 channel FETs are presented, where the differences between these WSe2 channel FETs lie in the presence or absence of the p-type drain current improvement layer 114P. Curve C81 represents the current-voltage characteristics of a WSe2 channel FET including a source / drain contact structure with an Sb:Pt thickness ratio of approximately 10:12 (e.g., a source / drain contact structure with 10 nm thick Sb and 12 nm thick Pt) but without the p-type drain current improvement layer 114P. Curve C82 represents the current-voltage characteristics of a WSe2 channel FET including the p-type drain current improvement layer 114P (e.g., MoO2). x) source / drain contact structure having a Sb to Pt thickness ratio of about 10: 12 (e.g., a source / drain contact structure having a 10 nm thick Sb and a 12 nm thick Pt). As shown in FIG. 8 C82 exhibits superior drain current behavior to I-V curve C81 under conditions of negative gate voltage. These data demonstrate that integration of a p-type drain current improvement layer 114P covering the source / drain contact structure 108 and the 2D channel region 106C can be used to increase the drain current when the WSe2 channel FET is operated in PFET mode. Further, it is observed that the drain current of a p-type WSe2 channel FET having a p-type drain current improvement layer 114P covering a Sb-Pt contact structure is greater than the drain current of a p-type WSe2 channel field effect transistor having other metal contact structures (e.g., a Ru contact structure, an Au contact structure, a Pd contact structure, an In contact structure, a Ni contact structure, a Ti contact structure, or a combination thereof). In some embodiments, the WSe2 channel FET having a p-type drain current improvement layer 114P has an effective mobility (μeff) in a range from about 10.5 cm 2 / v-s to about 11.5 cm 2 / v-s (e.g., about 10.8 cm 2 / v-s) and a contact resistance (R c ) in a range from about 0.7 kQ-μm to about 1.0 kQ-μm (e.g., about 0.9 kQ-μm).

[0117] FIG. 9 to FIG. 28A Cross-sectional views illustrating intermediate stages in the formation of a semiconductor device in accordance with some embodiments of the present disclosure are presented. In the various views and illustrative embodiments, like reference numerals are used to denote like elements. It is understood that additional operations can be provided before, during, and after the processes described in FIG. 9 to FIG. 28A , and some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged.

[0118] As FIG. 9As shown in FIG. 6A, an initial structure is received. The initial structure includes a substrate 610. The substrate 610 includes an N-well region 600N and a P-well region 600P, where the N-well region 600N can be doped with an N-type impurity (e.g., phosphorous, arsenic, antimony, or the like) and the P-well region 600P can be doped with a P-type impurity (e.g., boron, boron fluoride, indium, or the like). The substrate 610 can be a semiconductor material and can include, for example, a graded layer or a buried oxide. Other materials, such as germanium, quartz, sapphire, and glass, can alternatively be used for the substrate 610. Alternatively, the silicon substrate 610 can be an active layer of a semiconductor-on-insulator (SOI) substrate or a multi-layer structure such as a silicon germanium layer formed on a bulk silicon layer.

[0119] An isolation structure 605 is disposed in the substrate 610. In some embodiments, the isolation structure 605 can include an oxide, such as silicon dioxide. The isolation structure 605 can be formed by a chemical vapor deposition (CVD) technique using tetraethyl orthosilicate (TEOS) and oxygen as precursors, which acts as a shallow trench isolation (STI) around the P-well region 600P and the N-well region 600N.

[0120] A gate structure 600A is disposed over the P-well region 600P of the substrate 610 and a gate structure 600B is disposed over the N-well region 600N of the substrate 610. In some embodiments, each of the gate structure 600A and the gate structure 600B includes a gate dielectric 602 and a gate electrode 604. In some embodiments, the gate dielectric 602 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. In some embodiments, the gate electrode 604 can include polysilicon (poly-Si) or polysilicon germanium (poly-SiGe). In some other embodiments, the gate structure 600A and the gate structure 600B can be a metal gate structure including a high-k dielectric layer, a work function metal layer over the high-k dielectric layer, and a gate metal over the work function metal layer.

[0121] A cap layer 625 is disposed over the gate structures 600A and 600B. In some embodiments, the cap layer 625 can be an oxide. A plurality of gate spacers 612 is disposed on opposite sides of the gate structures 600A and 600B. In some embodiments, the gate spacers 612 can include SiO2, Si3N4, SiO x N y , SiC, SiCN film, SiOC, SiOCN film, and / or a combination thereof.

[0122] N-type source / drain regions 620N are disposed in P-well regions 600P of substrate 610 on opposite sides of gate structure 600A, and p-type source regions 620P are disposed in N-well regions 620N of substrate 610 on opposite sides of gate structure 600B. In some embodiments, n-type source / drain regions 620N can be doped with n-type impurities, and p-type source / drain regions 620P can be doped with p-type impurities. In some embodiments, source / drain regions 620N, 620P can be formed by performing an epitaxial growth process that provides epitaxial material over substrate 610, and thus, source / drain regions 620N and 620P can be referred to interchangeably as epitaxial structures 620N and 620P herein. In various embodiments, source / drain regions 620N, 620P can include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials.

[0123] A contact etch stop layer (CESL) 630 is disposed over isolation structure 605 and over cap layer 625. An interlayer dielectric (ILD) layer 640 is disposed over CESL 630 and around gate structures 600A and 600B. In some embodiments, CESL 630 includes silicon nitride, silicon oxynitride, or other suitable materials. CESL 630 can be formed using, for example, plasma-enhanced CVD, low-pressure CVD, ALD, or other suitable techniques. In some embodiments, ILD layer 640 can include silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicate glass (FSG), carbon-doped silicon oxide, amorphous fluorocarbon, parylene, bisbenzocyclobutene (BCB), or polyimide. ILD layer 640 can be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques.

[0124] A source / drain contact structure 650 is disposed in the ILD layer 640 and contacts the source / drain regions 620N and 620P. In some embodiments, each source / drain contact structure 650 includes a barrier layer 652 and a contact plug 654. The barrier layer 652 is located between the contact plug 654 and the underlying source / drain region 620N or 620P. In some embodiments, the barrier layer 652 facilitates the deposition of the contact plug 654 and helps reduce the outward diffusion of the metallic material of the contact plug 654. In some embodiments, the barrier layer 652 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. The contact plug 654 includes a conductive material such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive materials. In some embodiments, because the source / drain contact structure 650 does not contact the two-dimensional semiconductor material (e.g., WSe2), the source / drain contact structure 650 is formed of a material different from the aforementioned multilayer source / drain contact structure 108.

[0125] An etch stop layer (ESL) 700 is disposed above the ILD layer 640 and the source / drain contact structure 650. An inter-metal dielectric (IMD) layer 705 is disposed above the ESL 700. The material and formation method of the ESL 700 are similar to those of the ESL 630. Furthermore, the material and formation method of the IMD layer 705 are similar to those of the ILD layer 640.

[0126] exist FIG. 10 In this process, the ESL 700 and IMD layer 705 are patterned using suitable optical lithography and etching techniques to form trenches O1, thereby exposing the source / drain contact structure 650. In some embodiments, trench O1 exposes the source / drain contact structure 650, while another trench O1 extends laterally for a longer length to expose the source / drain contact structure 650 of an adjacent transistor.

[0127] exist FIG. 11 In this process, one or more liner layers 710 are conformally deposited into the trench O1 using physical vapor deposition (PVD), CVD, ALD, or similar methods. In some embodiments, the one or more liner layers 710 include a diffusion barrier layer and a copper (Cu) seed layer. The diffusion barrier layer includes a tantalum-containing material, such as tantalum (Ta) or tantalum nitride (TaN), to protect the IMD layer 705 from metal diffusion and poisoning by the subsequently formed copper layer.

[0128] exist FIG. 12In some embodiments, a fill metal layer 712 is deposited over the one or more liner layers 710 until the trench Ol is overfilled by the fill metal layer 712. The fill metal layer 712 can be formed by electroplating a metal material over the one or more liner layers 710, followed by performing an annealing process on the metal material. In some embodiments, the fill metal layer 712 can be formed of a metal material such as copper, although other conductive materials such as nickel, gold, or metal alloys, combinations of these materials, or the like can also be used.

[0129] In FIG. 13 In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process can be performed to remove excess metal material of the fill metal layer 712 and the liner layers 710 from the top surface of the IMD layer 705, while leaving portions of the fill metal layer 712 and the liner layers 710 in the trench Ol to serve as the metal wire 714 embedded in the IMD layer 705.

[0130] In FIG. 14 In some embodiments, another ESL 716 and another IMD layer 718 are sequentially formed over the IMD layer 705. The material and fabrication method of the ESL 716 are similar to the ESL 700, and thus are not repeated for brevity. The material and fabrication method of the IMD layer 718 are similar to the IMD layer 705, and thus are not repeated for brevity.

[0131] In FIG. 15 In some embodiments, a back gate structure 720 is formed over the IMD layer 718. In some embodiments, the back gate structure 720 is formed by depositing one or more gate metal layers over the IMD layer 718, followed by patterning the one or more gate metal layers into the back gate structure 720 using suitable optical lithography and etching processes. In some embodiments, the back gate structure 720 includes TiN, TaN, Ti, Ta, Ru, Mo, Al, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, W, Co, the like, or combinations thereof. The materials used to form the back gate structure 720 can be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, or the like.

[0132] In FIG. 16In this process, a high-k dielectric layer 722 is formed over the back gate structure 720 using CVD, ALD, or other suitable deposition techniques. The high-k dielectric layer 722 covers the three sides of the back gate structure 720. In some embodiments, the high-k dielectric layer 722 has a dielectric constant greater than that of silicon oxide (approximately 3.9). The high-k dielectric layer 722 may include hafnium oxide (HfO2). Alternatively, the high-k dielectric layer 722 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), tantalum titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0133] exist FIG. 17 In this process, a planarization process, such as a CMP process, is performed to thin the high-k dielectric layer 722 until the target thickness of the high-k dielectric layer 722 is achieved. After the CMP process is completed, the gate dielectric region 722g directly above the back gate structure 720 has a finely tuned thickness suitable for use as a gate dielectric in a WSe2 channel FET. In some embodiments, the CMP process is a timing CMP process with a predetermined CMP duration.

[0134] exist FIG. 18 In this process, another ILD layer 724 is formed above the high-k dielectric layer 722. In some embodiments, the ILD layer 724 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicone glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The ILD layer 724 may be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques.

[0135] exist FIG. 19In some embodiments, one or more openings O2 are formed in the ILD layer 724 by using suitable optical lithography and etching techniques. The openings O2 are used to define a pattern of the WSe2 layer that is subsequently formed. In some embodiments, the openings O2 vertically overlap the back gate structure 720, which allows the channel region of the subsequently formed WSe2 layer to be controlled by using the back gate structure 720.

[0136] In some embodiments, the transition metal layer 726 is converted to a transition metal dichalcogenide (TMD) layer 728, which is interchangeably referred to as a two-dimensional semiconductor layer 728. For example, an annealing process can be performed using a sulfur-containing gas (e.g., H2S) or a selenium-containing gas (H2Se) as an ambient gas to sulfurize or selenize the transition metal layer 726 into the TMD layer 728. For example, in some embodiments where the transition metal layer 726 is W, an annealing process performed using H2Se results in a selenization reaction with W to form WSe2 that serves as the TMD layer 728. FIG. 20 In some embodiments, the transition metal layer 726 is converted to a transition metal dichalcogenide (TMD) layer 728, which is interchangeably referred to as a two-dimensional semiconductor layer 728. For example, an annealing process can be performed using a sulfur-containing gas (e.g., H2S) or a selenium-containing gas (H2Se) as an ambient gas to sulfurize or selenize the transition metal layer 726 into the TMD layer 728. For example, in some embodiments where the transition metal layer 726 is W, an annealing process performed using H2Se results in a selenization reaction with W to form WSe2 that serves as the TMD layer 728.

[0137] FIG. 21 In some embodiments, the transition metal layer 726 is converted to a transition metal dichalcogenide (TMD) layer 728, which is interchangeably referred to as a two-dimensional semiconductor layer 728. For example, an annealing process can be performed using a sulfur-containing gas (e.g., H2S) or a selenium-containing gas (H2Se) as an ambient gas to sulfurize or selenize the transition metal layer 726 into the TMD layer 728. For example, in some embodiments where the transition metal layer 726 is W, an annealing process performed using H2Se results in a selenization reaction with W to form WSe2 that serves as the TMD layer 728.

[0138] In some embodiments, the transition metal layer 726 is converted to a transition metal dichalcogenide (TMD) layer 728, which is interchangeably referred to as a two-dimensional semiconductor layer 728. For example, an annealing process can be performed using a sulfur-containing gas (e.g., H2S) or a selenium-containing gas (H2Se) as an ambient gas to sulfurize or selenize the transition metal layer 726 into the TMD layer 728. For example, in some embodiments where the transition metal layer 726 is W, an annealing process performed using H2Se results in a selenization reaction with W to form WSe2 that serves as the TMD layer 728. FIG. 22 In some embodiments, the transition metal layer 726 is converted to a transition metal dichalcogenide (TMD) layer 728, which is interchangeably referred to as a two-dimensional semiconductor layer 728. For example, an annealing process can be performed using a sulfur-containing gas (e.g., H2S) or a selenium-containing gas (H2Se) as an ambient gas to sulfurize or selenize the transition metal layer 726 into the TMD layer 728. For example, in some embodiments where the transition metal layer 726 is W, an annealing process performed using H2Se results in a selenization reaction with W to form WSe2 that serves as the TMD layer 728.

[0139] FIG. 23 to FIG. 28A ​Exemplary processing steps to form a multi-layer source / drain contact structure in the source / drain contact structure opening O3 are illustrated. These processing steps are exemplary only and are not intended to be limiting of the present disclosure. In FIG. 23 In some embodiments, the first semimetal layer 734 is antimony (Sb). Deposition of antimony can be achieved via several techniques, such as PVD, CVD, or molecular beam epitaxy (MBE).

[0140] Using PVD as an example, the first semimetal layer 110 can be deposited using an evaporation process. In an evaporation process, a source of antimony is placed in an evaporation source holder inside a high vacuum chamber. The source material is then heated to its sublimation point using resistive heating or electron beam heating. Upon reaching the sublimation point, antimony atoms begin to evaporate from the source and travel along a target path in the vacuum chamber. The substrate 610 with the high-k dielectric layer 722 is positioned above the antimony source and held at a lower temperature to promote adhesion and condensation of the evaporated antimony atoms. A shutter can be used to control the deposition time and achieve the desired thickness of the antimony layer. The evaporated antimony atoms adhere to the top surface of the high-k dielectric layer 722 and the top surface of the patterned mask layer 730, forming the first semimetal layer 734.

[0141] In FIG. 24 In some embodiments, the first semimetal layer 734 is antimony (Sb). Deposition of antimony can be achieved via several techniques, such as PVD, CVD, or molecular beam epitaxy (MBE).

[0142] Next, the exposed left side portions of the exposed leftmost first semimetal layer 734a and the first semimetal layer 734b are etched back using the patterned mask layer 736 as an etch mask, thereby forming thinned first semimetal portions 738b of the thinned first semimetal layer 738a and the first semimetal layer 734b that are contiguous to the unthinned portions, as illustrated in FIG. 7E. FIG. 25The thinned first metal layer 738a and the thinned first metal portion 738b have a thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nm), and the unthinned first metal portion 734b and the unthinned first metal layer 734c have a thickness in a range from about 25 nm to about 35 nm (e.g., about 30 nm). The difference in thickness allows for the use of the thinned first metal layer 738a and the thinned first metal portion 738b as a basis for forming PFET source / drain contact structures, while using the unthinned first metal portion 734b and the unthinned first metal layer 738c as a basis for forming NFET source / drain contact structures. Once the thickness difference is created, the patterned mask layer 736 is removed, as shown in FIG. 7C. FIG. 26

[0143] In FIG. 27 In some embodiments, the second metal layer 742 is platinum (Pt) and has a thickness in a range from about 10 nm to about 15 nm (e.g., about 12 nm). Deposition of platinum can be achieved via several techniques, such as PVD or CVD. Using PVD as an example, the second metal layer 742 can be deposited using evaporation. In a platinum evaporation process, a platinum source is placed in an evaporation boat or crucible within a high vacuum chamber. The platinum source is then heated, such as using resistance or electron beam heating, until it reaches an evaporation temperature. As platinum atoms evaporate, they travel in a line of sight path within the vacuum chamber toward the substrate 610. The substrate 610, which has included the thinned first metal layer 738a, 738b and the unthinned first metal layer 734b, 734c, is positioned a distance above the platinum source. The substrate 610 is held at a lower temperature to promote condensation and adhesion of the evaporated platinum atoms. A shutter mechanism can be used to control the exposure time, allowing for precise control of the thickness of the platinum layer. The evaporated platinum atoms adhere to the thinned first metal layer 738a, 738b and the unthinned first metal layer 734b, 734c, forming the second metal layer 742.

[0144] ​In some embodiments where antimony forms the first semimetal layers 734b, 734c and the thinned first semimetal layers 738a, 738b, a resublimation phenomenon of antimony can be observed during the platinum deposition of the second semimetal layers 742. This is attributed to the lower sublimation temperature of antimony compared to platinum. During the evaporation process of the platinum deposition, the chamber environment is subjected to a temperature that exceeds the sublimation point of antimony. As a result, the thickness of the pre-existing first semimetal layers 734b, 734c and thinned layers 738a, 738b can be reduced. Furthermore, considering the sublimation of antimony during the platinum deposition, a composition mixing is possible. Specifically, a mixture of resublimated antimony atoms and evaporated platinum atoms can collectively adhere to the surface of the underlying first semimetal layers. This can result in the second semimetal layers 742 having a non-uniform composition of Sb-Pt alloy.

[0145] In some embodiments, because the top surface of the unthinned first semimetal layers 734b, 734c is higher than the top surface of the thinned first semimetal layers 738a, 738b, the top surface of the second semimetal layers 742c and 742d can be higher than the top surface of the second semimetal layers 742a and 742b.

[0146] In FIG. 28A and FIG. 28B The resulting structure includes the NFET 800N and PFET 800P sharing the common back gate structure 720, which in turn collectively function as a complementary FET (CFET) structure. The PFET 800P includes a first PFET source / drain contact structure including a stack of the first semimetal layer 738a and the second semimetal layer 742a, and a second PFET source / drain contact structure including a stack of the first semimetal layer 738b and the second semimetal layer 742b. The NFET 800N includes a first NFET source / drain contact structure including a stack of the first semimetal layer 734b and the second semimetal layer 742c, and a second NFET source / drain contact structure including a stack of the first semimetal layer 734c and the second semimetal layer 742d.

[0147] In some embodiments, the NFET source / drain contact structures each include a thickness ratio of Sb to Pt (i.e., a thickness ratio of the first semimetal layer to the second semimetal layer) that is more than 100%, allowing the WSe2 channel FET to function primarily as an NFET, as described in detail above. In some embodiments, the PFET source / drain contact structures each include a thickness ratio of Sb to Pt (i.e., a thickness ratio of the first semimetal layer to the second semimetal layer) that is less than 100%, allowing the WSe2 channel FET to function primarily as a PFET, as described above. In such scenarios, the NFET source / drain contact structures have a first semimetal layer that is thicker than the PFET source / drain contact structures, but have a second semimetal layer that is the same thickness as the PFET source / drain contact structures. Thus, the NFET source / drain contact structures have a higher top surface than the PFET source / drain contact structures.

[0148] FIG. 28B is FIG. 28A An example top-down view of the structure in FIG. 28B As shown in FIG. 28B The PFET source / drain contact structure labeled "pMD" in FIG. 28B The NFET source / drain contact structure labeled "nMD" in

[0149] FIG. 29 to FIG. 33 Exemplary processing steps to form a multi-layer source / drain contact structure in a source / drain contact opening O3 are illustrated in accordance with some other embodiments. These processing steps are merely exemplary and are not intended to limit the disclosure. In FIG. 29 In

[0150] In FIG. 30 In

[0151] In FIG. 31In some embodiments, thicker first semimetal layers 754a and 754b are deposited over the NFET regions, with the patterned mask layer 756 shielding the PFET regions. In some embodiments, the thicker first semimetal layers 754a and 754b have a greater thickness than the thinner first semimetal layers 750a and 750b, such that the adjoining first semimetal layers 750b and 754a form a stepped top surface profile with a step between the top surface of the thinner first semimetal layer 750b and the top surface of the thicker first semimetal layer 754a. In some embodiments, the step is in a range from about 15 nm to about 25 nm (e.g., about 20 nm). In some embodiments, the thinner first semimetal layers 750a and 750b have a thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nm), and the thicker first semimetal layers 754a and 754b have a thickness in a range from about 25 nm to about 35 nm (e.g., about 30 nm). This thickness difference allows the use of the thinner first semimetal layers 750a and 750b as a basis for forming the source / drain contact structures for the PFETs, while using the thicker first semimetal layers 754a and 754b as a basis for forming the NFETs.

[0152] In some embodiments, the patterned mask layer 756 is removed by using, for example, a lift-off process. The lift-off of the patterned mask layer 756 also removes any overlying material in the thicker first semimetal layers. FIG. 32

[0153] In some embodiments, second semimetal layers 742a, 742b, 742c, and 742d (collectively, second semimetal layers 742) are formed over the thinner first semimetal layers 750a and 750b and the thicker first semimetal layers 754a and 754b, respectively. In some embodiments, the two-dimensional semiconductor layer 728 is covered with a patterned mask layer prior to forming the second semimetal layers 742. After the formation of the second semimetal layers 742 is complete, the patterned mask layer is removed by using a lift-off process. In some embodiments, the second semimetal layers 742 are platinum (Pt) and have a thickness in a range from about 10 nm to about 15 nm (e.g., about 12 nm). The deposition of platinum can be achieved via several techniques such as PVD or CVD, as previously described with respect to the deposition of the first semimetal layers 750a and 750b. FIG. 33 FIG. 27

[0154] FIG. 34 Exemplary cross-sectional views of semiconductor devices, in accordance with some other embodiments of the present disclosure, are illustrated. FIG. 34 Exemplary cross-sectional views of semiconductor devices, in accordance with some other embodiments of the present disclosure, are illustrated. FIG. 28A or FIG. 33 ​​​substantially identical structure, except that a p-type drain current improvement layer 760P is formed over each PFET source / drain contact structure including a thinned first semimetal layer 738 and a second semimetal layer 742, and an n-type drain current improvement layer 760N is formed over each NFET source / drain contact structure including an un-thinned first semimetal layer 734 and a second semimetal layer 742. The p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N are formed in a deposition and patterning process. For example, in some embodiments, the p-type drain current improvement layer 760P is formed by a blanket deposition of a blanket layer across both the NFET region and the PFET region, followed by patterning the blanket layer into the p-type drain current improvement layer 760P positioned at the PFET region. Similarly, the n-type drain current improvement layer 760N is formed by a blanket deposition of a blanket layer across both the NFET region and the PFET region, followed by patterning the blanket layer into the n-type drain current improvement layer 760N positioned at the NFET region.

[0155] When the WSe2 channel FET is operated in PFET mode (i.e., under negative gate voltage conditions), the p-type drain current improvement layer 760P has a material suitable for increasing drain current. In some embodiments, the p-type drain current improvement layer 760P is a layer of molybdenum oxide (MoO x ), a layer of nitrogen dioxide (NO2), a layer of tungsten oxide (WO x ), a layer of iodine (I2), a combination thereof, or the like, deposited over the PFET source / drain contact structures and the two-dimensional semiconductor layer 728 extending between the PFET source / drain contact structures using a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the p-type drain current improvement layer 760P has a thickness in a range of about 1 nm to 50 nm.

[0156] When the WSe2 channel FET is operated in NFET mode (i.e., under positive gate voltage conditions), the n-type drain current improvement layer 760N has a material suitable for increasing drain current. In some embodiments, the n-type drain current improvement layer 760N is a layer of silicon oxynitride (SiON x ), a layer of hafnium oxide (HfO x ), a layer of aluminum oxide (AlO x ), a layer of titanium oxide (TiO xA layer, a composition thereof, or the like, is deposited over the NFET source / drain contact structure and a two-dimensional semiconductor layer 728 extending between the NFET source / drain contact structure using a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the n-type drain current improvement layer 760N has a thickness in the range of about 1 nm to 50 nm.

[0157] FIG. 35 An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 35 Display and FIG. 28A or FIG. 33 The structures are essentially the same, except that the common back gate structure 720 is replaced by two separate back gate structures 762 and 764. Back gate structures 762 and 764 are located within the PFET and NFET regions, respectively, allowing the PFET and NFET to be independently controlled by the different back gate structures 762 and 764. Specifically, back gate structure 762 is laterally positioned between the PFET source / drain contact structures and perpendicularly overlaps with a two-dimensional semiconductor layer 728 extending between the PFET source / drain contact structures; back gate structure 764 is laterally positioned between the NFET source / drain contact structures and perpendicularly overlaps with a two-dimensional semiconductor layer 728 extending between the NFET source / drain contact structures. The separate back gate structures 762 and 764 can be positioned using suitable optical lithography and etching techniques, such as... FIG. 15 The steps shown are formed at the location.

[0158] FIG. 36 An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 36 Display and FIG. 35 The structures are essentially the same, differing only in that a p-type drain current improvement layer 760P is formed on each PFET source / drain contact structure, including a thinned first half-metal layer 738 and a second half-metal layer 742; and an n-type drain current improvement layer 760N is formed on each NFET source / drain contact structure, including an unthinned first half-metal layer 734 and a second half-metal layer 742. The p-type drain current improvement layer 760P is perpendicularly overlapped with the entire back gate structure 762, and the n-type drain current improvement layer 760N is perpendicularly overlapped with the entire back gate structure 764. Exemplary materials and other details regarding the drain current improvement layers 760P and 760N have been previously referenced. FIG. 34 Therefore, for the sake of brevity, this will not be discussed further here.

[0159] FIG. 37An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 37 Display and FIG. 36 The structures are essentially the same, except that the back gate structures 762 and 764 are replaced by front gate structures 766 and 768 formed above the p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N, respectively. In some embodiments where the p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N are dielectric materials, they can be used as gate dielectrics to space the front gate structures 766 and 768 from the underlying two-dimensional semiconductor material 728. In some embodiments, the front gate structures 766 and 768 are formed, for example, by depositing one or more gate metal layers above the p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N, and then patterning the one or more gate metal layers into the front gate structures 766 and 768.

[0160] FIG. 38 An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 38 Display and FIG. 35 The structures are essentially the same, except that the PFET source / drain contact structure containing half-metal layers 738b and 742b is spaced apart from the adjacent NFET source / drain contact structure containing half-metal layers 734b and 742c. Therefore, in this embodiment, the NFET and PFET do not share a common source / drain contact structure. This structure can be achieved, for example, by... FIG. 35 The structure shown is formed by performing an etching process to etch through the half-metal layers 742b, 742c, 738b and 734b, thereby forming a separate source / drain contact structure.

[0161] FIG. 39 An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 39 Display and FIG. 38 The structures are essentially the same, differing only in that a p-type drain current improvement layer 760P is formed on each PFET source / drain contact structure, including a thinned first half-metal layer 738 and a second half-metal layer 742; and an n-type drain current improvement layer 760N is formed on each NFET source / drain contact structure, including an unthinned first half-metal layer 734 and a second half-metal layer 742. The p-type drain current improvement layer 760P contacts the outermost walls of half-metal layers 738b and 742b facing the NFET region. The n-type drain current improvement layer 760N contacts the outermost walls of half-metal layers 734b and 742c facing the PFET region. Exemplary materials and other details regarding the drain current improvement layers 760P and 760N have been previously referenced. FIG. 34 Therefore, for the sake of brevity, this will not be discussed further here.

[0162] FIG. 40 An exemplary cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure is shown. FIG. 40 Display and FIG. 39 The structures are essentially the same, except that the back gate structures 762 and 764 are replaced by front gate structures 766 and 768 formed above the p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N, respectively. In some embodiments where the p-type drain current improvement layer 760P and the n-type drain current improvement layer 760N are dielectric materials, they can be used as gate dielectrics to separate the front gate structures 766 and 768 from the underlying two-dimensional semiconductor material 728.

[0163] Based on the foregoing discussion, it is evident that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. One advantage is that the Sb-Pt contact structure mitigates the Fermi level pinning problem commonly encountered when using Pd contact structures in two-dimensional semiconductor devices. Another advantage is that the effective work function of the Sb-Pt contact structure is tunable by varying the thickness ratio between the Sb and Pt layers, thereby advantageously improving the performance of PFETs and NFETs.

[0164] In some embodiments, an apparatus includes an NFET and a PFET. The NFET includes a first two-dimensional (2D) semiconductor layer and first source / drain contact structures on opposite sides of the first 2D semiconductor layer. The PFET includes a second 2D semiconductor layer and second source / drain contact structures on opposite sides of the second 2D semiconductor layer. Each of the first source / drain contact structures includes a first semimetal layer and a second semimetal layer over the first semimetal. Each of the second source / drain contact structures includes a third semimetal layer and a fourth semimetal layer over the third semimetal layer. A thickness ratio of the first semimetal layer to the second semimetal layer in the NFET is greater than a thickness ratio of the third semimetal layer to the fourth semimetal layer in the PFET. In some embodiments, the first semimetal layer and the third semimetal layer comprise a same material. In some embodiments, the first semimetal layer is an antimony layer and the third semimetal layer is an antimony layer. In some embodiments, the second semimetal layer and the fourth semimetal layer comprise a same material. In some embodiments, the second semimetal layer is a platinum layer and the fourth semimetal layer is a platinum layer. In some embodiments, the thickness ratio of the first semimetal layer to the second semimetal layer in the NFET is greater than 100%. In some embodiments, the thickness ratio of the third semimetal layer to the fourth semimetal layer in the PFET is less than 100%. In some embodiments, the apparatus further includes a first cap layer covering the first source / drain contact structures of the NFET and a second cap layer covering the second source / drain contact structures of the PFET. The first cap layer and the second cap layer are formed of different materials. In some embodiments, the first cap layer is formed of silicon oxynitride, hafnium oxide, aluminum oxide, or titanium oxide. In some embodiments, the second cap layer is formed of molybdenum oxide, nitrogen dioxide, tungsten oxide, or iodine.

[0165] In some embodiments, an apparatus includes a first two-dimensional (2D) semiconductor layer over a substrate, a first source / drain contact structure in contact with a first region of the first 2D semiconductor layer, and a second source / drain contact structure in contact with a second region of the first 2D semiconductor layer spaced apart from the first region of the first 2D semiconductor layer. The first source / drain contact structure includes a first antimony layer in contact with the first region of the first 2D semiconductor layer and a first platinum layer over the first antimony layer. In some embodiments, the first antimony layer has a thickness less than a thickness of the first platinum layer. In some embodiments, the first antimony layer has a thickness greater than twice the thickness of the first platinum layer. In some embodiments, the apparatus further includes a second 2D semiconductor layer over the substrate, a third source / drain contact structure in contact with a first region of the second 2D semiconductor layer, and a fourth source / drain contact structure in contact with a second region of the second 2D semiconductor layer. The third source / drain contact structure includes a second antimony layer and a second platinum layer over the second antimony layer. The first antimony layer and the second antimony layer have different thicknesses, and the first platinum layer and the second platinum layer have the same thickness.

[0166] In some embodiments, a method includes forming a dielectric layer over a substrate; forming a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer over the dielectric layer; forming a first antimony layer and a second antimony layer in contact with opposing sides of the first two-dimensional semiconductor layer; forming a third antimony layer and a fourth antimony layer in contact with opposing sides of the second two-dimensional semiconductor layer; and forming a first platinum layer, a second platinum layer, a third platinum layer, and a fourth platinum layer over the first antimony layer, the second antimony layer, the third antimony layer, and the fourth antimony layer, respectively. The third antimony layer has a thickness greater than a thickness of the first antimony layer. In some embodiments, forming the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer includes forming a first transition metal layer and a second transition metal layer over the dielectric layer, and selenizing the first transition metal layer and the second transition metal layer into the first two-dimensional semiconductor layer and the second two-dimensional semiconductor layer. In some embodiments, the method further includes forming a back gate structure over the substrate. The dielectric layer is formed over the back gate structure. In some embodiments, the fourth antimony layer has a thickness greater than a thickness of the second antimony layer. In some embodiments, a semiconductor device includes a dielectric layer over a substrate; a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer over the dielectric layer; a first antimony layer and a second antimony layer in contact with opposing sides of the first two-dimensional semiconductor layer; a third antimony layer and a fourth antimony layer in contact with opposing sides of the second two-dimensional semiconductor layer, wherein the third antimony layer has a thickness greater than a thickness of the first antimony layer; a first platinum layer, a second platinum layer, a third platinum layer, and a fourth platinum layer over the first antimony layer, the second antimony layer, the third antimony layer, and the fourth antimony layer, respectively.

[0167] The foregoing outlines features of several embodiments so that a thorough comprehension of the present disclosure can be attained. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: an n-type field effect transistor comprising a first two-dimensional semiconductor layer and a plurality of first source / drain contact structures on opposite sides of the first two-dimensional semiconductor layer; and a p-type field effect transistor comprising a second two-dimensional semiconductor layer and a plurality of second source / drain contact structures on opposite sides of the second two-dimensional semiconductor layer, wherein each of the plurality of first source / drain contact structures comprises a first semimetal layer and a second semimetal layer over the first semimetal layer, and each of the plurality of second source / drain contact structures comprises a third semimetal layer and a fourth semimetal layer over the third semimetal layer, wherein a thickness ratio of the first semimetal layer and the second semimetal layer in the n-type field effect transistor is greater than a thickness ratio of the third semimetal layer and the fourth semimetal layer in the p-type field effect transistor.

2. The semiconductor device according to claim 1, wherein The thickness ratio of the first semimetal layer and the second semimetal layer in the n-type field effect transistor is greater than 100%.

3. The semiconductor device according to claim 1, wherein The thickness ratio of the third semimetal layer and the fourth semimetal layer in the p-type field effect transistor is less than 100%.

4. The semiconductor device according to claim 1, wherein Further comprising: a first capping layer capping the plurality of first source / drain contact structures of the n-type field effect transistor; and a second capping layer capping the plurality of second source / drain contact structures of the p-type field effect transistor.

5. A semiconductor device, characterized by comprising: Comprising: a first two-dimensional semiconductor layer over a substrate; a first source / drain contact structure of an n-type field effect transistor in contact with a first region of the first two-dimensional semiconductor layer; and a second source / drain contact structure of an n-type field effect transistor in contact with a second region of the first two-dimensional semiconductor layer, the second region being separated from the first region of the first two-dimensional semiconductor layer, wherein the first source / drain contact structure of the n-type field effect transistor comprises a first antimony layer in contact with the first region of the first two-dimensional semiconductor layer and a first platinum layer over the first antimony layer; a second two-dimensional semiconductor layer over the substrate; a first source / drain contact structure of a p-type field effect transistor in contact with a first region of the second two-dimensional semiconductor layer; and a second source / drain contact structure of a p-type field effect transistor in contact with a second region of the second two-dimensional semiconductor layer, wherein the first source / drain contact structure of the p-type field effect transistor comprises a second antimony layer and a second platinum layer over the second antimony layer, wherein a thickness ratio of the first antimony layer and the first platinum layer is greater than a thickness ratio of the second antimony layer and the second platinum layer.

6. The semiconductor device according to claim 5, wherein The first antimony layer has a thickness greater than a thickness of the first platinum layer.

7. The semiconductor device according to claim 5, wherein The first antimony layer has a thickness greater than twice a thickness of the first platinum layer.

8. The semiconductor device of claim 5, wherein: the first antimony layer and the second antimony layer have different thicknesses, and the first platinum layer and the second platinum layer have a same thickness.

9. A semiconductor device, characterized by comprising: Comprising: a dielectric layer over a substrate; a first two-dimensional semiconductor layer and a second two-dimensional semiconductor layer over the dielectric layer; a first antimony layer and a second antimony layer in contact with opposite sides of the first two-dimensional semiconductor layer; a third antimony layer and a fourth antimony layer in contact with opposite sides of the second two-dimensional semiconductor layer, wherein the third antimony layer has a thickness greater than a thickness of the first antimony layer; and a first platinum layer, a second platinum layer, a third platinum layer, and a fourth platinum layer over the first antimony layer, the second antimony layer, the third antimony layer, and the fourth antimony layer, respectively, wherein the first antimony layer and the first platinum layer form a source / drain contact structure for a p-type field effect transistor, the third antimony layer and the third platinum layer form a source / drain contact structure for an n-type field effect transistor, wherein a thickness ratio of the third antimony layer and the third platinum layer is greater than a thickness ratio of the first antimony layer and the first platinum layer.

10. The semiconductor device according to claim 9, wherein the fourth antimony layer has a thickness greater than a thickness of the second antimony layer.

Images