Signal conversion system

Abstract

The utility model discloses a signal conversion system, which comprises a signal receiving module, a signal analysis and frequency reduction processing module, a signal output module and a Tcon module, corresponding ends of the signal receiving module, the signal analysis and frequency reduction processing module, the signal output module and the Tcon module are electrically connected in sequence; the signal receiving module is used for receiving a V-by-One signal and an LVDS (Low Voltage Differential Signaling) signal; the signal analysis and frequency reduction processing module is used for performing frequency reduction on the received V-by-One signal, converting the received LVDS signal into the V-by-One signal, and outputting the V-by-One signal through the signal output module; and the TCON module is used for receiving the V-by-One signal output by the signal output module and driving the display panel to work. According to the utility model, the 4K 120Hz V-by-One signal is subjected to frequency reduction to 4K 60Hz, so that the 4K resolution content is ensured to be normally displayed on equipment which does not support a high refresh rate.

Description

Technical Field

[0001] This utility model relates to the field of signal conversion technology, and in particular to a signal conversion system. Background Technology

[0002] A significant problem in the current display technology field is the mismatch between the driver board motherboard and the signal interface of the LCD glass. With the increasing prevalence of 4K resolution, some motherboards support 4K 120Hz V-by-One output, while the LCD glass may only have a 4K 60Hz V-by-One input interface. This mismatch prevents display devices from fully utilizing their performance and also limits the compatibility between older signal source devices and newer display devices.

[0003] While traditional LVDS interfaces perform well in low-resolution displays, their bandwidth limitations become a bottleneck in high-resolution and high-refresh-rate 4K displays. Meanwhile, V-by-One interfaces, with their high bandwidth, can support signal transmission at even higher resolutions and refresh rates, but they require compatibility with existing LVDS interfaces. Utility Model Content

[0004] To address the problems existing in the prior art, this invention provides a signal conversion system that downclocks a 4K 120Hz V-by-One signal to 4K 60Hz, ensuring normal display of 4K resolution content on devices that do not support high refresh rates. This avoids the need to replace the high-performance 4K 120Hz processing circuitry, achieving compatibility using existing 4K 60Hz driver boards and reducing hardware costs.

[0005] This technology enables the conversion from low-resolution LVDS signals to high-resolution V-by-One signals, promoting the upgrade of display devices from traditional LVDS technology to V-by-One technology. It allows LVDS-enabled signal source devices (such as older motherboards and embedded systems) to drive new high-resolution displays that support V-by-One, preventing the obsolescence of these devices. It also enables technical upgrades in resolution and interfaces, helping older signal source devices adapt to new display devices.

[0006] It is used to solve the problem of mismatch between the signal interface of the driver board motherboard and the LCD glass. It supports LVDS signal, 16-lane and 8-lane V-by-one signal input, and unifies the output as 8-lane V-by-one signal. It is used to solve the problem that the motherboards on the market are 4K 120Hz V-by-one output.

[0007] To achieve the above objectives, the technical solution of this utility model is as follows:

[0008] This utility model provides a signal conversion system, including: a signal receiving module, a signal parsing and down-conversion processing module, a signal output module, and a Tcon module;

[0009] The corresponding terminals of the signal receiving module, signal parsing and down-frequency processing module, signal output module, and Tcon module are electrically connected in sequence.

[0010] The signal receiving module is used to receive V-by-One signals and LVDS signals;

[0011] The signal analysis and down-frequency processing module is used to down-frequency the received V-by-One signal, convert the received LVDS signal into a V-by-One signal, and output it through the signal output module;

[0012] The TCON module is used to receive the V-by-One signal output by the signal output module and drive the display panel to work.

[0013] Preferably, the signal receiving module is used to receive 4K 120Hz V-by-One signals and FHD 60Hz LVDS signals.

[0014] Preferably, the signal parsing and down-frequency processing module is used to down-frequency the received 4K 120Hz V-by-One signal to a 4K 60Hz V-by-One signal, and to convert the FHD 60Hz LVDS signal into a 4K 60Hz V-by-One signal.

[0015] Preferably, the signal analysis and down-frequency processing module includes an MST6M60FVC chip, used to down-frequency a 4K 120Hz V-by-One signal to a 4K 60Hz V-by-One signal, and to convert an FHD 60Hz LVDS signal into a 4K 60Hz V-by-One signal.

[0016] Preferably, the signal receiving module includes:

[0017] The V-by-One interface is used to receive 16-channel or 8-channel 4K 120Hz V-by-One signals;

[0018] The LVDS interface is used to receive FHD 60Hz LVDS signals.

[0019] Preferably, the signal output module includes:

[0020] The V-by-One output interface is used to output signals in 4K 60Hz V-by-One format.

[0021] Preferably, the V-by-One interface includes FI-RE41S and FI-RE51S interfaces, and the LVDS interface includes FI-RE51S interface two.

[0022] The technical solution of this utility model has the following beneficial effects:

[0023] This invention is used to solve the problem of mismatch between the signal interfaces of the driver board motherboard and the LCD glass. It supports LVDS signal, 16-lane and 8-lane V-by-one signal input, and unifies the output as an 8-lane V-by-one signal, which solves the problem that the motherboards on the market are 4K 120Hz V-by-one output.

[0024] This invention downclocks the 4K 120Hz V-by-One signal to 4K 60Hz, ensuring normal display of 4K resolution content on devices that do not support high refresh rates. It avoids replacing the high-performance 4K 120Hz processing circuitry, achieving compatibility using existing 4K 60Hz driver boards, thus reducing hardware costs.

[0025] This invention enables the conversion from low-resolution LVDS signals to high-resolution V-by-One signals, promoting the upgrade of display devices from traditional LVDS technology to V-by-One technology. It allows LVDS-enabled signal source devices (such as older motherboards and embedded systems) to drive new high-resolution displays that support V-by-One, preventing the obsolescence of these devices. It also achieves technical upgrades in resolution and interfaces, helping older signal source devices adapt to new display devices.

[0026] Easy to integrate: The modular design of this system makes it easy to integrate into existing display systems, and signal conversion and display can be achieved without complicated installation process.

[0027] Wide range of applications: This system is widely applicable to industrial displays, advertising screens, home displays, game console connections and other fields, and has a high degree of application flexibility.

[0028] Technology Upgrade: By upgrading from low-resolution to high-resolution signals, the display quality is improved, enabling older signal source equipment to drive new high-resolution displays, thus achieving a technological upgrade in resolution and interface. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the module of this utility model;

[0030] Figure 2 This is a schematic diagram of the control system of this utility model;

[0031] Figure 3This is the circuit schematic diagram of the MST6M60FVC chip U2A of this utility model;

[0032] Figure 4 This is the circuit schematic diagram of the MST6M60FVC chip U2B of this utility model;

[0033] Figure 5 This is the circuit schematic diagram of the MST6M60FVC chip U2C of this utility model;

[0034] Figure 6 This is the circuit schematic diagram of the MST6M60FVC chip U2D of this utility model;

[0035] Figure 7 This is the circuit schematic diagram of the MST6M60FVC chip U2E of this utility model;

[0036] Figure 8 This is the circuit schematic diagram of the MST6M60FVC chip U2F of this utility model. Detailed Implementation

[0037] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0038] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0040] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0041] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0042] Reference Figures 1 to 8 This utility model provides a signal conversion system, including: a signal receiving module 100, a signal analysis and down-conversion processing module 200, a signal output module 300, and a Tcon module 400;

[0043] The corresponding terminals of the signal receiving module 100, the signal parsing and down-conversion processing module 200, the signal output module 300, and the Tcon module 400 are electrically connected in sequence.

[0044] The signal receiving module 100 is used to receive V-by-One signals and LVDS signals;

[0045] The signal analysis and down-frequency processing module 200 is used to down-frequency the received V-by-One signal, convert the received LVDS signal into a V-by-One signal, and output it through the signal output module 300;

[0046] The TCON module 400 is used to receive the V-by-One signal output by the signal output module 300 and drive the display panel to work.

[0047] Furthermore, the signal receiving module is used to receive high-resolution, high-refresh-rate 4K 120Hz (3840×2160@120Hz) V-by-One signals and low-resolution FHD 60Hz (e.g., 1920×1080@60Hz) LVDS signals.

[0048] Receiving 4K 120Hz V-by-One signals, this high-resolution and high-refresh-rate signal reception capability enables the system to be compatible with high-end display devices, meeting users' demands for an ultra-high-definition and smooth display experience. Simultaneously receiving low-resolution FHD 60Hz LVDS signals ensures compatibility with traditional display devices, such as older embedded systems or standard-definition monitors. By simultaneously supporting high-resolution, high-refresh-rate V-by-One signals and low-resolution LVDS signals, the signal receiving module 100 provides broad signal source adaptability. This allows the system to act as a bridge, connecting signal source devices and display devices of different performance levels and eras.

[0049] Furthermore, the signal analysis and down-frequency processing module 200 is used to down-frequency the received 4K 120Hz V-by-One signal to a 4K 60Hz V-by-One signal, and convert the FHD 60Hz LVDS signal into a 4K 60Hz V-by-One signal. This conversion enables older signal source equipment to drive new high-resolution displays, improves display quality, and extends the service life of older equipment.

[0050] The signal analysis and down-frequency processing module includes an MST6M60FVC chip, which has 6 (refer to...) Figures 3 to 8 The system comprises four MST6M60FVC chips: U2A, U2B, U2C, U2D, U2E, and U2F. These chips are used to down-convert 4K 120Hz V-by-One signals to 4K 60Hz V-by-One signals, and to convert FHD 60Hz LVDS signals to 4K 60Hz V-by-One signals. The MST6M60FVC chips handle the parsing and conversion of various signal inputs (4K 120Hz, FHD 60Hz) and output a 4K 60Hz V-by-One signal. They support down-conversion from V-by-One (high refresh rate) to V-by-One (low refresh rate) and also support format conversion from LVDS to V-by-One. It satisfies the frequency reduction requirements of high refresh rate signals while also taking into account the upgrade requirements of low resolution signals. It is widely applicable to consumer electronics, industrial displays and other fields, and solves the compatibility problem between new and old signal standards.

[0051] In this embodiment, the signal parsing and down-clocking module 200 can perform high refresh rate down-clocking: for a 4K 120Hz V-by-One input signal, the MST6M60FVC chip redistributes the signal along the time axis, reducing the refresh rate from 120Hz to 60Hz to adapt to display devices that do not support high refresh rates. During the down-clocking process, signal synchronization is ensured to avoid screen tearing or frame drops.

[0052] Low-resolution signal upgrade: For FHD (1920×1080@60Hz) LVDS input signals, the chip uses a resolution doubling algorithm to extend the signal to 4K (3840×2160@60Hz) to improve image quality.

[0053] Format conversion: LVDS signals are transmitted in parallel format, while V-by-One signals are transmitted in serial format. The MST6M60FVC converts LVDS to V-by-One format to meet the interface requirements of the target device.

[0054] The design of the signal analysis and down-frequency processing module 200 enables display devices that do not support high refresh rates to stably display 4K content, expanding the scope of device use; it also realizes the upgrade from low-resolution signals to high-resolution signals, improving display quality and extending the service life of older devices.

[0055] Furthermore, the signal receiving module includes: a V-by-One interface for receiving 16-channel or 8-channel 4K 120Hz V-by-One signals to meet high bandwidth requirements. This design allows the signal conversion system to receive signals from high-performance signal sources, such as high-end graphics cards or video processors, ensuring compatibility with the latest display technologies and suitability for 4K ultra-high-definition content transmission, providing richer details and smoother dynamic images. An LVDS interface for receiving FHD 60Hz LVDS signals, adapting to low-bandwidth signals; the LVDS interface is also used to receive low-resolution FHD 60Hz signals, such as 1920×1080@60Hz. This interface compatibility ensures that the signal conversion system can be used with existing standard definition signal source devices, such as older motherboards or embedded systems. Through the LVDS interface, the signal conversion system can receive and process signals from traditional signal sources, enabling these devices to drive new high-resolution displays. This achieves a technological upgrade in resolution and interface, helping older signal source devices adapt to new display devices. The V-by-One interface includes FI-RE41S and FI-RE51S interfaces, and the LVDS interface includes FI-RE51S interface II.

[0056] Furthermore, the signal output module 300 includes: a V-by-One output interface for outputting signals in 4K 60Hz V-by-One format; the V-by-One output interface supports high-bandwidth transmission to ensure that the signal is transmitted to the target device without distortion; the MST6M60FVC chip output signal is transmitted to the Tcon module through the V-by-One interface; the Tcon module further splits the signal into row and column driving signals required by the display screen to drive the screen display.

[0057] Working principle of this utility model:

[0058] Step 1: Signal Input

[0059] Users connect the input signal through the FI-RE41S and FI-RE51S interfaces.

[0060] If the input signal is 4K 120Hz (V-by-One), it enters the V-by-One input channel of the MST6M60FVC chip.

[0061] If the input signal is FHD60Hz (LVDS), it enters the LVDS input channel of the MST6M60FVC chip.

[0062] The MST6M60FVC chip allows you to select the signal type, resolution, and refresh rate via a DIP switch.

[0063] Step 2: Signal Analysis

[0064] The MST6M60FVC chip analyzes the input signal and extracts its resolution, refresh rate, and format information.

[0065] The target output standard is confirmed to be 4K 60Hz V-by-One.

[0066] Step 3: Signal Conversion

[0067] High refresh rate downclocking (e.g., 4K 120Hz → 4K 60Hz):

[0068] The signal time axis is adjusted, and the number of frames is redistributed according to the 60Hz refresh rate.

[0069] The MST6M60FVC chip calibrates frame synchronization information to ensure that there is no delay or screen tearing during the display process.

[0070] Resolution upgrade (e.g., FHD 60Hz → 4K 60Hz):

[0071] Pixel interpolation is performed using existing interpolation algorithms to extend the original resolution to the target resolution;

[0072] Ensure smooth transitions in image details and avoid distortion when magnified;

[0073] Format conversion (LVDS→V-by-One):

[0074] Parallel signals are converted into serial signals and timing control information from the V-by-One protocol is added.

[0075] Step 4: Signal Output

[0076] After conversion, the MST6M60FVC chip transmits the signal in 4K 60Hz V-by-One format through the V-by-One output interface;

[0077] The output signal is transmitted to the TCON module and drives the display panel to work.

[0078] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A signal conversion system, characterized by, Comprise: Signal receiving module, signal analysis and frequency reduction processing module, signal output module, Tcon module; The signal receiving module, signal analysis and frequency reduction processing module, signal output module, Tcon module are electrically connected in sequence corresponding to the end; The signal receiving module is used for receiving V-by-One signal and LVDS signal; The signal analysis and frequency reduction processing module is used for reducing the frequency of the received V-by-One signal, converting the received LVDS signal into V-by-One signal, and outputting through the signal output module; The Tcon module is used for receiving the V-by-One signal output by the signal output module and driving the display panel to work.

2. The signal conversion system of claim 1, wherein, The signal receiving module is used for receiving 4K 120Hz V-by-One signal and FHD 60Hz LVDS signal.

3. The signal conversion system of claim 2, wherein, The signal analysis and frequency reduction processing module is used for reducing the frequency of the received 4K 120Hz V-by-One signal to 4K 60Hz V-by-One signal, and converting the FHD 60Hz LVDS signal into 4K 60Hz V-by-One signal.

4. The signal conversion system of claim 3, wherein, The signal analysis and frequency reduction processing module comprises an MST6M60FVC chip, which is used for reducing the frequency of the 4K 120Hz V-by-One signal to 4K 60Hz V-by-One signal, and converting the FHD 60Hz LVDS signal into 4K 60Hz V-by-One signal.

5. The signal conversion system of claim 4, wherein, The signal receiving module comprises: V-by-One interface, used for receiving 16-channel or 8-channel 4K 120Hz V-by-One signal; LVDS interface, used for receiving FHD 60Hz LVDS signal.

6. The signal conversion system of claim 5, wherein, The signal output module comprises: V-by-One output interface, used for outputting signal in 4K 60Hz V-by-One format.

7. The signal conversion system of claim 5, wherein, The V-by-One interface comprises FI-RE41S and FI-RE51S interfaces, and the LVDS interface comprises FI-RE51S interface two.

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