Plastic package power module structure
By using a substrate design and dual-loop layout for the plastic-encapsulated power module structure, parasitic inductance inside and outside the module is reduced, the problems of voltage overshoot and electromagnetic interference in the prior art are solved, and the reliability and current sharing characteristics of the device are improved.
Patent Information
- Application Number
- CN202520042633.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-01-08
AI Technical Summary
The existing power modules have high parasitic inductance inside and outside the module, which leads to voltage overshoot and electromagnetic interference problems, increases switching losses, causes uneven current in parallel chips, and affects device reliability.
The module adopts a plastic-encapsulated power module structure and uses a substrate design with lead-out structures (positive busbar and negative busbar) stacked design to allow current to flow in opposite directions through adjacent conductors. It also uses a dual-loop layout inside the module to reduce the module's parasitic inductance.
It reduces parasitic inductance outside the module, improves the module's reliability and current sharing characteristics, reduces turn-on and turn-off losses, and enhances device reliability.
Smart Images
Figure CN223743664U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a plastic-encapsulated power module structure. Background Technology
[0002] Power modules are widely used in new energy vehicles, new energy power generation, smart grids, and transportation electrification. In some areas, such as new energy vehicle controllers, there are higher requirements for the miniaturization, lightweighting, and high power of power modules. To achieve high power capabilities, multi-chip parallel connection is often used, but this brings some challenges. Traditional power modules have large parasitic inductance in the power circuit, leading to voltage overshoot and electromagnetic interference problems, increasing switching losses, and reducing device reliability. In addition, mismatched branch parameters within the module may cause uneven current in the parallel chips, leading to thermal failure of individual chips.
[0003] Infineon's HPD (Hybrid Pack Drive) module is a packaged module with silicone filling and a half-bridge structure. However, it has a relatively high parasitic inductance, ranging from 8nH to 12nH depending on the number of internal parallel chips. For example, the parasitic inductance of the 8-chip parallel version is about 10nH.
[0004] Tesla's T-pak module is a plastic-encapsulated module with high parasitic inductance.
[0005] Therefore, how to reduce the parasitic inductance of the circuit within the module or the parasitic inductance outside the module is a focus of attention for those skilled in the art. Utility Model Content
[0006] The purpose of this invention is to propose a plastic-encapsulated power module structure that can at least reduce parasitic inductance outside the module.
[0007] To achieve the above objectives, this utility model provides a plastic-encapsulated power module structure, comprising:
[0008] A substrate, wherein the first layer of the substrate is a wiring layer, the second layer is an insulating layer, and at least one molding compound covers the upper surface of the wiring layer;
[0009] The wiring layer includes a first wiring area and a second wiring area;
[0010] A first group of chips and a second group of chips are disposed on the substrate; the first group of chips is an upper transistor, and the second group of chips is a lower transistor; both the upper transistor and the lower transistor contain at least one power device and one freewheeling diode;
[0011] The power device of the upper tube contains at least a first electrode and a second electrode;
[0012] The freewheeling diode of the upper tube contains at least a third electrode and a fourth electrode;
[0013] The power device of the lower transistor contains at least a fifth and a sixth electrode;
[0014] The freewheeling diode of the lower transistor contains at least a seventh and an eighth electrode;
[0015] At least three power terminals, namely the first terminal, the second terminal, and the third terminal;
[0016] The first terminal is connected to the first pole and the third pole, the second terminal is connected to the sixth pole and the eighth pole, and the third terminal is simultaneously connected to the second pole, the fourth pole, the fifth pole and the seventh pole;
[0017] The first electrode and the third electrode are connected to the first wiring area of the wiring layer through a solder layer; the fifth electrode and the seventh electrode are connected to the second wiring area of the wiring layer through a solder layer; the second electrode and the fourth electrode are connected through a bonding wire and are connected to the second wiring area of the wiring layer through a bonding wire; the sixth electrode and the eighth electrode are connected through a bonding wire and are connected to the second terminal through a bonding wire.
[0018] The third terminal extends from a first side of the encapsulation, the second terminal extends from a second side of the encapsulation, the first side is opposite to the second side, and the first terminal extends from the upper surface of the encapsulation; the direction from the second side to the first side is defined as the first reference direction;
[0019] The positive busbar of the first terminal and the negative busbar of the second terminal are led out in the same direction, so that the positive busbar of the first terminal and the negative busbar of the second terminal have overlapping portions.
[0020] In an optional configuration, based on the first reference direction, the arrangement sequence is: second terminal, power device of the lower transistor, freewheeling diode of the lower transistor, first terminal, freewheeling diode of the upper transistor, power device of the upper transistor, and third terminal.
[0021] In an optional embodiment, the first terminal consists of two or more sub-terminals, and the first wiring area is centrally divided with the first reference direction. The multiple sub-terminals of the first terminal fall within different divided areas. Current flows from the multiple sub-terminals of the first terminal through the first pole and the third pole to the second pole and the fourth pole, then through the bonding wire to the second wiring area of the wiring layer, then through the fifth pole and the seventh pole, through the sixth pole and the eighth pole, and finally to the second terminal.
[0022] In an optional configuration, the power device of the upper transistor is positioned as close as possible to the third terminal, provided that the process allows; and the power device of the lower transistor is positioned as close as possible to the second terminal, provided that the process conditions allow.
[0023] In an alternative embodiment, the first terminal is a conductive block exposed on the upper surface of the encapsulation; or the first terminal is part of the wiring layer and is exposed through a window in the encapsulation.
[0024] In an optional embodiment, the conductive block is made of copper, aluminum, copper-molybdenum alloy, or aluminum silicon carbide.
[0025] In an optional configuration, the bonding wire is an aluminum wire, an aluminum strip, a copper wire, or a copper strip.
[0026] In the optional embodiment, the power device is a fully controllable power device.
[0027] The beneficial effects of this utility model are as follows:
[0028] The plastic-encapsulated power module structure of this utility model, through the stacked design of the lead-out structure (positive busbar and negative busbar), allows the current to flow in opposite directions through the adjacent conductors, which can make the total parasitic inductance less than the sum of the self-inductance of the positive busbar and the negative busbar, thereby reducing the parasitic inductance outside the module.
[0029] Furthermore, the internal power circuit of the plastic-encapsulated power module structure uses a dual-loop (loop1 and loop2) layout to reduce the parasitic inductance of the internal circuit of the module. Attached Figure Description
[0030] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.
[0031] Figure 1 This is a schematic diagram of the structure of a plastic-encapsulated power module in one embodiment of the present invention.
[0032] Figure 2 This is a dual-loop route diagram in one embodiment of the present invention.
[0033] Figure 3 This is a diagram showing the positional relationship between the positive busbar of the first terminal and the negative busbar of the second terminal in one embodiment of the present invention.
[0034] Figure 4 A schematic diagram of the turn-on of a power device without a Kelvin source in the prior art.
[0035] Figure 5 This is a schematic diagram of the power device being turned on in one embodiment of the present invention.
[0036] Figure 6 This is a schematic diagram of the turn-off of a power device without a Kelvin source in the prior art.
[0037] Figure 7 This is a schematic diagram of the power device being turned off in one embodiment of the present invention.
[0038] Figure 8 This is a circuit diagram of the first terminal, the second terminal, and the third terminal in one embodiment of the present invention.
[0039] Figure label:
[0040] 1-First terminal; 2-Second terminal; 3-Third terminal; 4-Upper transistor; 5-Lower transistor; 41-Power device of the upper transistor; 42-Freewheeling diode of the upper transistor; 51-Power device of the lower transistor; 52-Freewheeling diode of the lower transistor; 6-Bond wire; 7-Positive busbar of the first terminal; 8-Negative busbar of the second terminal; 9-First wiring area; 10-Second wiring area. Detailed Implementation
[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and drawings. However, it should be noted that the concept of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.
[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0045] Example 1
[0046] Reference Figures 1 to 8 This embodiment provides a molded power module structure, including:
[0047] The substrate has a first layer as a wiring layer and a second layer as an insulating layer, with at least one molding compound covering the upper surface of the wiring layer; the insulating layer can be made of insulating materials such as aluminum oxide, aluminum nitride, zirconium oxide, silicon nitride, epoxy resin, or silicone.
[0048] The wiring layer includes a first wiring area 9 and a second wiring area 10;
[0049] A first group of chips and a second group of chips are disposed on the substrate; the first group of chips is an upper transistor 4, and the second group of chips is a lower transistor 5; both the upper transistor 4 and the lower transistor 5 contain at least one power device and one freewheeling diode; the power device is a fully controllable power device, such as a metal-oxide-semiconductor field-effect transistor chip (MOSFET chip) or an insulated-gate bipolar transistor chip (IGBT chip); the power device 41 of the upper transistor 4 contains at least a first terminal and a second terminal; the freewheeling diode 42 of the upper transistor 4 contains at least a third terminal and a fourth terminal; the power device 51 of the lower transistor contains at least a fifth terminal and a sixth terminal; the freewheeling diode 52 of the lower transistor contains at least a seventh terminal and an eighth terminal; when the power device 41 of the upper transistor is a MOSFET chip, the first terminal is the drain and the second terminal is the source; when the power device 51 of the lower transistor is a MOSFET chip, the fifth terminal is the drain and the sixth terminal is the source.
[0050] At least three power terminals are defined as a first terminal 1 (DC+), a second terminal 2 (DC-), and a third terminal 3 (AC); the first terminal 1 is connected to the first pole and the third pole, the second terminal 2 is connected to the sixth pole and the eighth pole, and the third terminal 3 is connected to the second pole, the fourth pole, the fifth pole, and the seventh pole.
[0051] The first and third electrodes are connected to the first wiring area 9 of the wiring layer via a solder layer; the fifth and seventh electrodes are connected to the second wiring area 10 of the wiring layer via a solder layer; the second and fourth electrodes are connected via a bonding wire 6 and also connected to the second wiring area 10 of the wiring layer via a bonding wire; the sixth and eighth electrodes are connected via a bonding wire and also connected to the second terminal 2 via a bonding wire. It should be noted that the solder layer and bonding wire are broad concepts and do not specifically refer to a particular layer or wire. The solder layer can be conductive materials such as sintered silver, solder, or conductive silver paste. The bonding wire can be aluminum wire, aluminum strip, copper wire, or copper strip.
[0052] The third terminal 3 extends from the first side of the encapsulation, the second terminal 2 extends from the second side of the encapsulation, the first side and the second side are opposite each other, and the first terminal 1 extends from the upper surface of the encapsulation; the direction from the second side to the first side is defined as the first reference direction. (Refer to...) Figure 3 The positive busbar 7 of the first terminal and the negative busbar 8 of the second terminal are led out in the same direction, so that the positive busbar 7 of the first terminal and the negative busbar 8 of the second terminal have overlapping portions.
[0053] In this embodiment, the total parasitic inductance of the external circuit of the module is L. loop3 =L DC+ +L DC- -2×M, L DC+ For the self-inductance of the positive busbar 7 of the first terminal, L DC- M is the self-inductance of the negative busbar 8 at the second terminal, and M is the mutual inductance between the positive busbar 7 and the negative busbar 8, which is a positive number. By using the stacked design of the lead-out structure (positive busbar and negative busbar), the current flows through the adjacent conductors in opposite directions, which makes the total parasitic inductance less than the sum of the self-inductances of the positive busbar and the negative busbar, thus reducing the parasitic inductance outside the module.
[0054] In this embodiment, based on the first reference direction, the arrangement sequence is as follows: second terminal 2, power device 51 of the lower transistor, freewheeling diode 52 of the lower transistor, first terminal 1, freewheeling diode 42 of the upper transistor, power device 41 of the upper transistor, and third terminal 3. The power device 41 of the upper transistor is placed as close as possible to the third terminal 3, provided that the process allows; the power device 51 of the lower transistor is placed as close as possible to the second terminal 2, provided that the process allows.
[0055] Reference Figure 1 and Figure 2 In this embodiment, the first terminal consists of two or more sub-terminals. Figure 2 Taking two sub-terminals as an example, the first wiring area 9 is divided in the center with the first reference direction (from bottom to top). The two (or more) sub-terminals of the first terminal fall in different areas of the division (distributed left and right). The current flows from the multiple sub-terminals of the first terminal 1 through the first pole and the third pole to the second pole and the fourth pole, then through the bonding wire to the second wiring area 10 of the wiring layer, then through the fifth pole and the seventh pole, through the sixth pole and the eighth pole, and finally to the second terminal 2.
[0056] This molded power module uses a dual-loop (loop1 and loop2) layout for its internal power circuitry, reducing parasitic inductance within the module. The total parasitic inductance of the internal circuitry is... According to the arithmetic inequality, we know that... Therefore, the dual-loop arrangement can greatly reduce the parasitic inductance of the loops within the module.
[0057] In this embodiment, the first terminal 1 is a conductive block exposed on the upper surface of the encapsulation. In another embodiment, the first terminal 1 is part of the first wiring area of the wiring layer, exposed through a window in the encapsulation. The conductive block can be made of conductive materials such as copper, aluminum, copper-molybdenum alloy, or aluminum silicon carbide.
[0058] Reference Figure 4In existing technologies, in power modules without a Kelvin source, when the power device is turned on, the collector current I of the power device... C Yes, it increases, inducing a voltage with positive polarity at the top and negative polarity at the bottom on the emitter stray inductor Le. This voltage has the same polarity as the externally applied drive voltage, causing V on the internal power device to... GE The gate-emitter voltage (referring to the IGBT transistor) decreases, as shown in the formula below. This alleviates the turn-on process but increases turn-on losses.
[0059] V GE(turn-on) =V gon -R G I G -LedI C / d t
[0060] Among them, V GE(turn-on) This represents the gate-emitter voltage during the turn-on phase, V. gon R represents the drive voltage during the turn-on phase. G I represents the gate drive resistance. G I represents the gate current. C Le represents the collector current, and Le represents the emitter stray inductance.
[0061] Reference Figure 5 This is a schematic diagram of the power device being turned on in this embodiment. The drive circuit and the power circuit are decoupled from each other. The collector current I of the power device... C Changes will not cause power device V GE The change in voltage is shown in the following formula. Compared to a source without Kelvin, this accelerates the turn-on process and reduces turn-on losses.
[0062] V GE(turn-on) =V gon -R G I G
[0063] Reference Figure 6 In existing technologies, in power modules without a Kelvin source, when the power device is turned off, the collector current I of the power device... C This reduction will induce a voltage with negative polarity at the top and positive polarity at the bottom on the emitter stray inductor Le. This voltage has the same polarity as the externally applied drive voltage, causing V on the internal power device to... GE The negative voltage decreases, as shown in the formula below, thereby alleviating the turn-off process and increasing turn-off losses.
[0064] V GE(turn-off) =V goff -R G I G +LedI C / d t
[0065] Among them, V GE(turn-off) V represents the gate-emitter voltage during the turn-off phase. goff This indicates the drive voltage during the turn-off phase.
[0066] Reference Figure 7 This is a schematic diagram of the power device turn-off in this embodiment. The drive circuit and the power circuit are decoupled from each other. The collector current I of the power device... C Changes will not cause power device V GE The change in voltage is shown in the following formula. Compared to a source without Kelvin, this accelerates the turn-off process and reduces turn-off losses.
[0067] V GE(turn-off) =V goff -R G I G
[0068] The power module of this invention greatly reduces the coupling between the power circuit and the drive circuit, and can be considered to have no common source inductor (the structure of the power module in the prior art couples the power circuit and the drive circuit, thus manifesting as a common source inductor).
[0069] The power module in this embodiment significantly reduces the parasitic inductance of parallel chips through low-inductance design both inside and outside the module, while achieving better current sharing characteristics, thereby improving the reliability of the module.
[0070] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A plastic package power module structure, characterized by, The application relates to a power module, comprising: a substrate, a first layer of which is a wiring layer and a second layer of which is an insulating layer, and at least one plastic package covering the upper surface of the wiring layer; the wiring layer comprises a first wiring area and a second wiring area; a first group of chips and a second group of chips are arranged on the substrate; the first group of chips is an upper tube and the second group of chips is a lower tube; the upper tube and the lower tube each contain at least one power device and one freewheeling diode; the power device of the upper tube contains at least a first pole and a second pole; the freewheeling diode of the upper tube contains at least a third pole and a fourth pole; the power device of the lower tube contains at least a fifth pole and a sixth pole; the freewheeling diode of the lower tube contains at least a seventh pole and an eighth pole; at least three power terminals, which are a first terminal, a second terminal and a third terminal; the first terminal is connected with the first pole and the third pole, the second terminal is connected with the sixth pole and the eighth pole, and the third terminal is connected with the second pole, the fourth pole, the fifth pole and the seventh pole; the first pole and the third pole are connected with the first wiring area of the wiring layer through a solder layer, and the fifth pole and the seventh pole are connected with the second wiring area of the wiring layer through a solder layer; the second pole and the fourth pole are connected through a bonding wire and connected with the second wiring area of the wiring layer through a bonding wire, and the sixth pole and the eighth pole are connected through a bonding wire and connected with the second terminal through a bonding wire; the third terminal is led out from a first side of the plastic package, the second terminal is led out from a second side of the plastic package, the first side is opposite to the second side, and the first terminal is led out from the upper surface of the plastic package; a first reference direction is defined as a direction from the second side to the first side; the positive busbar of the first terminal and the negative busbar of the second terminal are led out in the same direction, so that the positive busbar of the first terminal and the negative busbar of the second terminal have an overlapping part.
2. The plastic package power module structure of claim 1, wherein, Based on the first reference direction, the arrangement sequence is the second terminal, the power device of the lower tube, the freewheeling diode of the lower tube, the first terminal, the freewheeling diode of the upper tube, the power device of the upper tube and the third terminal.
3. The plastic package power module structure of claim 2, wherein, The first terminal is composed of two or more sub-terminals, the first wiring area is centrally divided in the first reference direction, and the plurality of sub-terminals of the first terminal fall in different divided areas respectively; current flows from the plurality of sub-terminals of the first terminal to the second pole and the fourth pole through the first pole and the third pole, then flows to the second wiring area of the wiring layer through a bonding wire, then flows through the sixth pole and the eighth pole through the fifth pole and the seventh pole, and finally flows to the second terminal.
4. The plastic package power module structure of claim 1, wherein, The power device of the upper tube is as close to the third terminal as possible under the process allowable condition, and the power device of the lower tube is as close to the second terminal as possible under the process allowable condition.
5. The plastic package power module structure of claim 1, wherein, The first terminal is a conductive block exposed on the upper surface of the plastic package, or the first terminal is a part of the wiring layer exposed in the form of windowing of the plastic package.
6. The plastic package power module structure of claim 5, wherein, The material of the conductive block is copper, aluminum, copper-molybdenum alloy or aluminum silicon carbide.
7. The plastic package power module structure of claim 1, wherein, The bonding wire is an aluminum wire, an aluminum tape, a copper wire or a copper tape.
8. The plastic package power module structure of claim 1, wherein, The power device is a full-controlled power device.