Cascade circuit

Abstract

Described herein is a cascade circuit comprising a controller configured to provide a set of control signals each having a high or low level value, and having a data port, and at least two multiplexers. And at least two multiplexers in a cascade arrangement electrically connected to the controller, respectively, each multiplexer including: a plurality of transmission pins configured to transmit a plurality of transmission signals communicated to the outside, respectively; and an output pin in communication with the data port, the plurality of transfer pins being respectively coupled to the output pin via a multi-way switching element. The respective output pins of the at least two multiplexers are collectively electrically connected to the data port, and signal communication with the data port of the controller is switched between the respective output pins of the at least two multiplexers.

Description

Technical Field

[0001] This disclosure relates to a cascaded circuit, and more specifically, to a circuit based on a plurality of multiplexers arranged in a cascaded manner. Background Technology

[0002] In existing technologies used in data communication, microcontrollers (MCUs) are typically employed as processors for tasks such as data acquisition. Typical applications include analog signal detection or digital signal transmission. If data transmission is performed directly using only the MCU's own data ports (e.g., in pin-based packages), then, for example, n analog signals to be detected would require the resources of n ADC ports on the MCU itself. However, with increasingly complex customer demands, the number of signals required is also increasing, necessitating processors and processing circuits with more port resources, thus increasing design costs. Furthermore, for a large number of signals to be processed, such as exceeding the pin count specified by the MCU, the processor (MCU) cannot simultaneously provide enough pins, such as output pins, to handle so many different operational signals.

[0003] Therefore, additional multiplexing chips are needed to increase the number of pins sufficient to handle multiple signal transmission tasks. These chips are also known as multiplexers (MUX) or data selectors. In related technologies, multiplexer chips are typically used to provide port resources directly to the processor for data acquisition, thereby reducing the number of ports occupied by the processor itself. Furthermore, two or more multiplexer chips can be cascaded as needed to further reduce the number of ports occupied by the processor itself.

[0004] Therefore, in the existing technology, there is an urgent need for an improved cascaded circuit, which can be achieved, for example, through circuit design improvements such as the cascaded design of two or more multiplexer chips, thereby solving the aforementioned problems of saving processor port resources and reducing design costs. Utility Model Content

[0005] The purpose of this disclosure is to provide a simple cascaded circuit that achieves compatibility with both digital and analog signal transmission through a simple and intuitive circuit design using a cascaded design of two or more multiplexer chips, thereby addressing at least one aspect of the aforementioned problems and deficiencies in the prior art, such as saving processor port resources and reducing design costs.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] In a first aspect of this disclosure, a cascaded circuit is provided, comprising a controller and at least two multiplexers. The controller is configured to provide a set of control signals, each having a high or low level value, and has a data port. The at least two multiplexers are arranged in a cascaded configuration, each electrically connected to the controller. Each multiplexer includes: a plurality of transmit pins configured to transmit a plurality of transmit signals connected to an external source; and an output pin connected to the data port, the plurality of transmit pins being connected to the output pin via multiplexing switching elements. The corresponding output pins of the at least two multiplexers are commonly electrically connected to the data port, and the signal communication with the data port of the controller is switched between the respective output pins of the at least two multiplexers.

[0008] In an exemplary embodiment, the circuit has a pre-defined logic function table that covers an exhaustive set of grouped level values ​​of the set of control signals. The at least two multiplexers are configured to look up the logic function table using the set of control signals at a single point in time during the operation of the circuit, and one of the control signals puts at most one multiplexer into an enabled state, thereby switching one of the plurality of transmit pins of the enabled multiplexer to be connected to the output pin.

[0009] In an exemplary embodiment, each multiplexer is a CMOS integrated circuit chip.

[0010] In an exemplary embodiment, each multiplexer is an 8:1 single-channel multiplexer chip.

[0011] In an exemplary embodiment, the set of control signals includes an enable signal and a plurality of addressing signals.

[0012] In an exemplary embodiment, each multiplexer further includes an enable pin and a plurality of addressing pins, the enable pin being configured to switch the corresponding multiplexer between an enabled or disabled state in response to an enable signal received from the controller, and the plurality of addressing pins being configured to receive the plurality of addressing signals respectively.

[0013] In an exemplary embodiment, the respective enable signals of the enable pins of the at least two multiplexers do not simultaneously take valid values ​​that enable the respective multiplexer.

[0014] In an exemplary embodiment, at a single point in time during the operation of the circuit, the at most one multiplexer is enabled by the corresponding enable pin that receives the enable signal from the set of control signals, while the remaining multiplexers are in standby mode.

[0015] In an exemplary embodiment, each multiplexer further includes a decoder electrically connected to the enable pin and the plurality of addressing pins, the decoder having a truth table of grouped level values ​​of the plurality of addressing signals, and the respective truth tables of the grouped level values ​​of the plurality of addressing signals for the respective plurality of addressing pins of the at least two multiplexers, and the high or low level value of the respective enable pin, collectively defining the logic function table; and the decoder is configured to switch one of the plurality of transmit pins of the at most single multiplexer that is in an enabled state to be connected to the output pin.

[0016] In an exemplary embodiment, the corresponding decoder of the at most single multiplexer is configured to select a corresponding transmission signal of one of the plurality of transmission pins to the output pin by using the plurality of addressing signals to look up the truth table to switch one of the plurality of transmission pins to be connected to the output pin.

[0017] In an exemplary embodiment, within each multiplexer, the plurality of transmit pins are connected to the corresponding output pins via the multiplexing element under the control of the decoder.

[0018] In an exemplary embodiment, the at least two multiplexers are n multiplexers of the same specification, and each multiplexer includes one enable pin, one output pin, i transmit pins, and j address pins.

[0019] In an exemplary embodiment, each multiplexer further includes a power supply pin and a ground pin.

[0020] In an exemplary embodiment, compared to the case where the controller directly receives transmitted signals from the outside using only its own ports without multiplexers, the n multiplexers of the circuit collectively save the controller (i-1)*n-(j+1) ports.

[0021] In an exemplary embodiment, the at least two multiplexers are two multiplexers of the same specification.

[0022] In an exemplary embodiment, each multiplexer includes one enable pin, one output pin, eight transmit pins, and three address pins. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help to explain some principles associated with the disclosed embodiments. In the drawings:

[0024] Figure 1This diagram illustrates a schematic block diagram of an MCU in the related art that directly connects to external transmission signals via its own ports.

[0025] Figure 2A and Figure 2B The diagrams show schematic and detailed circuit diagrams of port connections between two cascaded multiplexer chips and an MCU, respectively, according to embodiments of the present disclosure.

[0026] Figure 3A and Figure 3B The diagrams show a port block diagram of an exemplary 8:1 single-channel multiplexer chip and a package diagram with detailed pin definitions. Figure 3C The following is a truth table showing the respective signals for the enable and address pins of an exemplary 8:1 single-channel multiplexer chip.

[0027] Figure 4 The embodiments shown in this disclosure will be based on two such Figure 3A and 3B The exemplary 8:1 single-channel multiplexer chip shown is used for, for example Figure 2A and 2B An exemplary logic function table of the cascaded circuit constructed in the illustrated embodiment.

[0028] Figure 5 This diagram illustrates an extension of the present disclosure to employing n multiplexer chips arranged in a cascaded manner and their port connections to an MCU. Detailed Implementation

[0029] This disclosure will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples to enable those skilled in the art to practice this disclosure. It is important to note that the following drawings and examples are not intended to limit the scope of this disclosure to a single embodiment, but rather to enable other embodiments by means of interchange of some or all of the described or illustrated elements. Furthermore, where certain elements of this disclosure can be implemented using known components in part or entirely, only those portions of such known components necessary for understanding this disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure this disclosure. Unless otherwise stated herein, it will be understood by those skilled in the art that embodiments described as being implemented in software are not intended to be limited to this, but may include embodiments implemented in hardware or a combination of software and hardware, and vice versa. Embodiments showing a singular number of components in this specification should not be considered limiting; rather, unless expressly stated otherwise herein, this disclosure is intended to cover other embodiments including a plurality of identical components, and vice versa. Furthermore, the applicant does not intend for any terminology in this specification or claims to be relegated to an uncommon or particular meaning unless so expressly stated. In addition, this disclosure covers current and future known equivalents of known components mentioned herein with the aid of illustrations.

[0030] Unless otherwise specified, the terms "bottom" and "top," "upper" and "lower," etc., used in this disclosure are relative concepts. Furthermore, the terms "corresponding" or "corresponding" in this disclosure refer to the correspondence between paired, collaboratively working components.

[0031] Figure 1 This diagram illustrates a schematic block diagram of an MCU in the related art that directly connects to external transmission signals via its own ports.

[0032] In such Figure 1In the related technologies shown, for example, a microcontroller, or MCU (Microprogrammed Control Unit), is directly used as a processor for tasks such as data acquisition. In typical applications such as analog signal detection or digital signal transmission, if data transmission is performed directly using only the MCU's own data ports (e.g., in pin-based packages), then, for example, n analog signals to be detected would require the resources of n ADC ports of the MCU itself. For example, in the case of 16-channel signal transmission as shown in the figure, 16 ports of the MCU, namely SI1 to SI16, would be used. However, as customer demands become increasingly complex, the number of signals required also gradually increases, necessitating processors and processing circuits with more port resources, thus increasing design costs. Furthermore, for a large number of signals to be processed, such as exceeding the MCU's pin count specifications, the MCU used cannot simultaneously provide enough pins, such as output pins, to handle so many different operational signals.

[0033] Figure 2A and Figure 2B The diagrams show schematic and detailed circuit diagrams of port connections between two cascaded multiplexer chips and an MCU, respectively, according to embodiments of the present disclosure.

[0034] In one aspect of this disclosure, based on the overall technical concept of this disclosure, such as Figure 2A and Figure 2B As shown, a cascaded circuit is provided, comprising a controller MCU and at least two multiplexers MUX. The controller MCU is configured to provide a set of control signals, each having a high or low level value, and the controller MCU has a data port OUT. The at least two multiplexers MUX are arranged in a cascaded configuration, each electrically connected to the controller, and each multiplexer includes multiple transmit pins (labeled SI1 to SI8 on one MUX and SI9 to SI16 on the other MUX, as described below). Figure 3A and 3B The official specification diagram shows pins s0 to s7, configured to transmit multiple signals connected to the outside; and output pins (labeled OUT on the MUX in the diagram, as described later). Figure 3A and 3B The output pins (corresponding to pin D in the official specification diagram) are connected to the data port, and the plurality of transmission pins are respectively connected to the output pin D via multiplexing elements. For example, the corresponding output pins of the at least two multiplexers (MUX) are commonly electrically connected to the data port, and the signal communication with the data port of the controller is switched between the respective output pins of the at least two multiplexers.

[0035] As an example, with respect to a set of control signals provided by the controller, specifically, for example, in positive logic, a high level value is defined as "1" and a low level value is defined as "0".

[0036] In a further embodiment, as shown in the figure as a specific example, the set of control signals includes, for example, an enable signal for determining which multiplexer to use to signal to the controller's data port, and multiple addressing signals for subsequently determining which transmit pin of the selected multiplexer establishes a transmission channel with the controller's data port, as will be described in detail below.

[0037] This setup enables a simple and intuitive circuit design compatible with both digital and analog signal transmissions, for example, by utilizing a circuit design that cascades two or more multiplexer chips. This solves at least one aspect of the problems and shortcomings of the prior art, such as saving processor port resources and reducing design costs.

[0038] In practical applications, a single MCU controller can be wired to connect multiple single-channel multiplexers 20 simultaneously. See, for example... Figure 2A and Figure 2B , Figure 2A and Figure 2B This is a schematic diagram illustrating the application of two single-channel multiplexers in this disclosure. Here, we still use an exemplary 8:1 single-channel multiplexer chip as an example, based on... Figure 3A and Figure 3B As can be seen from the architecture, each additional single-channel multiplexer will add eight signal paths to the MCU controller, that is, eight external transmission channels are extended to the MCU, thereby saving the MCU's own ports.

[0039] In exemplary embodiments of this disclosure, for example, the at least two multiplexers are typically selected as n multiplexers of the same specification, and each multiplexer includes one enable pin EN, one output pin D, i transmit pins, and j address pins. Further, as an example, each multiplexer also includes one power supply pin and one ground pin.

[0040] In such Figure 2A and 2B In the application scenario, as an example, each multiplexer includes one enable pin, one output pin, eight transmit pins, and three address pins. As an example, each multiplexer is a CMOS integrated circuit chip. Accordingly, in a further embodiment, for example, the at least two multiplexers are, for example, two multiplexers of the same specification, and each multiplexer can be an exemplary multiplexer chip, more specifically, such as an 8:1 single-channel multiplexer chip.

[0041] An exemplary multiplexer chip is a general-purpose complementary metal-oxide-semiconductor (CMOS) multiplexer (MUX). As an example, an exemplary multiplexer chip is an 8:1 single-channel (single-ended) multiplexer. This device can support bidirectional analog and digital signals ranging from GND to VDD on its source (Sx) and drain (Dx) pins.

[0042] The exemplary 8:1 single-channel multiplexer chip features internal current injection control, eliminating the need for external diode and resistor networks (typically used to protect switches and keep input signals within the supply voltage range). The internal current injection control circuitry allows signals on the signal path to be disabled above the supply voltage without affecting signals on the enabled signal path. Furthermore, the exemplary 8:1 single-channel multiplexer chip has no internal diode path to the power pin, eliminating the risk of damaging components connected to the power pin or providing unexpected power to the power rail.

[0043] All logic inputs have thresholds compatible with 1.8V logic, ensuring TTL and CMOS logic compatibility when operating at the effective supply voltage. Fail-protected logic allows voltage to be applied to the control pins first, followed by the power pins, thus protecting the device from potential damage.

[0044] Figure 3A and Figure 3B The diagrams show a schematic block diagram of the ports for an exemplary 8:1 single-channel multiplexer chip and a detailed package schematic showing the pin definitions. These diagrams are derived from the official specification sheet of the exemplary 8:1 single-channel multiplexer chip provided by the chip manufacturer.

[0045] Taking an 8:1 single-channel multiplexer chip as an example, if the chip specification sheet provided by the official manufacturer is available... Figure 3A and Figure 3B As defined, this single-channel multiplexer has, for example, a total of 16 pins. Besides the power supply pin VDD (which, according to official specifications, has a rated voltage range between -0.5V and 6V), eight pins sx (where x is a specific numerical number) are used for data signal transmission, such as s0 to s7 in the diagram. Figure 2A and Figure 2B The pin markings in the diagram are SI1 to SI8, SI9 to SI16, and similar to... Figure 4 The transmission pins marked SI1 to SI8 and SI9 to SI16 in the logic function diagram correspond to the other three pins, A0 to A2, which are addressing pins. Figure 2A and Figure 2B The address pins S0 to S2 of the two cascaded multiplexer chips are labeled, and as follows: Figure 4 The addressing signals of the addressing pins S0 to S2 are marked in the logic function diagram; and there is another pin, EN, which is the enable pin. Other pins include, for example, the empty pin NC (i.e., not connected), the ground pin GND, and the output pin D (as in...). Figure 2A and Figure 2B The output pins of the two cascaded multiplexer chips are labeled OUT, which will not be elaborated on for now.

[0046] Therefore, for example Figure 3A and Figure 3B As shown, the innovation of the overall technical concept of this disclosure lies in using two or more multiplexer chips in a cascaded design as the transmission interface between the MCU and external transmission signals. Then, by switching between the two or more multiplexer chips one by one in a manner similar to chip select, data transmission to the MCU is achieved. This aims to save the MCU's own port resources and reduce design costs.

[0047] Further, in a specific exemplary embodiment according to this disclosure, as shown in the figures, for example, the circuit has a pre-defined logic function table covering an exhaustive set of grouped level values ​​of the set of control signals. The at least two multiplexers are configured to look up the logic function table using the set of control signals at a single point in time during circuit operation, and one of the control signals puts at most one multiplexer into an enabled state, thereby switching one of the plurality of transmit pins of the corresponding multiplexer in the enabled state to be connected to the output pin. As an example, for instance, Figure 4 As shown in the logic function table, the values ​​of the enable signal of the enable pin and the address signal of the address pin are defined in the same way as the truth table. For example, they are both defined as active low, so that the multiplexer MUX where the corresponding enable pin is located is selected and is in signal communication with the data port of the controller MCU, and a signal transmission channel is established between the selected transmit pin and the data port through the addressing operation; and the enable signal of the enable pin is also defined as floating high, so that the multiplexer MUX where the corresponding enable pin is located is disabled but in standby state, and is not in signal communication with the data port of the controller MCU.

[0048] With this configuration, utilizing the set of control signals and based on the pre-built logic function table, the circuit compares the level values ​​in the logic function table to determine the specific multiplexer selected by the controller for signal transmission from at least two multiplexers whose respective output pins are all electrically connected to the controller's data port. This achieves switching between the output pins of the at least two multiplexers and their signal connectivity with the controller's data port, effectively ensuring that at any single point in time during circuit operation, at most only one multiplexer is in a signal-connected state with the controller's data port. In other words, a chip select-like function is achieved in this one-to-many cascaded arrangement of multiple multiplexer MUXs relative to a single controller MCU.

[0049] In a further exemplary embodiment, as an example, as shown in the figure, each multiplexer also includes an enable pin EN and a plurality of addressing pins, such as A0, A1, A2, wherein the enable pin EN is configured to switch the corresponding multiplexer MUX between an enabled or disabled state in response to an enable signal received from the controller MCU, and the plurality of addressing pins are configured to receive the plurality of addressing signals respectively.

[0050] In a specific exemplary embodiment, for example, the corresponding enable signals of the respective enable pins of the at least two multiplexers do not simultaneously take valid values ​​that enable the respective multiplexer. As an example, the enable pin can be active low.

[0051] In a more specific embodiment, for example, at a single point in time during the operation of the circuit, the at most one multiplexer is enabled by the corresponding enable pin that receives the enable signal from the set of control signals, while the remaining multiplexers are in standby mode.

[0052] See back Figure 3A As an example, each multiplexer also includes a decoder electrically connected to the enable pin and the plurality of addressing pins. The decoder has a truth table of grouped level values ​​of the plurality of addressing signals, and the respective truth tables of the grouped level values ​​of the plurality of addressing signals for the respective plurality of addressing pins of the at least two multiplexers, as well as the high or low level value of the respective enable pin, collectively define the logic function table; and the decoder is configured to switch one of the plurality of transmit pins of the at most single multiplexer that is in the enabled state to be connected to the output pin.

[0053] In a further exemplary embodiment, for example, the corresponding decoder of the at most single multiplexer is configured to select a corresponding transmission signal of one of the plurality of transmission pins to the output pin by using the plurality of addressing signals to look up the truth table to switch one of the plurality of transmission pins to be connected to the output pin.

[0054] And as Figure 3A As shown, as an example, within each multiplexer, the plurality of transmit pins are connected to the corresponding output pins via the multiplexing switching element under the control of the decoder.

[0055] Figure 3C The following is a truth table showing the respective signals for the enable and address pins of an exemplary 8:1 single-channel multiplexer chip. Figure 4 As shown Figure 2A and 2B An exemplary logic function table of an exemplary 8:1 single-channel multiplexer chip in the illustrated embodiment.

[0056] The following explains in detail that by controlling the status of the MCU control signals used for the address pins A0 to A2 and the enable pin EN of each multiplexer chip, i.e. the signal values, the control signals connected from the MCU to the address pins A0 to A2 and the enable pin EN can be used to control which multiplexer is used to connect the signal to the controller's data port, and thus determine which transmission pin of the selected multiplexer establishes a transmission channel with the controller's data port.

[0057] It should be noted that Figure 3C In each exemplary 8:1 single-channel multiplexer chip, the enable pin is active low, meaning it is active when the enable signal sent from the controller to the enable pin is low (i.e., a low logic input, with a value of 0); conversely, when the enable signal of this enable pin is as follows: Figure 3C As shown, when the high logic input is 1, all internal switches are turned off. This characteristic of this exemplary 8:1 single-channel multiplexer chip results in the controller selecting the corresponding exemplary 8:1 single-channel multiplexer chip with an active-low EN pin to establish a signal connection between the drain (output pin D) of the multiplexer chip and the controller's data port.

[0058] Subsequently, the enable signal of the selected multiplexer's enable pin also determines the transmission pin that needs to establish a connection with the MCU's data port, thus completing the addressing. Conversely, if the enable signal of the enable pin is as follows... Figure 3CAs shown, when the high logic input is 1, all internal switches are turned off. Therefore, based on the multiple addressing signals sent by the controller to the addressing pins A0 to A2 of the selected multiplexer chip, a specific transmission pin (s0 to s7) is selected to establish a signal transmission channel between the selected transmission pin and the data port OUT, thus establishing a signal transmission channel between the selected transmission pin and the data port OUT.

[0059] In this way, by comparing a set of control signals with a logic function table, a two-step gating function for establishing specific signal paths is achieved. This facilitates optimized circuit design that expands the port resources of the MCU controller through simple circuit hardware layout and wiring connections, as well as simple signal path settings.

[0060] And it should be noted that, Figure 4 The logic function table illustrates the exhaustive combinations of grouped control signal values ​​for a cascaded circuit using two multiplexers. Within this table, the signal values ​​corresponding to the three addressing terminals A0 to A2 of each multiplexer are labeled S0 to S2, the signal value corresponding to the output pin D of each multiplexer is labeled output, and the signal values ​​corresponding to the enable pins of the two multiplexers are labeled EN1 and EN2, respectively. In this logic function table, the specific value for each pin is either 0 or 1.

[0061] In specific exemplary embodiments, for example, at least two multiplexers, typically such as Figure 3A and Figure 3B The diagram shows two multiplexers that utilize control signals from the MCU connected to their respective address pins S0 to S2 and enable pin EN to communicate with... Figure 4 The various control signal combinations listed in the logic function table are compared and searched to determine the corresponding value combinations. Based on the determined combinations, the two multiplexers respectively execute predetermined actions corresponding to the value combinations. As an example, in each multiplexer, 8 transmit pins (such as s0 to s7 in the specification diagram) can correspond to a total of 8 value combinations, and 8 different data signals can be transmitted through the 8 transmit pins to compensate for the problem of excessive occupation of the port resources of the MCU controller itself.

[0062] Thus, in the cascaded circuit according to an exemplary embodiment of the present disclosure, based on such Figure 4 As shown in its logical function table, in such a case... Figure 2A and 2BIn the application scenario of using two exemplary 8:1 single-channel multiplexer chips, when the enable signal of the enable pin EN1 of the multiplexer chip in the upper part of the figure is in a valid state, the multiplexer chip in the upper part of the figure (hereinafter referred to as the first multiplexer) is selected; while the enable pin EN2 of the multiplexer chip in the lower part of the figure (hereinafter referred to as the second multiplexer chip) is not selected because it is in the opposite state.

[0063] Then, continue with the subsequent steps based on the logical function table, specifically as follows: Figure 3C As shown, based on the truth table in the built-in decoder of the first multiplexer, all transmission pins of the first multiplexer are further determined. Figure 2A and Figure 2B The numbers SI1 to SI8 are consistent with those provided in the official specifications. Figure 3A and Figure 3B Which specific transmission pin (corresponding to transmission pins s0 to s7) is connected to its output pin D, that is, the switch between the selected specific transmission pin and the output pin D is connected, thereby establishing a signal connection between the selected specific transmission pin and the data port of the controller via the output pin D, thus establishing a signal transmission channel between the selected transmission pin and the data port.

[0064] In another scenario, when the enable signal of the second multiplexer chip (EN2) in the lower part of the diagram is active, the second multiplexer chip is selected; while the enable pin EN1 of the first multiplexer chip (EN1) in the upper part of the diagram is not selected because it is in the opposite state. Subsequently, the following steps are performed based on the logic function table, specifically as follows: Figure 3C As shown, based on the truth table in the built-in decoder of the second multiplexer, all transmission pins of the second multiplexer are further determined. Figure 2A and Figure 2B The Chinese label is marked SI9 to SI16, which is consistent with the standard specifications provided. Figure 3A and Figure 3B Which specific transmission pin (corresponding to transmission pins s0 to s7) is connected to its output pin D, that is, the switch between the selected specific transmission pin and the output pin D is connected, thereby establishing a signal connection between the selected specific transmission pin and the data port of the controller via the output pin D, thus establishing a signal transmission channel between the selected transmission pin and the data port.

[0065] With this setup, a chip select-like function can be implemented with a simple circuit layout based on the enable signal sent by the MCU to the enable pin of the multiplexer, so as to facilitate switching between different multiplexers and effectively expand the MCU's ports.

[0066] The embodiments disclosed herein are not limited to, for example Figure 3A and Figure 3B The scenario shown, which uses only two multiplexers, can be further extended to scenarios using more than two multiplexers.

[0067] Figure 5 This diagram illustrates the port connections of an MCU to n multiplexer chips MUX1 to MUXn arranged in a cascaded configuration, according to an embodiment of this disclosure. The enable pins of each of the n multiplexer chips MUX1 to MUXn are labeled EN1 to ENn.

[0068] According to exemplary embodiments of this disclosure, such as Figure 5 As shown, for example, a chip select function can be implemented by using the enable pins of multiple multiplexer chips to ensure that only a single multiplexer chip and the MCU controller are transmitting signals at any given time.

[0069] like Figure 5 As shown, as an example, the at least two multiplexers are n multiplexers of the same specification, and each multiplexer includes one enable pin EN, one output pin D, i transmit pins, and j address pins.

[0070] Thus, firstly, for each additional multiplexer used, due to the i transmission pins it provides, i transmission channels directly connected to the MCU's own ports can be reduced accordingly. Simultaneously, it must be considered that each multiplexer's enable pin needs to be electrically connected to a corresponding terminal of the MCU, meaning each multiplexer's enable pin occupies a corresponding port of the MCU. In other words, the number of MCU terminals saved by each multiplexer is (i-1). Therefore, the total number of MCU terminal resources saved by n multiplexers is (i-1)*n.

[0071] Furthermore, considering the MCU itself, the MCU controller also provides several common terminals shared by each multiplexer, including: j addressing ports shared by the multiple multiplexers, each connected to j addressing pins of each multiplexer; and an output port shared by the multiple multiplexers, which is connected to the drain (output pin D) of each multiplexer. Thus, the redundant port usage of the MCU itself due to providing addressing and enable signals is (j+1).

[0072] In conclusion, compared to directly receiving transmitted signals from the outside using only the controller's own ports without multiplexers, the n multiplexers in this circuit collectively save the controller (i-1)*n-(j+1) ports. In other words, this circuit of multiple multiplexers arranged in a cascaded configuration results in a total port saving of (i-1)*n-(j+1) for the MCU.

[0073] As an example, in the case where multiple multiplexers (MUXs) all employ the same exemplary 8:1 single-channel multiplexer chip, each multiplexer includes one enable pin (EN), one output pin (D), eight transmit pins, and three address pins. In other words, in this case, i=8, j=3, the circuitry of multiple exemplary 8:1 single-channel multiplexer chips arranged in a cascaded manner results in a total port saving of 7n-4 for the MCU.

[0074] In exemplary embodiments according to this disclosure, for example, the transmitted data signals are categorized into digital signals and analog signals based on the characteristics of the input signals. Signals of the same type, such as transmitted signals that are all digital signals, can be designed using a cascaded multiplexer chip; or alternatively, transmitted signals that are all digital signals can also be designed using a cascaded multiplexer chip. This saves processor port resources and reduces design costs.

[0075] In one specific embodiment, as an example, the transmission signals, all of which are analog signals, are input to the multiplexer chip. Then, through the chip cascading arrangement, each chip is selected using its own enable signal. Then, the addressing signals S0, S1, and S2 control the output of the transmission signal to OUT to the MCU.

[0076] In another alternative embodiment, as an example, the transmission signal of the digital signal is output to the device, controlled by the enable signal, and then the data port OUT signal of the MCU controller is connected to which output pin of the multiplexer chip by the addressing signals S0, S1, S2.

[0077] With this design, since the exemplary 8:1 single-channel multiplexer chip can support bidirectional analog and digital signals from GND to VDD on the source (Sx) and drain (Dx) pins, this cascaded circuit based on multiple multiplexer chips arranged in a cascaded manner can be compatible with transmission signals that are all analog signals or all digital signals, thereby expanding the application range.

[0078] Based on the cascaded circuit comprising multiple multiplexer chips arranged in a cascaded manner as described above, the following superior technical effects compared to existing technical solutions in the art can be achieved:

[0079] For example, improvements in circuit design, such as cascading two or more exemplary 8:1 single-channel multiplexer chips, achieve the intended goals of saving processor port resources and reducing design costs. By comparing a set of control signals provided by the MCU with the logic function table built into the multiplexer chip, a two-step signal path selection function is achieved. This facilitates optimized circuit design that expands the port resources of the MCU controller through simple circuit hardware layout and wiring connections, as well as simple signal path settings. Furthermore, based on the enable signal sent by the MCU to the multiplexer's enable pin, a chip select-like function can be implemented with a simple circuit layout to facilitate switching between different multiplexers, thereby effectively expanding the MCU's ports. Furthermore, since the exemplary 8:1 single-channel multiplexer chip can support bidirectional analog and digital signals ranging from GND to VDD on the source (Sx) and drain (Dx) pins, this cascaded circuit based on multiple multiplexer chips arranged in a cascaded manner can be compatible with transmission signals that are all analog signals or all digital signals, thereby expanding the application range.

[0080] The above description of the cascaded circuits in the foregoing embodiments of this disclosure is intended to be illustrative and not restrictive. Although this disclosure has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to exemplify preferred embodiments of this disclosure and should not be construed as limiting this disclosure.

[0081] Therefore, those skilled in the art will understand that the embodiments described above are exemplary and can be improved by those skilled in the art. The structures described in the various embodiments can be modified and freely combined without conflict in structure or principle, and these changes should fall within the protection scope of this disclosure.

[0082] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined only by the following claims and their equivalents.

[0083] It should be noted that the word "comprising" does not exclude other elements or steps, and the words "a" or "an" do not exclude multiple. Furthermore, any element reference numerals in the claims should not be construed as limiting the scope of this disclosure.

Claims

1. A cascaded circuit comprising: a controller (MCU) configured to provide a set of control signals each having a high or low level value, and having a data port (OUT); and at least two multiplexers (MUX) in a cascaded arrangement each electrically connected to the controller, and each multiplexer comprising: a plurality of pass-through pins (s0, s1, s2, s3, s4, s5, s6, s7) configured to pass-through a plurality of pass-through signals each to an outside; and an output pin (D) in communication with the data port, the plurality of pass-through pins being coupled to the output pin (D) via a multiplexing switch element each; characterized in that, the respective output pins (D) of the at least two multiplexers (MUX) are collectively electrically connected to the data port (OUT), and signal communication with the data port (OUT) of the controller (MCU) is switched between the respective output pins (D) of the at least two multiplexers (MUX). the circuit is pre-provisioned with a logic function table encompassing an exhaustive set of the set of level values of the set of control signals, the at least two multiplexers (MUX) are configured to look up the logic function table by utilizing the set of control signals at a single point in time during operation of the circuit, and at most a single multiplexer (MUX) is brought into an active state by one of the set of control signals, whereby one of the plurality of pass-through pins of the respective multiplexer in the active state is switched into communication with the output pin.

2. The circuit of claim 1, wherein, each multiplexer is a CMOS integrated circuit chip.

3. The circuit of claim 1, wherein, each multiplexer is an 8: 1 single-channel multiplexer chip.

4. The circuit of claim 3, wherein, the set of control signals comprises an enable signal and a plurality of address signals.

5. The circuit of claim 2, wherein, each multiplexer further comprises an enable pin (EN) configured to switch the respective multiplexer between an active or inactive state in response to the enable signal received from the controller (MCU), and a plurality of address pins (A0, A1, A2) configured to receive the plurality of address signals respectively.

6. The circuit of claim 5, wherein, the respective enable signals of the respective enable pins (EN) of the at least two multiplexers (MUX) are not simultaneously taken such that the respective multiplexers are in the active state.

7. The circuit of claim 6, wherein, at a single point in time during operation of the circuit, a single multiplexer is brought into the active state by the respective enable pin receiving the enable signal of the set of control signals, while the remaining multiplexers are in a standby state.

8. The circuit of claim 7, wherein, each multiplexer (MUX) further comprises a decoder (DECODER) electrically connected to the enable pin and the plurality of address pins (A0, A1, A2), the decoder having a truth table of the set of level values of the plurality of address signals, and the respective truth tables of the set of level values of the plurality of address signals for the respective plurality of address pins, and the high or low level value of the respective enable pin of the at least two multiplexers collectively define the logic function table; and 9. The circuit of claim 8, wherein, ​ The decoders (DECODER) are configured to switch one of the plurality of pass-through pins (s0, s1, s2, s3, s4, s5, s6, s7) of the single multiplexer in the enabled state into communication with the output pin (D).

10. The circuit of claim 9, wherein, The respective decoders (DECODER) of the single multiplexer are configured to strobe the respective pass-through signal of one of the plurality of pass-through pins (s0, s1, s2, s3, s4, s5, s6, s7) to the output pin (D) by looking up the truth table against the plurality of address signals to switch one of the plurality of pass-through pins into communication with the output pin (D).

11. The circuit of claim 9 or 10, characterized in that, Within each multiplexer (MUX), the plurality of pass-through pins are coupled to the respective output pin (D) via the multiplexing switching element under control of the decoder.

12. The circuit of claim 6, wherein, The at least two multiplexers (MUX) are n multiplexers of the same specification, and each multiplexer includes 1 enable pin (EN), 1 output pin (D), i pass-through pins, and j address pins.

13. The circuit of claim 12, wherein, Each multiplexer further includes 1 power pin (VDD) and 1 ground pin (GND).

14. The circuit of claim 12, wherein, The n multiplexers of the circuit collectively save the controller (i-1)*n-(j+1) number of ports compared to a case where only the ports of the controller itself directly receive pass-through signals from the outside without the multiplexers.

15. The circuit of claim 12, wherein, The at least two multiplexers are 2 multiplexers of the same specification.

16. The circuit of claim 12, wherein, Each multiplexer includes 1 enable pin, 1 output pin, 8 pass-through pins, and 3 address pins.

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