Pulse sequence type image sensor and electronic equipment

Abstract

The utility model provides a pulse sequence type image sensor. The pulse sequence type image sensor comprises a pixel module and a reading module, the pixel module comprises more than two pixels, and the pixels are divided into a first group and a second group; the reading module comprises a first comparator, a second comparator and a mode switching sub-module, and is configured as follows: when the mode switching sub-module works in a first state, pixels in the pixel module are respectively connected with the first comparator and the second comparator; the reference signal of the first comparator is larger than that of the second comparator, and the reference signal of the second comparator is equal to the threshold value of the electric signal; and when the mode switching sub-module works in a second state, the pixels in the first group are connected with the first comparator, the pixels in the second group are connected with the second comparator, and the reference signals of the first comparator and the second comparator are equal to the threshold value of the electric signal. The utility model also provides an electronic device. The pulse sequence type image sensor provided by the utility model has a better signal to noise ratio.

Description

Technical Field

[0001] This utility model relates to the field of image sensor technology, and in particular to a pulse sequence image sensor and electronic device. Background Technology

[0002] During the operation of an image sensor, each pixel reset introduces random reset noise, and noise is also introduced into the transmission path of reading the pixel signal (i.e., the electrical signal formed by photoelectric conversion) from the pixel to the column circuit. The presence of these noises directly affects the image quality of the image sensor.

[0003] To suppress this noise, a traditional 4T pixel (i.e., four-transistor pixel) first retains the photogenerated charge in the photodiode after exposure, resets the floating diffusion region, and samples the reset signal from the floating diffusion region to the column-level circuit. Then, by controlling the conduction of the transfer transistor, the photogenerated charge on the photodiode is transferred to the floating diffusion region, and the photosensitive signal from the floating diffusion region is sampled to the column-level circuit. Finally, the two signals sampled to the column-level circuit are differentially divided. Differentially dividing the two signals effectively eliminates noise introduced during pixel reset and in the pixel signal transmission path. As a result, subsequent processing of the differential signal can form a high-quality image.

[0004] Compared to traditional 4T pixels, traditional pulse sequence pixels lack floating diffusion regions and transfer transistors, so they cannot effectively suppress noise introduced during the pixel reset process and in the pixel signal transmission path, resulting in poor image quality of pulse sequence image sensors based on traditional pulse sequence pixels. Utility Model Content

[0005] To overcome the aforementioned deficiencies in the prior art, this utility model provides a pulse sequence image sensor, which includes:

[0006] A pixel module and a readout module connected to the pixel module;

[0007] The pixel module includes two or more pixels, which are divided into a first group and a second group. Each pixel includes a photoelectric conversion unit for converting optical signals into electrical signals.

[0008] The readout module includes a first comparator, a second comparator, and a mode switching submodule, wherein the first comparator, the second comparator, and the mode switching submodule are configured as follows:

[0009] When the mode switching submodule is working in the first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0010] When the mode switching submodule is operating in the second state, each pixel in the first group is connected to the first comparator, each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold of the electrical signal.

[0011] According to one aspect of the present invention, in the pulse sequence image sensor, the pulse sequence image sensor includes a pixel array and a readout circuit; each column of pixels in the pixel array constitutes a pixel module; the readout circuit includes readout modules that are the same number as the number of pixel modules and correspond one-to-one, and each readout module is connected to its corresponding pixel module.

[0012] According to another aspect of the present invention, in the pulse sequence image sensor, the pixels in each column of pixels located in odd-numbered rows are divided into one group of the first group and the second group, and the pixels located in even-numbered rows are divided into the other group of the first group and the second group.

[0013] According to another aspect of the present invention, in the pulse sequence image sensor, each pixel includes an input terminal for receiving a reset signal and an output terminal for outputting the electrical signal; the connection of each pixel in the pixel module to the first comparator and the second comparator includes: the output terminal of each pixel in the pixel module is connected to the negative input terminal of the first comparator and the negative input terminal of the second comparator, respectively, and the input terminal of each pixel in the pixel module is connected to the output terminal of the second comparator; the connection of each pixel in the first group to the first comparator and each pixel in the second group to the second comparator includes: the output terminal of each pixel in the first group is connected to the negative input terminal of the first comparator, the input terminal of each pixel in the first group is connected to the output terminal of the first comparator, the output terminal of each pixel in the second group is connected to the negative input terminal of the second comparator, and the input terminal of each pixel in the second group is connected to the output terminal of the second comparator.

[0014] According to another aspect of the present invention, in the pulse sequence image sensor, each pixel further includes a signal output section and a reset section; the photoelectric conversion section is used to convert an optical signal into an electrical signal; the signal output section is used to output the electrical signal, wherein a first end of the signal output section is connected to the photoelectric conversion section, and a second end of the signal output section serves as the output end of the pixel; the reset section is used to reset the photoelectric conversion section according to the reset signal, wherein a first end of the reset section is connected to the photoelectric conversion section, and a second end of the reset section serves as the input end of the pixel.

[0015] According to another aspect of the present invention, in the pulse sequence image sensor, the photoelectric conversion unit includes a photodiode, wherein the positive terminal of the photodiode is grounded, and the negative terminal of the photodiode is connected to the first terminal of the signal output unit and the first terminal of the reset unit; the electrical signal is the negative terminal voltage signal of the photodiode.

[0016] According to another aspect of the present invention, in this pulse sequence image sensor, the signal output section includes a source follower transistor and a pixel selection transistor; the first terminal of the source follower transistor is connected to a power supply, the second terminal of the source follower transistor is connected to the first terminal of the pixel selection transistor, and the third terminal of the source follower transistor serves as the first terminal of the signal output section and is connected to the negative terminal of the photodiode; the second terminal of the pixel selection transistor serves as the second terminal of the signal output section and is connected to the corresponding readout module, and the third terminal of the pixel selection transistor is used to receive a first control signal controlling its conduction or deactivation; wherein, when the pixel selection transistor is turned on, the source follower transistor outputs the negative voltage signal of the photodiode it reads to the corresponding readout module through the pixel selection transistor.

[0017] According to another aspect of the present invention, in the pulse sequence image sensor, the reset unit includes a reset transistor and a reset selection transistor; the first terminal of the reset transistor is connected to a power supply, the second terminal of the reset transistor serves as the first terminal of the reset unit and is connected to the negative terminal of the photodiode, and the third terminal of the reset transistor is connected to the second terminal of the reset selection transistor; the first terminal of the reset selection transistor serves as the second terminal of the reset unit and is connected to the corresponding readout module, and the third terminal of the reset selection transistor is used to receive a second control signal that controls its conduction or deactivation; wherein, when the first terminal of the reset selection transistor receives the reset signal and the reset transistor is turned on, the reset transistor resets the photodiode according to the reset signal.

[0018] According to another aspect of the present invention, in this pulse sequence image sensor, the mode switching submodule includes a first electrical signal output line, a second electrical signal output line, a first reset signal input line, a second reset signal input line, a first switch, a second switch, and a third switch; the output terminals of the pixels in the first group are connected to the negative input terminal of the first comparator via the first electrical signal output line, and the output terminals of the pixels in the second group are connected to the negative input terminal of the second comparator via the second electrical signal output line; the first switch is disposed between the first electrical signal output line and the second electrical signal output line; the input terminals of the pixels in the first group are connected to the negative input terminal of the second comparator via the first reset signal input line. The input line is connected to the output terminal of the first comparator. The input terminal of the pixel in the second group is connected to the output terminal of the second comparator through the second reset signal input line. The second switch is disposed between the first reset signal input line and the second reset signal input line. The third switch is disposed on the first reset signal input line and located between the second switch and the first comparator. When both the first switch and the second switch are turned on and the third switch is turned off, the mode switching submodule operates in the first state. When both the first switch and the second switch are turned off and the third switch is turned on, the mode switching submodule operates in the second state.

[0019] This utility model also provides a pulse sequence image sensor, which includes:

[0020] A pixel module and a readout module connected to the pixel module;

[0021] The pixel module includes two or more pixels, and each pixel includes a photoelectric conversion unit for converting optical signals into electrical signals;

[0022] The readout module includes a first comparator, a second comparator, and a signal line submodule. Each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line submodule. The first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0023] This invention also provides an electronic device, which includes the aforementioned pulse sequence image sensor.

[0024] The pulse sequence image sensor provided by this invention includes a pixel module and a readout module connected to the pixel module. The pixel module includes two groups of pixels, and the readout module includes two comparators and a mode switching submodule. The readout module is configured to enable the pulse sequence image sensor to operate in a first pulse sequence output mode and a second pulse sequence output mode. When the pulse sequence image sensor operates in the first pulse sequence output mode, the pixel signal of each pixel in the pixel module is transmitted to the two comparators respectively, and the reference signals of the two comparators are set to be unequal. Subsequently, only differential operations need to be performed on the pulse sequences output by the two comparators to eliminate pixel reset noise and noise introduced in the pixel signal transmission path, thereby effectively improving the signal-to-noise ratio performance of the image sensor and thus improving the image quality. When the pulse sequence image sensor operates in the second pulse sequence output mode, the pixel signal of the first group of pixels in the pixel module is transmitted to the first comparator, and the pixel signal of the second group of pixels is transmitted to the second comparator. The first and second comparators operate in parallel, allowing the pixel signals of the two groups of pixels to be read out in parallel. Compared to existing technologies where pixel signals in a pixel module can only be read out one by one, implementing this invention improves the readout efficiency of pixel signals, thereby increasing the frame rate of the pulse sequence image sensor. In other words, in applications requiring high signal-to-noise ratio, the pulse sequence image sensor provided by this invention can operate in the first pulse sequence output mode; in applications requiring high frame rate, it can operate in the second pulse sequence output mode. Electronic devices based on the pulse sequence image sensor provided by this invention also exhibit superior performance. Attached Figure Description

[0025] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a circuit diagram of a column of pixels and its corresponding readout module in a pulse sequence image sensor according to a specific embodiment of the present invention.

[0027] Figure 2 This is a circuit diagram of a column of pixels and its corresponding readout module in a pulse sequence image sensor according to another specific embodiment of the present invention.

[0028] Figure 3 yes Figure 2 The diagram shown is the equivalent circuit of the structure operating in the first pulse sequence output mode.

[0029] Figure 4 yes Figure 2 The diagram shown is the equivalent circuit diagram of the structure operating in the second pulse sequence output mode.

[0030] Figure 5 yes Figure 2 The timing diagram of the structure shown is in the first pulse sequence output mode.

[0031] Figure 6 yes Figure 2 The diagram shows the timing of the structure in the second pulse sequence output mode.

[0032] The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0033] To better understand and explain this utility model, a further detailed description of this utility model will be provided below in conjunction with the accompanying drawings.

[0034] This invention provides a pulse sequence image sensor, which includes:

[0035] A pixel module and a readout module connected to the pixel module;

[0036] The pixel module includes two or more pixels, which are divided into a first group and a second group. Each pixel includes a photoelectric conversion unit for converting optical signals into electrical signals.

[0037] The readout module includes a first comparator, a second comparator, and a mode switching submodule, wherein the first comparator, the second comparator, and the mode switching submodule are configured as follows:

[0038] When the mode switching submodule is working in the first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and the first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0039] When the mode switching submodule is operating in the second state, each pixel in the first group is connected to the first comparator, each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold of the electrical signal.

[0040] The components of the aforementioned pulse sequence image sensor will be described in detail below.

[0041] Specifically, the pulse sequence image sensor provided by this utility model includes a pixel module and a readout module connected to the pixel module. The pixel module includes two or more pixels, wherein each pixel includes a photoelectric conversion unit for converting optical signals into pixel signals (i.e., electrical signals). The readout module is used to read the pixel signals of the pixels in the pixel module connected to it.

[0042] In this embodiment, the number of pixel modules and readout modules in the pulse sequence image sensor provided by this utility model is N, where N is an integer and N≥1. The N pixel modules constitute the pixel array of the pulse sequence image sensor, and the N readout modules constitute the readout circuit of the pulse sequence image sensor. In this embodiment, the N pixel modules in the pixel array and the N readout modules in the readout circuit correspond one-to-one, and the corresponding pixel modules and readout modules are connected. Furthermore, in this embodiment, each pixel includes an input terminal and an output terminal, where the input terminal is used to receive the pixel's reset signal, and the output terminal is used to output the pixel signal. It should be noted that (1) this utility model does not limit how the pixel array is divided to obtain pixel modules. In a preferred embodiment, the pixel array is divided in columns, with each column being considered as a pixel module. In other embodiments, other methods can be used to divide the pixel array. Taking a pixel array comprising 4 rows × 4 columns of pixels as an example, the pixel array can be divided into 4 pixel modules, each pixel module comprising 2 rows × 2 columns of pixels. For the sake of simplicity, all the ways of dividing the pixel module will not be listed here. (2) When there are two or more pixel modules, the number of pixels in each pixel module is preferably the same, but they can also be different. This utility model does not limit this. (3) This utility model does not limit the specific structure of the pixel. Any photoelectric conversion structure that has the above-mentioned input end and output end and can be used in an image sensor is applicable to the pixel in this utility model. For the sake of simplicity, all possible structures of the pixel will not be listed here. All pixels in the pixel array preferably have the same structure, but they can also be different. This utility model does not limit this. The following will use the example of all pixels in the pixel array having the same structure as an example.

[0043] In this embodiment, the pixels in each pixel module are further divided into two groups, referred to below as the first group and the second group, respectively. Preferably, the number of pixels in the first group and the second group are equal or as close as possible. Specifically, when the pixel module includes an even number of pixels, the number of pixels in the first group and the second group are the same; when the pixel module includes an odd number of pixels, the number of pixels in the first group and the second group differs by one. Those skilled in the art will understand that, depending on actual design requirements, the number of pixels in the first group and the second group may also be different, and this utility model does not impose any limitations on this. Furthermore, this utility model does not impose any limitations on which pixels are specifically included in the first group and the second group. The following description takes the case where each column of pixels is considered as a pixel module, and the number of pixels in the first group and the second group are equal or as close as possible. In one specific embodiment, pixels in the odd-numbered rows of each column are divided into the first group, and pixels in the even-numbered rows of each column are divided into the second group; or pixels in the even-numbered rows of each column are divided into the first group, and pixels in the odd-numbered rows of each column are divided into the second group. In another specific embodiment, the pixels in the first half of each column are divided into a first group, and the pixels in the second half of each column are divided into a second group. For the sake of simplicity, all the possibilities of the first and second groups will not be listed here.

[0044] In this embodiment, each readout module reads the pixel signal of each pixel in its corresponding pixel module and outputs it as a signal in the form of a pulse sequence. The readout module includes a first comparator, a second comparator, and a mode switching submodule, and the first comparator, second comparator, and mode switching submodule are configured as follows:

[0045] When the mode switching submodule operates in the first state, each pixel in the pixel module corresponding to the readout module is connected to a first comparator and a second comparator, respectively. The reference signal of the first comparator (hereinafter referred to as the first reference signal) is set to be greater than the reference signal of the second comparator (hereinafter referred to as the second reference signal), and the second reference signal of the second comparator is set to be equal to a threshold of the pixel signal. In a specific embodiment, connecting each pixel in the pixel module corresponding to the readout module to the first comparator and the second comparator includes: the output terminal of each pixel in the pixel module is connected to the negative input terminal of the first comparator and the negative input terminal of the second comparator, respectively; the input terminal of each pixel in the pixel module is connected to the output terminal of the second comparator; the positive input terminal of the first comparator receives the first reference signal; and the positive input terminal of the second comparator receives the second reference signal.

[0046] When the mode switching submodule operates in the second state, the first group of pixels in the pixel module corresponding to the readout module is connected to the first comparator, and the second group of pixels in the pixel module corresponding to the readout module is connected to the second comparator. The first reference signal of the first comparator and the second reference signal of the second comparator are both set to be equal to the threshold of the pixel signal. In one specific embodiment, connecting the first group of pixels in the pixel module corresponding to the readout module to the first comparator and the second group of pixels in the pixel module corresponding to the readout module to the second comparator includes: the output terminal of each pixel in the first group is connected to the negative input terminal of the first comparator; the input terminal of each pixel in the first group is connected to the output terminal of the first comparator; the output terminal of each pixel in the second group is connected to the negative input terminal of the second comparator; the input terminal of each pixel in the second group is connected to the output terminal of the second comparator; the positive input terminal of the first comparator receives the first reference signal; and the positive input terminal of the second comparator receives the second reference signal.

[0047] It should be noted that (1) this utility model does not impose any restrictions on the specific structure of the first comparator and the second comparator. Any device or circuit that can realize the comparison function is applicable to this utility model. For the sake of brevity, they will not be listed one by one here. (2) In a specific embodiment, the mode switching submodule includes a signal line submodule and a switch submodule. The signal line submodule includes signal lines for connecting each pixel in the pixel module to the comparator. The switch submodule includes switching elements for controlling the on / off / short-circuit states of the signal lines in the signal submodule. Those skilled in the art will understand that the above is only a preferred embodiment of the mode switching submodule and should not be construed as a limitation on the structure of the mode switching submodule. Any structure that can enable the pixels in the pixel module to switch between the corresponding comparators in the above two connection methods is applicable to the mode switching submodule in this utility model. For the sake of brevity, all possible structures of the mode switching submodule will not be listed one by one here. (3) When the pixel signal of a pixel reaches a certain value, the pixel needs to be reset. This value is the threshold of the pixel signal. Typically, the pixel signal of a pixel is a voltage signal formed through photoelectric conversion, and the corresponding threshold of the pixel signal is the threshold voltage. For a pixel, as the exposure time increases, the voltage signal formed by photoelectric conversion gradually decreases until the voltage signal drops to the threshold voltage, at which point the pixel is reset. The following document will illustrate this using the example of a pixel signal being a voltage signal formed through photoelectric conversion.

[0048] Regarding the pulse sequence image sensor provided by this utility model, when all mode switching submodules in the readout modules are working in the first state, the working mode of the pulse sequence image sensor is referred to as the first pulse sequence output mode; when all mode switching submodules in the readout modules are working in the second state, the working mode of the pulse sequence image sensor is referred to as the second pulse sequence output mode.

[0049] When the pulse sequence image sensor operates in the first pulse sequence output mode, the readout module reads the pixel signal of each pixel in its corresponding pixel module one by one in each frame. For each pixel, after reset, its pixel signal is usually close to the power supply voltage. As the exposure time increases, due to the accumulation of photogenerated charge, the pixel signal gradually decreases. Since the first reference signal of the first comparator is greater than the second reference signal of the second comparator, the pixel signal first drops to the first reference signal and triggers the first comparator to output a high-level pulse signal. When the pixel signal continues to drop to the second reference signal (i.e., the pixel signal threshold), it triggers the second comparator to output a high-level pulse signal. This high-level pulse signal can be used to trigger the pixel to reset. After reset, the pixel continues to be exposed, and this cycle repeats. In subsequent processing of the pulse sequences output by the first and second comparators, for each pixel, the time difference between triggering the high-level pulse signal output by the first comparator and the high-level pulse signal output by the second comparator in each exposure is calculated (the length of this time difference expresses the intensity of light, with a shorter time difference indicating stronger light and a longer time difference indicating weaker light). An image is then formed based on this time difference. Since the voltage difference between the first and second reference signals is fixed, even if noise is introduced during pixel reset and pixel signal transmission, it will not affect the time it takes for the pixel signal to drop from the first reference signal to the second reference signal. In this way, the noise introduced during pixel reset and pixel signal transmission can be effectively eliminated, which is beneficial to improving the signal-to-noise ratio performance of the pulse sequence image sensor.

[0050] When the pulse sequence image sensor operates in the second pulse sequence output mode, in each frame, the first comparator reads out the pixel signals of each pixel in the first group one by one, and the second comparator reads out the pixel signals of each pixel in the second group one by one. For each pixel in the first group, as the exposure time increases, when the pixel signal drops to the first reference signal (i.e., the pixel signal threshold), the first comparator outputs a high-level pulse. This high-level pulse can be used to trigger the pixel to reset, and after the pixel resets, exposure continues, and so on. Similarly, for each pixel in the second group, as the exposure time increases, when the pixel signal drops to the second reference signal (i.e., the pixel signal threshold), the second comparator outputs a high-level pulse. This high-level pulse can be used to trigger the pixel to reset, and after the pixel resets, exposure continues, and so on. Since the readout module can read the pixel signals of the first and second groups of pixels in parallel, the pixel signal readout efficiency can be effectively improved, thereby increasing the frame rate of the pulse sequence image sensor.

[0051] As described above, the pulse sequence image sensor provided by this invention improves the signal-to-noise ratio when operating in the first pulse sequence output mode, and increases the frame rate when operating in the second pulse sequence output mode. In this way, the operating mode of the pulse sequence image sensor can be selected according to actual needs to meet different application scenarios.

[0052] In addition, it should be noted that pulse sequence image sensors, besides pixel arrays and readout circuits, usually include conventional components such as peripheral circuits. For the sake of brevity, these conventional components will not be listed here.

[0053] The following will combine Figure 1 The pulse sequence image sensor provided by this utility model will be described using a specific embodiment. It should be noted that, for the sake of simplicity, Figure 1 Instead of showing the entire pixel array and readout circuitry of the pulse sequence image sensor, only a single pixel module (specifically, a column of pixels in the pixel array) and its corresponding readout module are schematically drawn.

[0054] Specifically, as shown in the figure, the pixel module includes pixel 1, pixel 2, pixel 3, pixel 4, ..., wherein each pixel, in addition to the photoelectric conversion unit 100, also includes a signal output unit 110 and a reset unit 120. In this embodiment, the photoelectric conversion unit 100 is used to convert optical signals into electrical signals; the signal output unit 110 is used to output the electrical signals formed by the photoelectric conversion unit 100, wherein the first end of the signal output unit 110 is connected to the photoelectric conversion unit 100, and the second end of the signal output unit 110 is connected to the readout module as the output end of the pixel; the reset unit 120 is used to reset the photoelectric conversion unit 100 according to a reset signal, wherein the first end of the reset unit 120 is connected to the photoelectric conversion unit 100, and the second end of the reset unit 120 is connected to the readout module as the input end of the pixel. Furthermore, in this embodiment, pixels located in odd-numbered rows (i.e., pixel 1, pixel 3, ...) in the pixel module are divided into a first group, and pixels located in even-numbered rows (i.e., pixel 2, pixel 4, ...) are divided into a second group.

[0055] The readout module 200 includes a first comparator 2001, a second comparator 2002, and a mode switching submodule. The positive input terminal of the first comparator 2001 is connected to the first reference signal Vref_1, and the positive input terminal of the second comparator 2002 is connected to the second reference signal Vref_2. The mode switching submodule includes a first electrical signal output line 2010, a second electrical signal output line 2011, a first reset signal input line 2012, a second reset signal input line 2013, a first switch S1, a second switch S2, and a third switch S3. The output terminal of the first group of pixels (i.e., the second terminal of the signal output section 110 in the first group of pixels) is connected to the negative input terminal of the first comparator 2001 via the first electrical signal output line 2010; the output terminal of the second group of pixels (i.e., the second terminal of the signal output section 110 in the second group of pixels) is connected to the negative input terminal of the second comparator 2002 via the second electrical signal output line 2011; the first switch S1 is connected between the first electrical signal output line 2010 and the second electrical signal output line 2011; the input terminal of the first group of pixels is connected to the output terminal of the first comparator 2001 via the first reset signal input line 2012; the input terminal of the second group of pixels is connected to the second comparator 2002 via the second reset signal line 2013; the second switch S2 is connected between the first reset signal input line 2012 and the second reset signal line 2013; and the third switch S3 is disposed on the first reset signal input line 2012, wherein one end of the third switch S3 is connected to the input terminal of the first group of pixels and the second switch S2, and the other end is connected to the output terminal of the first comparator 2001.

[0056] When both the first switch S1 and the second switch S2 are on and the third switch S3 is off, the mode switching submodule operates in the first state. Correspondingly, the first electrical signal output line 2010 and the second electrical signal output line 2011 are short-circuited, thereby connecting the output terminal of each pixel in the first and second groups simultaneously to the negative input terminal of the first comparator 2001 and the negative input terminal of the second comparator 2002; the first reset signal input line 2012 and the second reset signal line 2013 are short-circuited, and simultaneously, the first reset signal input line 2012 is disconnected from the output terminal of the first comparator 2001, thereby connecting the input terminal of each pixel in the first and second groups to the output terminal of the second comparator 2002.

[0057] When both the first switch S1 and the second switch S2 are open and the third switch S3 is open, the mode switching submodule operates in the second mode. Correspondingly, the output terminal of the first group of pixels is connected to the negative input terminal of the first comparator 2001, the input terminal of the first group of pixels is connected to the output terminal of the first comparator 2001, the output terminal of the second group of pixels is connected to the negative input terminal of the second comparator 2002, and the input terminal of the second group of pixels is connected to the output terminal of the second comparator 2002.

[0058] It should be noted that the first switch S1, the second switch S2, and the third switch S3 are preferably implemented using CMOS transistors. However, those skilled in the art will understand that other types of switches applicable to image sensors also fall within the protection scope of this utility model. For the sake of brevity, all possible switch types will not be listed here.

[0059] The photoelectric conversion unit, signal output unit, and reset unit in a pixel can be implemented in various ways. In a preferred embodiment, such as... Figure 2As shown, the photoelectric conversion unit 100 is implemented using a light-emitting diode (LED). The positive terminal of the LED is grounded, and the negative terminal is connected to the signal output unit and the reset unit, respectively. Correspondingly, the pixel signal of a pixel is the negative voltage signal of the LED. The signal output unit includes a source follower transistor 1101 and a pixel selection transistor 1102. The first terminal of the source follower transistor 1101 is connected to the power supply, the second terminal of the source follower transistor 1101 is connected to the first terminal of the pixel selection transistor 1102, and the third terminal of the source follower transistor 1101 serves as the first terminal of the signal output unit and is connected to the negative terminal of the photodiode. The second terminal of the pixel selection transistor 1102 serves as the second terminal of the signal output unit and is connected to the corresponding readout module 200. The third terminal of the pixel selection transistor 1102 is used to receive a first control signal that controls its on / off state. When the pixel selection transistor 1102 is on, the source follower transistor 1101 transmits the negative voltage signal of the photodiode it reads to the readout module 200 through the pixel selection transistor 1102. The reset unit 120 includes a reset transistor 1201 and a reset selection transistor 1202. The first terminal of the reset transistor 1201 is connected to a power supply. The second terminal of the reset transistor 1201, serving as the first terminal of the reset unit, is connected to the negative terminal of the photodiode. The third terminal of the reset transistor 1201 is connected to the second terminal of the reset selection transistor 1202. The first terminal of the reset selection transistor 1202, serving as the second terminal of the reset unit, is connected to the corresponding readout module 200. The third terminal of the reset selection transistor 1202 is used to receive a second control signal that controls its on / off state. When the first terminal of the reset selection transistor 1202 receives a reset signal and the reset transistor 1202 is turned on, the reset transistor 1201 resets the photodiode according to the reset signal. It should be noted that this invention does not limit the specific types of the source follower transistor 1101, pixel selection transistor 1102, reset transistor 1201, and reset selection transistor 1202; for example, they can be common PMOS transistors or NMOS transistors. If the source follower transistor 1101, pixel select transistor 1102, reset transistor 1201, and reset select transistor 1202 are all implemented using PMOS transistors, then the first terminal of each transistor is the drain, the second terminal is the source, and the third terminal is the gate. If the source follower transistor 1101, pixel select transistor 1102, reset transistor 1201, and reset select transistor 1202 are all implemented using NMOS transistors, then the first terminal of each transistor is the source, the second terminal is the drain, and the third terminal is the gate. Figure 3 yes Figure 2The diagram shown is the equivalent circuit diagram of the structure operating in the first pulse sequence output mode. Figure 4 yes Figure 2 The diagram shown is the equivalent circuit diagram of the structure operating in the second pulse sequence output mode.

[0060] The following will be based on Figure 2 Taking the structure shown as an example, its operating timing in the first pulse sequence output mode and the second pulse sequence output mode is described, wherein, Figure 5 yes Figure 2 The diagram shown illustrates the timing of the structure in the first pulse sequence output mode. Figure 6 yes Figure 2 The diagram shows the timing of the structure in the second pulse sequence output mode. It should be noted that (1) Figure 2 The source follower transistor 1101, pixel selection transistor 1102, reset transistor 1201 and reset selection transistor 1202 are all implemented using PMOS transistors; (2) Only four frames are drawn in the working timing diagram for illustrative purposes.

[0061] like Figure 5As shown, in each frame, the readout module sequentially reads the pixel signals of each pixel in the pixel module. Taking the first frame as an example, the first control signal Row_sel_1 applied to the gate of the pixel selection transistor 1102 in pixel 1 and the second control signal Rst_sel_1 applied to the gate of the reset selection transistor 1202 are first set to high-level pulses. When the first control signal Row_sel_1 is a high-level pulse, the pixel selection transistor 1102 in pixel 1 is turned on, and the negative voltage signal of the light-emitting diode 100 in pixel 1 is read out through the source follower transistor 1101 and the pixel selection transistor 1102 to the negative input terminals of the first comparator and the second comparator. Based on the comparison result of the negative voltage signal of the light-emitting diode 100 with the first reference signal and the second reference signal, the output terminals of the first comparator and the second comparator output corresponding level signals. When the second control signal Rst_sel_1 is a high-level pulse, the reset selection transistor 1202 in pixel 1 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output of the second comparator outputs a high-level signal, the reset transistor 1201 is triggered to reset the light-emitting diode 100. If the output of the second comparator outputs a low-level signal, the light-emitting diode 100 continues to be exposed. Then, the first control signal Row_sel_2 applied to the gate of the pixel selection transistor 1102 in pixel 2 and the second control signal Rst_sel_2 applied to the gate of the reset selection transistor 1202 are sequentially set to high-level pulses. When the first control signal Row_sel_2 is a high-level pulse, the pixel selection transistor 1102 in pixel 2 is turned on. The negative voltage signal of the light-emitting diode 100 in pixel 2 is read out through the source follower transistor 1101 and the pixel selection transistor 1102 to the negative input terminals of the first comparator and the second comparator. Based on the comparison result between the negative voltage signal of the light-emitting diode 100 and the first and second reference signals, the output terminals of the first and second comparators output corresponding level signals. When the second control signal Rst_sel_2 is a high-level pulse, the reset selection transistor 1202 in pixel 2 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output terminal of the second comparator outputs a high-level signal, the reset transistor 1201 is triggered to reset the light-emitting diode 100; if the output terminal of the second comparator outputs a low-level signal, the light-emitting diode 100 continues to be exposed. This process is repeated for pixels 3, 4, and so on, until the pixel signals of all pixels are read out, and the first frame ends. Subsequent frames are then read in the same manner. Correspondingly, the level signal output by the first comparator constitutes the first pulse sequence Output_1, and the level signal output by the second comparator constitutes the second pulse sequence Output_2. According to... Figure 5As can be seen from the first pulse sequence Output_1 and the second pulse sequence Output_2, up to the end of the fourth frame, the negative voltage signal of the LED 100 in pixels 1, 2, and 4 has not dropped to the first reference signal. Therefore, when reading the pixel signals of pixels 1, 2, and 4, both the first and second comparators output low-level signals. However, the negative voltage signal of the LED 100 in pixel 3 drops to the first reference signal in the second frame, triggering the first comparator to output a high-level signal. As the exposure time increases, the negative voltage signal of the LED 100 in pixel 3 drops to the second reference signal in the fourth frame, triggering the second comparator to output a high-level signal. This high-level signal, through the activated reset selection transistor 1202, reaches the reset transistor 1201 and triggers it to reset the LED 100 in pixel 3. In subsequent processing of the first pulse sequence Output_1 and the second pulse sequence Output_2, the time difference between the two high-level signals corresponding to pixel 3 in the first pulse sequence Output_1 and the second pulse sequence Output_2 is obtained through differential operation, and the image of pixel 3 is formed based on this time difference. Since the time for the negative electrode voltage signal of the light-emitting diode 100 in pixel 3 to drop from the first reference signal to the second reference signal (i.e., the time difference between the two high-level signals corresponding to pixel 3 in the first pulse sequence Output_1 and the second pulse sequence Output_2) is not affected by pixel reset and noise introduced in the pixel signal transmission path, the noise introduced in the pixel reset and pixel signal transmission path is suppressed, thereby effectively improving the signal-to-noise ratio performance of the image sensor and thus improving the image quality of the image sensor.

[0062] like Figure 6As shown, in each frame, the readout module reads the pixel signals of the first and second groups of pixels in the pixel module in parallel. In this embodiment, the timing of pixels 1 and 2 is the same in each frame, and the timing of pixels 3 and 4 is the same, so that the pixel signals of the first and second groups of pixels can be read out simultaneously. Taking the first frame as an example, the first control signal Row_sel_1 applied to the gate of the pixel selection transistor 1102 in pixel 1 and the second control signal Rst_sel_1 applied to the gate of the reset selection transistor 1202 are first set to high-level pulses in sequence. When the first control signal Row_sel_1 is a high-level pulse, the pixel selection transistor 1102 in pixel 1 is turned on, and the negative voltage signal of the light-emitting diode 100 in pixel 1 is read out to the negative input terminal of the first comparator through the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the negative voltage signal of the light-emitting diode 100 and the first reference signal, the output terminal of the first comparator outputs the corresponding level signal. When the second control signal Rst_sel_1 is a high-level pulse, the reset selection transistor 1202 in pixel 1 is turned on. During the period when the reset selection transistor 1202 is turned on, if the output of the first comparator outputs a high-level signal, the reset transistor 1201 is triggered to reset the light-emitting diode 100. If the output of the first comparator outputs a low-level signal, the light-emitting diode 100 continues to be exposed. Pixel 2 has the same timing as pixel 1. When the first control signal Row_sel_2 applied to the gate of the pixel selection transistor 1102 in pixel 2 is a high-level pulse, the pixel selection transistor 1102 in pixel 2 is turned on. The negative voltage signal of the light-emitting diode 100 in pixel 2 is read out to the negative input of the second comparator through the source follower transistor 1101 and the pixel selection transistor 1102. Based on the comparison result of the negative voltage signal of the light-emitting diode 100 and the second reference signal, the output of the second comparator outputs a corresponding level signal. When the second control signal Rst_sel_2 applied to the gate of the reset selection transistor 1202 in pixel 2 is a high-level pulse, the reset selection transistor 1202 in pixel 2 is turned on. During the conduction of the reset selection transistor 1202, if the output of the second comparator outputs a high-level signal, it triggers the reset transistor 1201 to reset the light-emitting diode 100; if the output of the second comparator outputs a low-level signal, the light-emitting diode 100 continues to be exposed. This process is repeated for pixels 3, 4, and so on, until the pixel signals of all pixels are read out, and the first frame ends. Subsequent frames are then read in the same manner. Correspondingly, the level signals output by the first comparator constitute the first pulse sequence Output_1, and the level signals output by the second comparator constitute the second pulse sequence Output_2. According to... Figure 6From the first pulse sequence Output_1 and the second pulse sequence Output_2, it can be seen that by the end of the fourth frame, the negative voltage signal of the LED 100 in pixels 2, 3, and 4 has not dropped to the first reference signal. Therefore, when reading the pixel signals of pixels 2, 3, and 4, both the first and second comparators output low-level signals. However, the negative voltage signal of the LED 100 in pixel 1 drops to the first reference signal in the first frame, triggering the first comparator to output a high-level signal and resetting the LED 100 in pixel 1 based on this high-level signal. After resetting, the LED 100 continues to be exposed. As the exposure time increases, the negative voltage signal of the LED 100 in pixel 1 drops to the first reference signal in the third frame, triggering the first comparator to output a high-level signal again and resetting the LED 100 in pixel 1 based on this high-level signal. In subsequent processing of the first pulse sequence Output_1, the image of pixel 1 is formed based on the time difference between the two high-level signals corresponding to pixel 1 in the first pulse sequence Output_1. Because the readout module can read the pixel signals from the first and second groups of pixels in parallel, it can effectively reduce the time required per frame, thereby increasing the frame rate of the pulse sequence image sensor. In particular, when the number of pixels in the first and second groups is the same, the time required per frame can be halved, and the frame rate can be doubled.

[0063] This utility model also provides a pulse sequence image sensor, which includes:

[0064] A pixel module and a readout module connected to the pixel module;

[0065] The pixel module includes two or more pixels, and each pixel includes a photoelectric conversion unit for converting optical signals into electrical signals;

[0066] The readout module includes a first comparator, a second comparator, and a signal line submodule. Each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line submodule. The first reference signal of the first comparator is greater than the second reference signal of the second comparator, and the second reference signal of the second comparator is equal to the threshold of the electrical signal.

[0067] The components of the aforementioned pulse sequence image sensor will be described in detail below.

[0068] Specifically, the pulse sequence image sensor provided by this invention includes a pixel module and a readout module connected to the pixel module. The structure of the pixel module can be referred to in the relevant section of the pulse sequence image sensor description above, and will not be repeated here for simplicity. The readout module includes a first comparator, a second comparator, and a signal line submodule. The structures of the first and second comparators can be referred to in the relevant section of the pulse sequence image sensor description above, and will not be repeated here for simplicity. The signal line submodule includes signal lines for connecting each pixel in the pixel module to the comparators. This invention does not limit the specific number or layout of the signal lines, as long as it enables the connection of the output terminal of each pixel in the pixel module to the negative input terminals of the first and second comparators, and the connection of the input terminal of each pixel in the pixel module to the output terminal of the second comparator. When the pulse sequence image sensor provided by this invention is working, the second reference signal of the second comparator is set to be equal to the threshold of the pixel signal, and the first reference signal is set to be greater than the second reference signal. Furthermore, the operating timing of the pulse sequence image sensor provided by this utility model can refer to the operating timing of the pulse sequence image sensor in the first pulse sequence output mode described above. For the sake of brevity, it will not be described again here.

[0069] Accordingly, this invention also provides an electronic device comprising the aforementioned pulse sequence image sensor. The electronic device provided by this invention can be a pulse camera, high-speed camera, audio / video player, navigation device, fixed-position terminal, entertainment unit, smartphone, communication device, device in a motor vehicle, camera, action or wearable camera, detection device, flight device, medical device, security device, etc. For the sake of brevity, not all possible types of the electronic device provided by this invention will be listed here. Because it employs the aforementioned pulse sequence image sensor, the electronic device provided by this invention has correspondingly superior performance.

[0070] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be encompassed within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other components, units, or steps, and the singular does not exclude the plural. Multiple components, units, or devices recited in the system claims may also be implemented by a single component, unit, or device through software or hardware.

[0071] The above-disclosed embodiments are merely some preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the claims of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A pulse sequence image sensor, comprising: a pixel module and a readout module connected to the pixel module; the pixel module comprises two or more pixels, the two or more pixels are divided into a first group and a second group, and the pixels comprise a photoelectric conversion unit for converting a light signal into an electrical signal; the readout module comprises a first comparator, a second comparator, and a mode switching submodule, wherein the first comparator, the second comparator, and the mode switching submodule are configured to: when the mode switching submodule works in a first state, each pixel in the pixel module is connected to the first comparator and the second comparator respectively, and a first reference signal of the first comparator is greater than a second reference signal of the second comparator, and the second reference signal of the second comparator is equal to a threshold value of the electrical signal; when the mode switching submodule works in a second state, each pixel in the first group is connected to the first comparator, and each pixel in the second group is connected to the second comparator, and the first reference signal of the first comparator and the second reference signal of the second comparator are both equal to the threshold value of the electrical signal.

2. The pulse sequence image sensor according to claim 1, wherein: the pulse sequence image sensor comprises a pixel array and a readout circuit; each column of pixels in the pixel array constitutes a pixel module; the readout circuit comprises the same number of readout modules as the number of pixel modules, and each readout module is connected to the pixel module corresponding thereto.

3. The pulse sequence image sensor according to claim 2, wherein: the pixels in each column of pixels located at odd-numbered row positions are divided into one of the first group and the second group, and the pixels located at even-numbered row positions are divided into the other of the first group and the second group.

4. The pulse sequence image sensor according to any one of claims 1 to 3, wherein: each pixel comprises an input end for receiving a reset signal and an output end for outputting the electrical signal; each pixel in the pixel module being connected to the first comparator and the second comparator respectively comprises: the output end of each pixel in the pixel module being connected to the negative input end of the first comparator and the negative input end of the second comparator respectively, and the input end of each pixel in the pixel module being connected to the output end of the second comparator; each pixel in the first group being connected to the first comparator and each pixel in the second group being connected to the second comparator comprises: the output end of each pixel in the first group being connected to the negative input end of the first comparator, the input end of each pixel in the first group being connected to the output end of the first comparator, the output end of each pixel in the second group being connected to the negative input end of the second comparator, and the input end of each pixel in the second group being connected to the output end of the second comparator.

5. The pulse sequence image sensor according to claim 4, wherein each of the pixels further comprises a signal output unit and a reset unit; the signal output unit is configured to output the electrical signal, wherein a first end of the signal output unit is connected to the photoelectric conversion unit, and a second end of the signal output unit serves as an output end of the pixel; the reset unit is configured to reset the photoelectric conversion unit according to the reset signal, wherein a first end of the reset unit is connected to the photoelectric conversion unit, and a second end of the reset unit serves as an input end of the pixel.

6. The pulse sequence image sensor according to claim 5, wherein the photoelectric conversion unit comprises a photodiode, wherein a positive electrode of the photodiode is grounded, and a negative electrode of the photodiode is connected to the first end of the signal output unit and the first end of the reset unit; the electrical signal is a negative electrode voltage signal of the photodiode.

7. The pulse sequence image sensor according to claim 6, wherein the signal output unit comprises a source follower transistor and a pixel selection transistor; a first end of the source follower transistor is connected to a power supply, a second end of the source follower transistor is connected to a first end of the pixel selection transistor, and a third end of the source follower transistor, which serves as the first end of the signal output unit, is connected to the negative electrode of the photodiode; a second end of the pixel selection transistor, which serves as the second end of the signal output unit, is connected to the corresponding readout module, and a third end of the pixel selection transistor is configured to receive a first control signal for controlling the conduction or non-conduction of the pixel selection transistor; when the pixel selection transistor is turned on, the source follower transistor outputs the negative electrode voltage signal of the photodiode read by the source follower transistor to the corresponding readout module through the pixel selection transistor.

8. The pulse sequence image sensor according to claim 6, wherein the reset unit comprises a reset transistor and a reset selection transistor; a first end of the reset transistor is connected to the power supply, a second end of the reset transistor, which serves as the first end of the reset unit, is connected to the negative electrode of the photodiode, and a third end of the reset transistor is connected to a second end of the reset selection transistor; a first end of the reset selection transistor, which serves as the second end of the reset unit, is connected to the corresponding readout module, and a third end of the reset selection transistor is configured to receive a second control signal for controlling the conduction or non-conduction of the reset selection transistor; when the first end of the reset selection transistor receives the reset signal and the reset transistor is turned on, the reset transistor resets the photodiode according to the reset signal.

9. The pulse sequence image sensor according to claim 4, wherein the mode switching submodule comprises a first electrical signal output line, a second electrical signal output line, a first reset signal input line, a second reset signal input line, a first switch, a second switch, and a third switch. ​ ​ ​ ​ ​ an output terminal of the pixel in the first group is connected to a negative input terminal of the first comparator through the first electrical signal output line, an output terminal of the pixel in the second group is connected to a negative input terminal of the second comparator through the second electrical signal output line, the first switch is arranged across the first electrical signal output line and the second electrical signal output line; an input terminal of the pixel in the first group is connected to an output terminal of the first comparator through the first reset signal input line, an input terminal of the pixel in the second group is connected to an output terminal of the second comparator through the second reset signal input line, the second switch is arranged across the first reset signal input line and the second reset signal input line, and the third switch is arranged on the first reset signal input line and between the second switch and the first comparator; wherein, when the first switch and the second switch are both turned on and the third switch is turned off, the mode switching sub-module works in the first state; and when the first switch and the second switch are both turned off and the third switch is turned on, the mode switching sub-module works in the second state.

10. A pulse sequence image sensor, comprising: a pixel module and a readout module connected to the pixel module; the pixel module comprises two or more pixels, and each pixel comprises a photoelectric conversion unit for converting a light signal into an electrical signal; the readout module comprises a first comparator, a second comparator and a signal line sub-module, wherein each pixel in the pixel module is connected to the first comparator and the second comparator through the signal line sub-module, and a first reference signal of the first comparator is greater than a second reference signal of the second comparator, and the second reference signal of the second comparator is equal to a threshold value of the electrical signal.

11. An electronic device comprising the pulse sequence image sensor according to any one of claims 1 to 10.

Images