Printed circuit board and controller

Abstract

The utility model discloses a printed circuit board and a controller, and the printed circuit board comprises a substrate which is provided with a first surface and a second surface which are opposite to each other, the first surface of the substrate is provided with a heat dissipation bonding pad, the second surface of the substrate is provided with a window, and the heat dissipation bonding pad is connected with the window through a heat dissipation via hole; a plurality of surface-mounted component placement areas are arranged in the window range, any surface-mounted component placement area is provided with a bonding pad, the area of the bonding pad is smaller than 0.5 time that of the surface-mounted component placement area, and the bonding pad is arranged close to the edge of the surface-mounted component placement area. The heat dissipation area of the surface of the printed circuit board can be increased, and the heat dissipation performance of the printed circuit board is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board manufacturing, and in particular to a printed circuit board and a controller. BACKGROUND

[0002] With the development of electronic manufacturing technology, the power consumption of components is also increasing, which brings the problem of component heat dissipation. Taking a chip as an example, a large number of chips use heat dissipation pads to solve the heat dissipation problem, and the heat dissipation pads are required to be punched during the packaging and manufacturing of the printed circuit board, and the heat is guided to the back window copper skin through the via hole for surface heat dissipation. With the increase of component power consumption, the above-mentioned via hole heat dissipation method cannot meet the heat dissipation requirements of the chip, and technical innovation is needed to solve the heat dissipation problem. CONTENT OF THE UTILITY MODEL

[0003] In order to solve the problems of the prior art, the present application adopts the following technical solutions:

[0004] The present application provides a printed circuit board, comprising:

[0005] The substrate has opposite first and second surfaces, the first surface of the substrate is provided with a heat dissipation pad, and the second surface of the substrate is provided with a window, and the heat dissipation pad and the window are connected through a heat dissipation via hole.

[0006] A plurality of patch element placement areas are provided within the window range, any of the patch element placement areas is provided with a solder pad, the area of the solder pad is less than 0.5 times the area of the patch element placement area, and the solder pad is arranged close to the edge of the patch element placement area.

[0007] In summary, the present application provides a printed circuit board, a plurality of patch element placement areas are arranged at the window position of the second surface of the substrate, and a solder pad is arranged close to the edge in each patch element placement area, the area of the solder pad is less than 0.5 times the area of the patch element placement area, when the patch element used for heat dissipation is arranged in the patch element placement area for reflow soldering, due to the small area of the solder pad and the close arrangement to the edge, the stress on the two ends of the patch element is inconsistent during the melting process of the solder paste, and the patch element placement area is lifted away from the solder pad, thereby effectively increasing the heat dissipation area of the surface of the printed circuit board and improving the heat dissipation performance of the printed circuit board.

[0008] Further, the patch element placement area is used to arrange the patch element, and the patch element is configured as a heat dissipation device for heat dissipation.

[0009] Further, the patch element placement area is configured as a rectangle, and the solder pad in the patch element placement area is arranged close to the short side of the patch element placement area.

[0010] Further, the size of the patch element placement area is related to the size of the windowed area,

[0011] The length of the patch element placement area is less than 0.3 times the length of the windowed area and greater than 0.25 times the length of the windowed area.

[0012] The width of the patch element placement area is less than 0.25 times the width of the windowed area and greater than 0.20 times the width of the windowed area.

[0013] Further, the ratio of the length of the patch element projected on the second surface of the substrate to the length of the patch element placement area satisfies: greater than or equal to 0.5 and less than or equal to 0.75.

[0014] The ratio of the width of the patch element projected on the second surface of the substrate to the width of the patch element placement area satisfies: greater than or equal to 0.55 and less than or equal to 0.85.

[0015] Further, the patch element and the solder pad in the patch element placement area are welded by a reflow soldering process, and after welding, the included angle between the extension direction of the patch element and the second surface of the substrate is greater than 0°.

[0016] Further, the plurality of patch element placement areas are arranged in an array within the windowed area, and for the solder pad in each patch element placement area, the solder pad is arranged close to the same short side of the patch element placement area.

[0017] Further, the second surface of the substrate is provided with a copper skin, the copper skin is connected with the heat dissipation solder pad on the first surface of the substrate through a heat dissipation via, and a windowing process is used to form a window on a selected area on the surface of the copper skin.

[0018] The solder pad in the patch element placement area is connected with the copper skin within the windowed area.

[0019] Further, a solder resist area is arranged around the solder pad in the patch element placement area.

[0020] Further, the solder resist area is a green oil layer reserved around the solder pad when the windowing is performed.

[0021] The application also provides a controller comprising a patch element, a chip and the printed circuit board according to any one of the above technical solutions, the chip is welded on the first surface of the printed circuit board and the heat dissipation fin of the chip is welded with the heat dissipation solder pad, and the patch element is welded on the solder pad of the patch element placement area to dissipate heat for the chip.

[0022] The controller according to the application comprises the printed circuit board according to any one of the above technical solutions, so it has all the beneficial effects of the printed circuit board, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A partial structure diagram of a first surface of a printed circuit board according to an embodiment of the present application is provided.

[0024] Figure 2 A partial structure diagram of a second surface of a printed circuit board according to an embodiment of the present application is provided.

[0025] Figure 3 A partial structure diagram of a second surface of a printed circuit board according to another embodiment of the present application is provided.

[0026] Figure 4 A monument device package diagram according to an embodiment of the present application is provided.

[0027] Figure 5 A monument device package diagram according to another embodiment of the present application is provided.

[0028] Figure 6 A design and packaging method flowchart of a printed circuit board according to an embodiment of the present application is provided.

[0029] Figure 7 A packaging step flowchart in a design and packaging method of a printed circuit board according to an embodiment of the present application is provided.

[0030] Figure 8 A monument effect diagram of a printed circuit board according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0031] The present application will be described in detail below with reference to the specific embodiments shown in the drawings, but these embodiments do not limit the present application, and the structural, method, or functional changes made by those of ordinary skill in the art based on these embodiments are included within the scope of protection of the present application.

[0032] In order to solve the problems of the prior art, the present application provides a printed circuit board, comprising: a substrate, the substrate having opposite first and second surfaces, the first surface of the substrate being provided with a heat dissipation pad, and the second surface of the substrate being provided with a window, the heat dissipation pad and the window being connected by a heat dissipation via.

[0033] A plurality of patch element placement areas are provided in the window range, and any patch element placement area is provided with a solder pad, the area of the solder pad being less than 0.5 times the area of the patch element placement area, and the solder pad being provided close to the edge of the patch element placement area.

[0034] Specifically, the substrate, as the basic structure of the printed circuit board, is usually made of insulating material, and the surface of the substrate is covered with a conductive layer for electrical connection and heat dissipation. In combination with Figure 1 and Figure 2 The substrate 11 has opposite first and second surfaces 101 and 102, and the first surface 101 is provided with a heat dissipation pad 111, and the second surface 102 is provided with a window 112.Figure 1 As shown, a heat dissipation pad 111 is provided on the first surface 101 of the substrate 11. The heat dissipation pad 111 is usually located below the chip or other high-power components and is used to conduct the heat generated by the components to other parts of the printed circuit board 100.

[0035] like Figure 2 The diagram shows a schematic representation of the windowed area 113 of the second surface 102 of the substrate 11. As an optional implementation, the second surface 102 of the substrate 11 is provided with copper foil, which is connected to the heat dissipation pads 111 of the first surface 101 of the substrate 11 via heat dissipation vias 112, forming a heat dissipation network for the printed circuit board. A window is formed in a selected area on the surface of the copper foil using a windowing process. The windowed area 113 is connected to the heat dissipation pads 111 of the first surface 101 via heat dissipation vias 112. The heat dissipation vias 112 are metallized holes penetrating the substrate 11, allowing heat to be conducted from the heat dissipation pads 111 of the first surface 101 of the substrate 11 to the windowed area 113 of the second surface 102 of the substrate 11, achieving efficient heat dissipation of the printed circuit board 100.

[0036] like Figure 2 As shown, a plurality of surface mount component placement areas 114 are provided within the window area. The pads 115 in the surface mount component placement areas 114 are connected to the copper foil within the window area, thereby connecting the pads on the second side of the substrate to the heat dissipation network of the printed circuit board. The surface mount component placement areas 114 are used to place surface mount components 116, which are configured as heat dissipation devices for heat dissipation.

[0037] The pad 115 is located at the edge of the surface mount component placement area 114, creating conditions for the tombstoning effect during the subsequent soldering of the surface mount component 116. Furthermore, the area of ​​the pad 115 is less than 0.5 times the area of ​​the surface mount component placement area 114. The smaller area of ​​the pad 115 reduces the contact area between the solder paste and the surface mount component 116 during soldering, which helps to form uneven stress during the soldering process and promotes the tombstoning effect of the surface mount component 116.

[0038] According to the above description, the printed circuit board provided in this application provides a plurality of surface mount component placement areas 114 at the window position on the second surface 102 of the substrate 11, and pads 115 are arranged near the edge in each surface mount component placement area 114. The area of ​​the pads 115 is less than 0.5 times the area of ​​the surface mount component placement area 114. When surface mount components 116 used for heat dissipation are placed in the surface mount component placement area 114 for reflow soldering, due to the small area of ​​the pads 115 and their proximity to the edge, the stress on both ends of the surface mount component 116 is inconsistent during the solder paste melting process, resulting in a tombstoning effect. This causes the end of the surface mount component 116 away from the pads 115 to lift up, thereby effectively increasing the heat dissipation area of ​​the printed circuit board 100 surface and improving the heat dissipation performance of the printed circuit board 100.Figure 1 As shown, taking a chip soldered on the first side 101 of the substrate 11 as an example, the heat dissipation pad 111 is usually located below the chip and is soldered to the heat sink of the chip, serving as the heat dissipation pad of the chip. The heat generated when the chip is working is conducted to the window area 113 and the surface mount element 116 through the heat dissipation pad 111, further increasing the heat dissipation area of ​​the chip and facilitating the heat dissipation of the chip.

[0039] like Figure 2 As shown, as an optional implementation, the surface mount component placement area 114 is configured as a rectangle, with the pads 115 in the surface mount component placement area 114 located close to the short side of the surface mount component placement area 114. Therefore, during reflow soldering, uneven stress is easily formed at the far ends of the surface mount component 116, thus promoting the tombstoning effect of the surface mount component 116. This ensures that the surface mount component 116 can stably form a tombstoned state during soldering, thereby increasing the heat dissipation area of ​​the printed circuit board 100 surface, improving the heat dissipation performance of the printed circuit board 100, and facilitating heat dissipation for devices located on the first surface 101.

[0040] As one implementation, a reflow soldering process is used to solder the surface mount component 116 to the pads 115 in the surface mount component placement area 114. After soldering, the angle between the extension direction of the surface mount component 116 and the second surface 102 of the substrate 11 is greater than 0°. Preferably, as shown in the example... Figure 8 As shown, the angle between the extension direction of the patch element 116 and the second surface 102 is approximately 90°.

[0041] Specifically, the surface mount component 116 is mounted on the printed circuit board 100 and soldered using a reflow soldering process to fix the surface mount component 116 to the pad 115. During the reflow soldering process, the uneven stress on both ends of the surface mount component 116 will produce a tombstoning effect, causing the end of the surface mount component 116 away from the pad 115 to lift up, forming a tombstoning state. This results in a certain angle between the extension direction of the surface mount component 116 and the second surface 102 of the substrate 11, thereby increasing the contact area between the surface mount component 116 and the air, increasing the heat dissipation area of ​​the printed circuit board 100 surface, and improving heat dissipation efficiency.

[0042] like Figure 2 As shown, as an optional implementation, a plurality of surface mount component placement areas 114 are arranged in an array within the window area. In this way, a plurality of surface mount components 116 can be evenly arranged in the heat dissipation area of ​​the printed circuit board 100, maximizing the utilization area of ​​the window area 113, thereby maximizing the heat dissipation area and achieving efficient heat dissipation of the printed circuit board 100.

[0043] As an optional implementation, for each surface mount component placement area 114, the pads 115 are set on the same short side of the surface mount component placement area 114.

[0044] Specifically, the pads 115 are located on the same short side of the surface mount component placement area 114. All surface mount components 116 will be subjected to similar stress conditions during the soldering process. When the tombstoning effect occurs, the tilting direction of all surface mount components 116 is consistent, ensuring that there is sufficient gap between each tombstoned surface mount component 116, avoiding mutual interference between the surface mount components 116, thereby further improving heat dissipation efficiency.

[0045] As an optional implementation, the size of the surface mount component placement area 114 is related to the size of the window area 113. The length of the surface mount component placement area 114 is less than 0.3 times the length of the window area 113 and greater than 0.25 times the length of the window area 113; the width of the surface mount component placement area 114 is less than 0.25 times the width of the window area 113 and greater than 0.20 times the width of the window area 113.

[0046] For example, such as Figure 2 As shown, the QFN32 packaged heat sink chip has a size of 5.80mm × 5.20mm. By controlling the length of the surface mount component placement area 114 to be between 0.25 and 0.3 times the length of the window area 113, and controlling the width of the surface mount component placement area 114 to be between 0.20 and 0.25 times the width of the window area 113, as... Figure 2 As shown, a 3×4 array of surface mount components 116 can be obtained, with multiple surface mount components 116 evenly distributed within the windowed area 113 to form a "tombstone array". This array layout significantly increases the heat dissipation surface area of ​​the printed circuit board 100 and can avoid mutual interference between the individual tombstone surface mount components 116 during heat dissipation.

[0047] As an optional implementation method, such as Figure 3 As shown, a solder mask area 117 is provided around the pad 115 in the surface mount component placement area 114. The solder mask area 117 is used to prevent molten solder paste from overflowing into the window area 113 during the soldering process, thereby ensuring soldering quality and heat dissipation.

[0048] As an alternative implementation, the solder mask area 117 is a green solder mask layer that surrounds the solder pad 115 when the window is opened, thereby simplifying the manufacturing process of the printed circuit board 100 and reducing the manufacturing cost of the printed circuit board 100.

[0049] As an optional implementation, the ratio of the length of the projection of the patch element 116 onto the second surface 102 of the substrate 11 to the length of the patch element placement area 114 satisfies the following: greater than or equal to 0.5 and less than or equal to 0.75.

[0050] The ratio of the width of the patch element 116 projected on the second surface 102 of the substrate 11 to the width of the patch element placement area 114 satisfies: greater than or equal to 0.55, and less than or equal to 0.85. Through the size design of the patch element 116, it can be avoided that the patch element 116 exceeds the patch element placement area 114, and it is ensured that any patch element 116 only contacts with the area of a single pad 115 when the patch element 116 is mounted, and the welding quality of the patch element 116 is ensured.

[0051] For example, as shown in Figure 4 below, taking the 0402 package patch capacitor and the QFN32 package chip as examples, the body size of the 0402 package patch capacitor is 1.00mmx0.50mmx0.50mm, the size of the patch element placement area 114 is not less than the body size of the 0402 package patch capacitor, Figure 4 the size of the patch element placement area 114 is 1.60mmx0.70mm. The pad 115 is located in the patch element placement area 114, the size of the pad 115 of the stand monument device package is 0.60mmx0.55mm, the patch element 116 is mounted on the printed circuit board 100 through the pad 115, and the heat on the printed circuit board 100 can be conducted to the patch element 116 through the pad 115.

[0052] As another optional implementation, the patch element 116 is substantially rectangular, and the patch element 116 has a defect near one side of the short side.

[0053] Specifically, as shown in Figure 5 due to the defect of the patch element 116 near one side of the short side, the uneven stress condition of the two ends of the patch element 116 during welding is increased, so that the patch element 116 can stably form a stand monument state during welding, thereby increasing the heat dissipation area of the surface of the printed circuit board 100 and improving the heat dissipation performance of the printed circuit board 100.

[0054] Further, the material of the patch element 116 can be selected as a metal material with good heat conduction performance, such as copper or aluminum, to further enhance the heat dissipation effect. By uniformly distributing a plurality of stand monument devices in the windowed area 113 of the printed circuit board 100, the stand monument effect of the patch element 116 increases the heat dissipation area of the surface of the printed circuit board 100, thereby improving the heat dissipation performance of the printed circuit board 100 without increasing the production cost.

[0055] The application also provides a design and packaging method of a printed circuit board 100, as shown in Figure 6 the method comprises the following steps:

[0056] Step S11, designing a monument device package, including a design of a patch element placement area 114 and a design of a pad 115, the pad 115 is located in the patch element placement area 114, is arranged close to the edge of the patch element placement area 114, and the area of the pad 115 is less than 0.5 times the area of the patch element placement area 114;

[0057] Step S12, providing a substrate 11, the substrate 11 has opposite first and second surfaces 101 and 102, a heat dissipation pad 111 is arranged on the first surface 101 of the substrate 11, and a windowed area 113 is arranged on the second surface 102 of the substrate 11, the heat dissipation pad 111 and the windowed area 113 are connected through a heat dissipation via 112;

[0058] Step S13, distributing the monument device package in the windowed area 113 away from the heat dissipation via 112;

[0059] Step S14, windowing according to the layout of the windowed area 113 and the monument device package, and retaining a green oil layer around the pad 115 of the monument device package to form a solder resist area 117 around the pad 115.

[0060] According to the design and packaging method of the printed circuit board 100 provided in the embodiments of the present application, the monument device package is designed, and the monument device package is distributed in the windowed area 113 away from the heat dissipation via 112. In the monument device package, the pad 115 is arranged close to the edge in the patch element placement area 114, and the area of the pad 115 is less than 0.5 times the area of the patch element placement area 114. When the patch element 116 for heat dissipation is arranged in the patch element placement area 114 for reflow soldering, due to the small area and the edge arrangement of the pad 115, the stress on the two ends of the patch element 116 is inconsistent in the tin paste melting process, and the monument effect occurs, so that the end of the patch element 116 far from the pad 115 is lifted, thereby effectively increasing the heat dissipation area of the surface of the printed circuit board 100 and improving the heat dissipation performance of the printed circuit board 100.

[0061] As an optional implementation manner, the design of the monument device package in step S11 can be obtained based on the modification of an existing basic patch element package.

[0062] Specifically, the basic patch element package can be obtained from the package element library, and the basic patch element package includes pads arranged in mirror image. The size parameters of the basic patch element package can be set according to actual needs, and the single-side pad of the basic patch element package is deleted, so as to obtain the monument device package provided in the embodiments of the present application. The design method of the monument device package is obtained by modifying the existing basic patch element package, and the implementation method is simple.

[0063] As an optional implementation manner, as shown in FIG. 2,Figure 7 As shown in the figure, the method further comprises:

[0064] In step S21, a tin paste printing screen plate is made, and the window size of the tin paste printing screen plate is consistent with the size of the pad 115 in the monument device package;

[0065] In step S21, the tin paste printing screen plate is aligned with the windowed area 113 of the substrate 11, and the tin paste is printed.

[0066] In step S21, the patch element 116 is attached, and reflow soldering is used for reflow curing to fix the patch element 116 to the pad 115. The patch element 116 is configured as a heat dissipation device for heat dissipation.

[0067] Specifically, assuming that the second surface 102 of the substrate 11 is placed parallel to the horizontal plane, when the patch element 116 is packaged, the patch element 116 only needs to be placed horizontally at the corresponding position of the pad 115 on the second surface 102 of the substrate 11. Due to the special design of the position of the pad 115 on the printed circuit board 100 in the embodiment of the present application, the monument phenomenon of the patch element 116 during reflow soldering can be promoted, so as to achieve the purpose of increasing the heat dissipation area of the printed circuit board 100. In this process, the patch element 116 is placed simply before reflow soldering, and the existing production line equipment can be used, without the need for special design of the patch element 116 grabbing equipment, so that the production cost can be reduced.

[0068] For example, the effect of the patch element 116 after being placed in the furnace and monumented is as shown in the figure. Figure 8 As shown in the figure, the original back heat dissipation area is 5.80mm*5.20mm=29.12mm, and the increased area is the area of 4 long sides of 12 0402 monument packages, i.e. 1.00mm*0.50mm*4*12=24mm. In this way, the back heat dissipation area is increased to nearly 2 times (182%) of the original area without increasing the cost.

[0069] According to the above description, the printed circuit board 100 provided by the present application is designed to package a monument device, and the monument device is distributed in the windowed area 113 away from the heat dissipation via hole 112, so that the patch element 116 is lifted away from one end of the pad 115 by using the monument effect, thereby effectively increasing the heat dissipation area of the surface of the printed circuit board 100 and improving the heat dissipation performance of the printed circuit board 100.

[0070] As an optional implementation manner, the present application further provides a controller, which comprises a chip, a printed circuit board, and a patch element. The printed circuit board is obtained by at least the method provided by the embodiment of the present application. The chip is located on the first surface of the printed circuit board, and the heat dissipation fin of the chip is welded to the heat dissipation pad of the printed circuit board. The patch element is located in the windowed area of the printed circuit board to form a monument, and is used for heat dissipation of the chip.

[0071] According to the above description, in the controller provided by the embodiment of the application, the second surface of the printed circuit board is provided with the patch element in the form of a monument, so that the heat dissipation performance of the controller can be improved.

[0072] It can be understood that the word "exemplary" used herein means "serving as an example, an illustration, or a description." Any embodiment described as "exemplary" is not necessarily preferred or superior over other embodiments and / or does not exclude other features from the application. It is to be understood that certain features that are, for clarity, described in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment can also be provided separately or in any appropriate combination. The above disclosure is merely preferred embodiments of the present application and is not intended to limit the scope of the application. Those skilled in the art can understand that changes, modifications, substitutions, combinations, simplifications, and the like, without departing from the spirit and scope of the application and the appended claims, are equivalent replacements and still fall within the scope of the application.

Claims

1. A printed wiring board, characterized by, The printed circuit board comprises: a substrate having opposite first and second surfaces, the first surface of the substrate being provided with a heat dissipation pad, and the second surface of the substrate being provided with a window, the heat dissipation pad and the window being connected by a heat dissipation via; a plurality of patch element placement areas are arranged in the range of the window, and each patch element placement area is provided with a pad, the area of the pad being less than 0.5 times the area of the patch element placement area, and the pad being arranged close to the edge of the patch element placement area.

2. The printed circuit board according to claim 1, wherein the patch element placement area is used to arrange a patch element, and the patch element is configured as a heat dissipation device for heat dissipation.

3. The printed circuit board according to claim 2, wherein the patch element placement area is configured as a rectangle, and the pad in the patch element placement area is arranged close to the short side of the patch element placement area.

4. The printed circuit board according to claim 3, wherein the size of the patch element placement area is related to the size of the window area, the length of the patch element placement area is less than 0.3 times the length of the window area and greater than 0.25 times the length of the window area; the width of the patch element placement area is less than 0.25 times the width of the window area and greater than 0.20 times the width of the window area.

5. The printed circuit board according to claim 3, wherein the ratio of the length of the patch element projected on the second surface of the substrate to the length of the patch element placement area satisfies: greater than or equal to 0.5 and less than or equal to 0.75; the ratio of the width of the patch element projected on the second surface of the substrate to the width of the patch element placement area satisfies: greater than or equal to 0.55 and less than or equal to 0.

85.

6. The printed circuit board according to any one of claims 3 to 5, wherein the patch element and the pad in the patch element placement area are welded by a reflow soldering process, and after welding, the included angle between the extension direction of the patch element and the second surface of the substrate is greater than 0°.

7. The printed circuit board according to claim 3, wherein a plurality of patch element placement areas are arranged in an array in the range of the window, and for the pad in each patch element placement area, the pad is arranged close to the same side short side of the patch element placement area.

8. The printed circuit board according to claim 1, wherein the second surface of the substrate is provided with a copper skin, the copper skin is connected with the heat dissipation pad on the first surface of the substrate through the heat dissipation via, and the window is formed on the selected area of the surface of the copper skin by a windowing process; the pad in the patch element placement area is connected with the copper skin in the range of the window.

9. The printed circuit board according to claim 1, wherein a solder resist area is arranged around the pad in the patch element placement area; and the solder resist area is a green oil layer reserved around the pad when the window is formed.

10. A controller characterized by comprising: A chip is soldered to a first surface of the printed wiring board and a heat sink of the chip is soldered to the heat sink land. A patch element is soldered to a land of the patch element placement area to radiate heat of the chip.

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