Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device includes a first memory array having a first side; a second memory array having a second side facing the first side; and a well pin region between the first memory array along the first side and the second memory array along the second side, the well pin region having a first region and a second region each including n well tap cells and an intermediate region between the first and second regions and including p well tap cells, wherein a first edge region of the first region is arranged along a first side of the first memory array and a second edge region of the second region is arranged along a second side of the second memory array; wherein the p-well tapping unit includes a continuous oxidation definition (OD) region for providing reverse bias for P-N junctions in the first and second memory arrays.

Description

Technical Field

[0001] This utility model relates to a semiconductor device, and more particularly to a semiconductor device in which a central strip region replaces the double edge regions. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, with the reduction of the minimum feature size, other problems need to be solved. Utility Model Content

[0004] The purpose of this disclosure is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0005] This disclosure provides a semiconductor device. The semiconductor device includes: a first memory array region having a first side; a second memory array region having a second side facing the first side, wherein the first memory array region and the second memory array region include a plurality of static random access memory (SRAM) cells; and a well-pin region disposed between the first memory array region along the first side and the second memory array region along the second side, the well-pin region having a first region including a first n-well tap unit, a second region including a second n-well tap unit, and an intermediate region disposed between the first region and the second region and including a p-well tap unit, wherein a first edge region of the first region is arranged along the first side of the first memory array region, and a second edge region of the second region is arranged along the second side of the second memory array region; wherein the p-well tap unit includes a continuous oxide definition (OD) region configured to provide reverse bias to PN junctions in the first memory array region and different PN junctions in the second memory array region.

[0006] According to one embodiment of the present invention, a distance is provided between an n-well in the first region and a different n-well in the second region, the distance having a polysilicon spacing of 3 times.

[0007] According to one embodiment of the present invention, the aforementioned intermediate region has a width that is 5 times the width of the polysilicon pitch.

[0008] According to one embodiment of the present invention, a first unconnected edge region is provided along a first opposite edge of the first memory array region, wherein the first opposite edge is located on the side opposite to the first side of the first memory array region.

[0009] According to one embodiment of the present invention, a first input / output region is disposed at the first opposite edge of the first memory array region, wherein the first unconnected edge region is located between the first memory array region and the first input / output region.

[0010] According to one embodiment of the present invention, a second unconnected edge region is provided along a second opposite edge of the second memory array region, wherein the second opposite edge is located on the side opposite to the second side of the second memory array region.

[0011] According to one embodiment of the present invention, the aforementioned second unconnected edge region does not include an n-well tap unit or a p-well tap unit.

[0012] According to one embodiment of the present invention, the well-connected area has a width of M*2-3 polysilicon pitch, where M is the polysilicon pitch width of an edge region of a memory array that is not adjacent to another memory array region and has an n-well tap unit and a p-well tap unit.

[0013] According to one embodiment of the present invention, a well n in the first region extends into the intermediate region; and a different well n in the second region extends into the intermediate region.

[0014] According to one embodiment of the present invention, the above-mentioned static random access memory cell includes a plurality of gate full-ring field-effect transistors disposed in a six-transistor static random access memory circuit topology. Attached Figure Description

[0015] The present disclosure will be better understood from the following embodiments and the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to make the explanation clear and understandable.

[0016] Figure 1 The present disclosure provides a circuit diagram of an exemplary static random access memory (SRAM) device according to some embodiments thereof.

[0017] Figure 2This is a schematic diagram of an exemplary 6T SRAM circuit topology for a memory cell, as shown in some embodiments of this disclosure.

[0018] Figure 3A This is a block diagram of an exemplary SRAM structure having a single SRAM array, as shown in some embodiments of the present disclosure.

[0019] Figure 3B A block diagram of an exemplary SRAM structure with dual SRAM arrays has been drawn to illustrate some embodiments of this disclosure.

[0020] Figure 4 A block diagram of an exemplary SRAM structure having four SRAM arrays has been drawn to illustrate some embodiments of this disclosure.

[0021] Figure 5 A layout diagram illustrating an exemplary layout of an SRAM edge region used with a single SRAM array is provided, according to some embodiments of the present disclosure.

[0022] Figure 6 A layout diagram illustrating an exemplary layout of the SRAM edge region for an SRAM structure having a dual SRAM array, as shown in some embodiments of this disclosure, is provided.

[0023] Figure 7 To illustrate some embodiments of this disclosure, a layout diagram of an exemplary middle strap region used in conjunction with an SRAM structure having dual SRAM arrays is provided.

[0024] Figure 8 This is a flowchart illustrating an exemplary method for memory cell placement according to some embodiments of this disclosure.

[0025] Figure 9 The following is a block diagram illustrating exemplary computer systems in which various embodiments of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0026] Figure 10 The following is a block diagram of an IC manufacturing system and related IC manufacturing processes according to some embodiments of this disclosure.

[0027] The attached figures are labeled as follows:

[0028] 100: SRAM device

[0029] 120: Column Decoder

[0030] 130: Character line driver

[0031] 140: Line Decoder

[0032] 150: Line Multiplexer

[0033] 160: Read / Write Circuit

[0034] 1700-170 N :OK

[0035] 180: SRAM array

[0036] 190: Memory Unit

[0037] 190 00 -190 MN : Memory unit

[0038] 220: NFET transmission device

[0039] 230: NFET transmission device

[0040] 240: NFET pull-down device

[0041] 250: NFET pull-down device

[0042] 260: PFET pull-up device

[0043] 270: PFET pull-up device

[0044] 300: Exemplary SRAM Structure

[0045] 302: SRAM array

[0046] 304: First Edge Region

[0047] 306: Second Edge Region

[0048] 308-310: Width

[0049] 320: Exemplary SRAM Structure

[0050] 322: First SRAM array

[0051] 324: Second SRAM array

[0052] 326: First Edge Region

[0053] 328: Middle strip area

[0054] 330: Width

[0055] 400: Exemplary SRAM Structure

[0056] 402: First SRAM Array

[0057] 403: First side

[0058] 404: Second SRAM array

[0059] 405: Second side

[0060] 406: Third SRAM array

[0061] 407: Side View

[0062] 408: Fourth SRAM Array

[0063] 409: Side View

[0064] 412: First I / O area

[0065] 414: Second I / O area

[0066] 416: Third I / O area

[0067] 418: Fourth I / O area

[0068] 420: First Control Area

[0069] 422: Second Control Area

[0070] 424: First WL drive area

[0071] 426: Second WL driver area

[0072] 428-434: No-bump edge region

[0073] 436: Edge area of ​​the middle strip

[0074] 438: Edge area of ​​the middle strip

[0075] 439: Width

[0076] 502: Edge area

[0077] 504: Zone 1

[0078] 506: Second Zone

[0079] 508: PO area

[0080] 510: OD region

[0081] 512:n well

[0082] 514:n well tapping unit

[0083] 516:p well tapping unit

[0084] 518: Width

[0085] 520: Width

[0086] 602: Edge region

[0087] 604: Zone 1

[0088] 605: Second Zone

[0089] 606: Middle Area

[0090] 608: PO area

[0091] 610: OD region

[0092] 612:n well

[0093] 614:n well tap unit

[0094] 616:p well tapping unit

[0095] 621: Width

[0096] 623: Width

[0097] 625: Interval

[0098] 627: Length

[0099] 702: Edge Area

[0100] 704: Zone 1

[0101] 705: Second Zone

[0102] 706: Middle strip area

[0103] 708: PO area

[0104] 710: OD region

[0105] 712:n well

[0106] 714:n well tapping unit

[0107] 716:p well tapping unit

[0108] 721: Width

[0109] 723: Width

[0110] 725: Interval

[0111] 727: Length

[0112] 728: First Edge

[0113] 730: Second Edge

[0114] 800: Exemplary Methods

[0115] 810-840: Square

[0116] 900: Exemplary Computer System

[0117] 902: Input / Output Interface

[0118] 903: Input / Output Device

[0119] 904: Processor

[0120] 906: Communication Infrastructure

[0121] 908: Main Memory

[0122] 910: Auxiliary storage

[0123] 912: Hard Drive

[0124] 914: Portable Disk Drive

[0125] 918: Removable Storage Unit

[0126] 920: Interface

[0127] 922: Removable Storage Unit

[0128] 924: Communication interface

[0129] 926: Communication Path

[0130] 928: Remote device

[0131] 1000: IC Manufacturing System

[0132] 1020: Design Studio

[0133] 1022: IC Design Layout Diagram

[0134] 1030: Photomask Studio

[0135] 1032: Data Preparation

[0136] 1044: Photomask Manufacturing

[0137] 1045: Photomask

[0138] 1050: Manufacturing Plant

[0139] 1052: Chip Manufacturing

[0140] 1053: Semiconductor wafer

[0141] 1060: IC device

[0142] BL: Bitline

[0143] BLB: Complementary Bit Line Detailed Implementation

[0144] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these examples are not intended to limit this disclosure.

[0145] For the sake of brevity, this document may not describe in detail conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various operations and processes described herein may be incorporated into more comprehensive processes or techniques with additional functionality not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known, and therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include a variable number of components, and a single component shown in the figures may represent multiple components.

[0146] Furthermore, for ease of description, this document may use spatial relative terms such as “above,” “overlapping,” “on top,” “top,” “below,” “under,” “below,” “lower than,” “bottom,” etc., to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover the different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly. When spatial relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on the other element, or there may be an intermediate element or layer. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer.

[0147] Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is intended for simplicity and clarity, and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0148] The features of this disclosure can be applied to SRAM designs with complementary metal-oxide-semiconductor (CMOS) planar field-effect transistors (FETs) or multi-gate FET devices, including dual-gate FETs, triple-gate FETs, omega (Ω) gate FETs, and gate-all-around (GAA) (or surround-gate) devices, and / or fin field-effect transistors (FinFETs) (field-effect transistors with fin-shaped channels). The features of this disclosure can also be applied to other circuit designs, such as other types of memory designs, or other designs in which circuit elements are repeated multiple times in the device.

[0149] The following disclosure describes various configurations of static random access memory (SRAM). Specifically, this disclosure describes different embodiments related to the layout of an SRAM device having multiple memory arrays. For ease of explanation, certain SRAM circuit elements and control circuitry are disclosed to facilitate the description of different embodiments. SRAM may also include other circuit elements and control circuitry. These other circuit elements and control circuitry are also included within the spirit and scope of this disclosure.

[0150] Figure 1 The accompanying drawings illustrate an exemplary static random access memory (SRAM) device 100 according to some embodiments of the present disclosure. The exemplary SRAM device 100 includes a row decoder 120, a word line driver 130, a column decoder 140, a row multiplexer (MUX) 150, read / write circuitry 160, and an SRAM array 180. The SRAM array 180 includes rows 1700-170 of SRAM cells. N .

[0151] Each SRAM cell in the SRAM array 180 is accessed using a memory address, for example, for memory read and write operations. Based on the memory address, column decoder 120 selects a column of memory cells for access via word line driver 130. Furthermore, based on the memory address, row decoder 140 selects rows 1700-170 of the memory cells. N A row is accessed via row multiplexer 150. For memory read operations, read / write circuitry 160 senses the voltage level on the bit line pair BL / BLB. For memory write operations, read / write circuitry 160 generates rows 1700-170 for the memory cell.N The voltage of the bit line to BL / BLB. The symbol "BL" refers to the bit line, while the symbol "BLB" refers to the complementary bit line. The intersection of the column and row of a memory cell being accessed results in access to a single memory cell.

[0152] Memory cell line 1700-170 N Each of these includes a plurality of memory cells 190. The memory cells 190 may be disposed in one or more arrays in the SRAM device 100. In this example, a single SRAM array 180 is shown to simplify the description of the disclosed embodiments. The SRAM array 180 has a number of columns of “M” and a number of rows of “N”. The symbol “190” 00 The symbol “190” refers to memory cell 190 located at column “0” and row “0”. Similarly, the symbol “190”... MN "" refers to memory cell 190 located in column "M" and row "N".

[0153] According to some embodiments of this disclosure, the number of memory cells in the SRAM array 180 may depend on one or more design parameters of the SRAM device 100. In some embodiments, the number of memory cells in the SRAM array 180 may depend on the desired bit line loading (e.g., the number of memory cells 190 electrically coupled to bit line BL and complementary bit line BLB).

[0154] In some embodiments, memory cell 190 may have a six-transistor (“6T”) SRAM circuit topology. Figure 2 The accompanying drawing illustrates an exemplary 6T SRAM circuit topology for memory cell 190. The 6T SRAM circuit topology includes n-type field-effect transistor (NFET) pull-down devices 220 and 230, NFET pull-down devices 240 and 250, and p-type FET (PFET) pull-up devices 260 and 270. The FET devices (e.g., NFET and PFET devices) may be planar metal-oxide-semiconductor FETs, FinFETs, gate-all-loop FETs, any suitable FET, or combinations thereof. Other SRAM circuit topologies, such as four-transistor (“4T”), eight-transistor (“8T”), and ten-transistor (“10T”) SRAM circuit topologies, are also included within the spirit and scope of this disclosure.

[0155] Voltage-controlled NFET transfer devices 220 and 230 from word line driver 130 transfer voltage from bit line pair BL / BLB to a bistable flip-flop structure formed by NFET pull-down devices 240 and 250 and PFET pull-up devices 260 and 270. The bit line pair BL / BLB voltage can be used during memory read and write operations. During a memory read operation, the voltage applied by word line driver 130 to the gate terminals of NFET transfer devices 220 and 230 can be at a sufficient voltage level to transfer the voltage stored in the bistable flip-flop structure to bit line BL and complementary bit line BLB, which can be sensed by read / write circuitry 160. For example, if a "1" or a logic high value (e.g., a power supply voltage, such as 0.4 volts (V), 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, and any other suitable voltage) is transmitted to bit line BL, and a "0" or a logic low value (e.g., ground or 0V) is transmitted to the complementary bit line BLB, then the read / write circuit 160 can sense (or read) these values. During a memory write operation, if bit line BL is at a "1" or logic high value and the complementary bit line BLB is at a "0" or logic low value, the voltage applied by word line driver 130 to the gate terminals of NFET transfer devices 220 and 230 can be at a sufficient voltage level to transmit the logic high value of bit line BL and the logic low value of complementary bit line BLB to the bistable flip-flop structure. In this way, these logic values ​​are written (or programmed) into the bistable flip-flop structure.

[0156] In some technologies, the active regions of a semiconductor device are positioned above n-type and p-type well regions in the substrate. The p-type well region adjacent to the n-type well region can form a PN junction. Forward bias at the PN junction can cause latch-up problems, potentially damaging the entire chip. To avoid this problem, tap cells are used in SRAM structures to provide reverse bias to the PN junction. In some SRAM structures, tap cells are formed in the edge regions of the SRAM structure.

[0157] Each SRAM array may include edge regions located on different sides of the array. The edge regions may include one or more dummy SRAM cells. The configuration of the dummy SRAM cells may be the same as or similar to that of SRAM cell 190. Furthermore, the dummy SRAM cells may not perform any circuitry function. The dummy SRAM cells may have any suitable configuration and may be included to improve the uniformity of fins and / or metal features. For example, each row of SRAM array 180 may begin and end at a dummy SRAM cell. For example, each column of SRAM array 180 may begin and end at a dummy SRAM cell. The edge regions may also include n-well tap cells and p-well tap cells.

[0158] Figure 3A This is a block diagram of an exemplary SRAM structure 300. The exemplary SRAM structure 300 includes an SRAM array 302, a first edge region 304, and a second edge region 306. The first edge region 304 may include dummy SRAM cells but not tap cells. In addition to dummy SRAM cells, the second edge region 306 may also include n-well tap cells and p-well tap cells to provide reverse bias to the PN junction. In this example, the width 308 of the second edge region has a contact polypitch (CPP) greater than the width 309 of the first edge region. In some embodiments, the exemplary SRAM array 302 may have a width 310 (e.g., in the x-direction), ranging from about 32 CPP to about 64 CPP. The term "contact polypitch (CPP)" may refer to the gate pitch of transistors in a layout, where the gate pitch may depend on the semiconductor process technology node implemented to manufacture the transistors. Semiconductor process technology nodes can include 16 nanometer (nm) technology nodes, 14nm technology nodes, 10nm technology nodes, 7nm technology nodes, 5nm technology nodes, 3nm technology nodes, 2nm technology nodes, 1nm technology nodes, and smaller technology nodes.

[0159] To increase the number of memory cells in an SRAM device, the SRAM array can be mirrored. This can result in duplication of edge cells and increase the IC footprint dedicated to the edge regions. According to embodiments of this disclosure, an intermediate stripe design is utilized to provide an edge region between two mirrored SRAM arrays, which is smaller than the two edge regions with multi-striped cells used for two SRAM arrays.

[0160] Figure 3BA block diagram of an exemplary SRAM structure 320 is provided. The exemplary SRAM structure 320 includes a first SRAM array 322, a second SRAM array 324, two first edge regions 326, and a middle stripe region 328. The first edge regions 326 may include dummy SRAM cells but not tap cells. The middle stripe region 328 may include n-well tap cells and p-well tap cells to provide reverse bias to the PN junction. In this example, the middle stripe region 328 has a width 330, which is not as wide as the two second edge regions 306 (e.g., twice the width 308). In some embodiments, the width 330 may be 15% smaller than the width of the two second edge regions 306 (e.g., twice the width 308). In some embodiments, the use of the middle stripe region 328 can result in approximately 1% area savings in the SRAM design.

[0161] Figure 4 This is a floor plan of an exemplary SRAM structure 400 according to various embodiments. The exemplary SRAM structure 400 includes a first SRAM array 402, a second SRAM array 404, a third SRAM array 406, and a fourth SRAM array 408. The exemplary SRAM structure 400 further includes a first input / output (I / O) region 412 for providing I / O to the first SRAM array 402, a second I / O region 414 for providing I / O to the second SRAM array 404, a third I / O region 416 for providing I / O to the third SRAM array 406, and a fourth I / O region 418 for providing I / O to the fourth SRAM array 408. The exemplary SRAM structure 400 also includes a first control region 420 for providing control functions (e.g., row decoding and column decoding) for the first SRAM array 402 and the third SRAM array 406, and a second control region 422 for providing control functions for the second SRAM array 404 and the fourth SRAM array 408. The exemplary SRAM structure 400 includes a first word line (WL) driver region 424 for driving the word lines in the first SRAM array 402 and the third SRAM array 406. The exemplary SRAM structure 400 includes a second WL driver region 426 for driving the word lines in the second SRAM array 404 and the fourth SRAM array 408.

[0162] The first SRAM array 402 includes a tapless edge region 428 on one side, which may include virtual SRAM cells but not taps. The second SRAM array 404 includes a tapless edge region 430 on one side, which may include virtual SRAM cells but not taps. The third SRAM array 406 includes a tapless edge region 432 on one side, which may include virtual SRAM cells but not taps. The fourth SRAM array 408 includes a tapless edge region 434 on one side, which may include virtual SRAM cells but not taps. In some embodiments, the tapless edge regions (tapless edge regions 428, 430, 432, 434) may have a width of 4 CPP (in the X direction).

[0163] Unlike each SRAM array which includes a separate edge region on the other side, the first SRAM array 402 and the second SRAM array 404 share a middle stripe edge region 436, wherein the middle stripe edge region 436 is located between the first side 403 of the first SRAM array 402 and the second side 405 of the second SRAM array 404, and the third SRAM array 406 and the fourth SRAM array 408 share a middle stripe edge region 438, wherein the middle stripe edge region 438 is located between the side 407 of the third SRAM array 406 and the side 409 of the fourth SRAM array 408.

[0164] Each of the intermediate stripe edge regions 436 and 438 may include an n-well tap unit and a p-well tap unit. In this example, each of the intermediate stripe edge regions 436 and 438 has a width 439, which is not as wide as the width 308 of the two second edge regions 306. Using the intermediate stripe edge region 436 can save integrated circuit area compared to using individual edge regions with tap units in each of the first SRAM array 402 and the second SRAM array 404. Similarly, using the intermediate stripe edge region 438 can save integrated circuit area compared to using individual edge regions with tap units in each of the third SRAM array 406 and the fourth SRAM array 408. In some embodiments, the width 439 may be 15% smaller than the width of the two second edge regions 306 (e.g., twice the width 308). In some embodiments, the use of intermediate strip edge regions 436 and / or intermediate strip edge regions 438 can result in approximately 1% area savings in SRAM designs.

[0165] In some embodiments, the above layout plan may represent a portion of a larger layout plan, such as a plan view of an entire chip or system design. The exemplary SRAM structure 400 may be an intermediate element manufactured during the process of an integrated circuit (IC) or a portion thereof. The IC or a portion thereof may include passive and active elements. Passive elements include resistors, capacitors, and inductors, while active elements include p-type FETs (PFETs), n-type FETs (NFETs), MOSFETs, CMOS transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. It should be understood that this disclosure is applicable to SRAM structures including FinFET transistors, nanostructure transistors (also known as nanosheet devices, nanowire devices, nanoring devices, gate-all-around devices, gate-all-around (GAA) devices, or multi-bridge-channel (MBC) devices). This disclosure is not limited to any particular number of devices or device regions, or to any particular device configuration.

[0166] Figure 5 A layout diagram is provided for an exemplary layout of an edge region 502 with tap cells that can be used with an SRAM array. The exemplary edge region 502 includes a first region 504 and a second region 506, both having a polysilicon (PO) region 508 and an OD region 510. FinFET NMOS and PMOS transistors are formed in the oxide-defined (OD) region. The OD region is sometimes referred to as an "oxide diffusion" region and typically defines the active region of the transistor, i.e., the region forming the channel beneath the source, drain, and gate of the transistor. Although the OD region 510 is not used for the transistors in the edge region 502, the OD region 510 is formed of the same material as the OD region used for the transistors in the SRAM array. The first region 504 also includes a plurality of n-wells 512 and n-well tap cells 514. The second region 506 includes a p+ injection region and a plurality of p-well tap cells 516. The exemplary edge region 502 has a width of approximately 10 CPP 518, which increases the geometry of the SRAM structure, where CPP is the contact polysilicon pitch defined as the spacing distance between adjacent gate structures, and the exemplary second region 506 has a width of approximately 4 CPP 520.

[0167] Figure 6A layout diagram is provided for an exemplary layout of an edge region 602 used in a dual SRAM array, where the dual SRAM arrays are adjacent to each other in the layout. The exemplary edge region 602 includes a first region 604, a second region 605, and an intermediate region 606, all having a polysilicon (PO) region 608 and an OD region 610. The first region 604 and the second region 605 also include multiple n-wells 612 and n-well tap units 614. The intermediate region 606 includes a p+ implantation region and multiple p-well tap units 616. The exemplary edge region 602 has a width 621 of approximately 20 CPP, while the exemplary intermediate region 606 has a width 623 of approximately 8 CPP. The spacing 625 between the n-wells 612 is approximately 6 CPP, and the length 627 of the OD region of the multiple p-well tap units 616 in the intermediate region 606 is approximately 2 CPP.

[0168] Figure 7 An exemplary layout for an edge region 702 of a dual SRAM array is provided based on layout diagrams shown in various embodiments, wherein the dual SRAM arrays are adjacent to each other in the layout. The exemplary edge region 702 includes a first region 704, a second region 705, and a middle stripe region 706, all having a polysilicon (PO) region 708 and an OD region 710. The first region 704 and the second region 705 also include multiple n-wells 712 and n-well tap units 714. The first region 704 includes a first edge 728, and the second region 705 includes a second edge 730. The middle stripe region 706 includes a p+ implantation region and multiple p-well tap units 716. The exemplary edge region 702 has a width 721 of approximately 17 CPP, wherein the width 721 is narrower than the width 621, and the exemplary middle stripe region 706 has a width 723 of approximately 5 CPP, wherein the width 723 is narrower than the width 623. The result of this in edge region 702 is that edge region 702 occupies less area in the integrated circuit than edge region 602. The spacing 725 between n-wells 712 is approximately 3 CPP, and the length 727 of the continuous OD region 710 of the plurality of p-well tap units 716 in the intermediate strip region 706 is approximately 4 CPP. The plurality of p-well tap units 716 can be used for SRAM arrays on both sides of edge region 702.

[0169] Figure 8 This is a flowchart of an exemplary method 800 for arranging memory cells. Figure 4 and Figure 7 It is cross-referenced to provide an exemplary embodiment following the completion of the various blocks of exemplary method 800.

[0170] In block 810, exemplary method 800 includes arranging a first memory array region having a first side in the layout region. (Refer to...) Figure 4 In an exemplary implementation, the first SRAM array 402 may be arranged to have a first side 403.

[0171] In block 820, exemplary method 800 includes arranging a second memory array region having a second side facing the first side in the layout region. (See reference...) Figure 4 In an exemplary embodiment, the second SRAM array 404 may be arranged to have a second side 405 facing the first side 403.

[0172] In block 830, exemplary method 800 includes arranging a pickup region between a first memory array region along a first side and a second memory array region along a second side. The pickup region may include a first region having n pickup units, a second region having n pickup units, and an intermediate region disposed between the first and second regions and having p pickup units, wherein a first edge region of the first region is arranged along a first side of the first memory array region, and a second edge region of the second region is arranged along a second side of the second memory array.

[0173] Reference Figure 4 and Figure 7 In an exemplary embodiment, the wellhead region (e.g., the middle strip edge region 436, edge region 702) is arranged between the first memory array region (first SRAM array 402) along the first side (first side 403) and the second memory array region (second SRAM array 404) along the second side (second side 405). The well tapping area (intermediate strip edge area 436, edge area 702) may include a first area (first area 704) having n well tapping units (n well tapping units 714), a second area (second area 705) having n well tapping units (n well tapping units 714), and an intermediate area (intermediate strip area 706) disposed between the first area (first area 704) and the second area (second area 705) and having p well tapping units (a plurality of p well tapping units 716), wherein the first edge (first edge 728) of the first area (first area 704) is arranged along the first side (first side 403) of the first memory array area (first SRAM array 402), and the second edge (second edge 730) of the second area (second area 705) is arranged along the second side (second side 405) of the second memory array area (second SRAM array 404).

[0174] In various embodiments, the well-connected pin region (middle strip edge region 436, edge region 702) has a width of approximately M*2-3 polysilicon pitch, where M is the width of the polysilicon pitch of the memory array that is not arranged adjacent to another memory array region, and has the width of the polysilicon pitch of the edge region (edge ​​region 502) of the n-well tap unit (n-well tap unit 514) and the p-well tap unit (p-well tap unit 516).

[0175] In various embodiments, the p-well tap unit (p-well tap unit 716) includes a continuous OD region (OD region 710) configured to provide reverse bias to the PN junctions in the first memory array and different PN junctions in the second memory array.

[0176] In various embodiments, the distance (spacing 725) between the n-wells (n-well 712) in the first region (first region 704) and the different n-wells (n-well 712) in the second region (second region 705) has approximately 3 times the polysilicon pitch width.

[0177] In various embodiments, the intermediate region (intermediate strip region 706) has a width of approximately 5 times the polysilicon pitch.

[0178] In various embodiments, a first tapless edge region (tapping edge region 428) is arranged along a first opposite edge of a first memory array region (first SRAM array 402), the first opposite edge being located on the opposite side of a first side (first side 403) of the first memory array region, wherein the first tapless edge region (tapping edge region 428) does not include an n-well tap unit or a p-well tap unit.

[0179] In various embodiments, the second tapless edge region (tapping edge region 430) is arranged along the second opposite edge of the second memory array region (second SRAM array 404), the second opposite edge being located on the opposite side of the second side (second side 405) of the second memory array region, wherein the second tapless edge region (tapping edge region 430) does not include an n-well tap unit or a p-well tap unit.

[0180] In various embodiments, the arrangement of the first memory array region (first SRAM array 402) and the arrangement of the second memory array region (second SRAM array 404) include inserting a plurality of SRAM cells (memory cells 190) in the layout region.

[0181] In various embodiments, inserting multiple SRAM cells (memory cells 190) in the layout area includes inserting multiple gate full-ring field-effect transistors in a six-transistor SRAM circuit topology.

[0182] In block 840, exemplary method 800 includes manufacturing an integrated circuit based on the arrangement of a first memory array region, the arrangement of a second memory array region, and the arrangement of pin regions.

[0183] Figure 9 As shown in some embodiments of the exemplary computer system 900, various embodiments of the present disclosure can be implemented in the exemplary computer system 900. The exemplary computer system 900 is configured by program instructions to perform the functions and operations described herein. For example, the exemplary computer system 900 is configured to arrange memory cells in an IC layout design using tools such as electronic design automation (EDA), but is not limited thereto. The exemplary computer system 900 is configured to perform one or more operations in exemplary method 800, which describes an exemplary method for arranging memory cells in a layout area.

[0184] The exemplary computer system 900 includes one or more processors (also referred to as central processing units or CPUs), such as processor 904. Processor 904 is connected to communication infrastructure or bus 906. The exemplary computer system 900 also includes input / output devices 903, such as a display, keyboard, pointing device, etc., which communicate with the communication infrastructure or bus 906 via input / output interface 902. EDA tools can receive instructions via input / output devices 903 to perform the functions and operations described herein, such as... Figure 8 The exemplary method 800. The exemplary computer system 900 also includes main memory 908, such as random access memory (RAM). Main memory 908 may include one or more levels of cache. Main memory 908 has stored control logic (e.g., computer software) and / or data therein. In some embodiments, control logic (e.g., computer software) and / or data may include previously referenced... Figure 8 One or more of the operations described in the exemplary method 800.

[0185] The exemplary computer system 900 may also include one or more auxiliary storage devices or memory 910. For example, auxiliary storage 910 may include hard disk 912 and / or removable storage device or disk drive 914. Removable storage disk drive 914 may be a floppy disk drive, magnetic tape drive, compact disk drive, optical storage device, tape backup device, and / or any other storage device / disk drive.

[0186] The removable storage disk drive 914 can interact with the removable storage unit 918. The removable storage unit 918 includes a computer-usable or readable storage device on which computer software (control logic) and / or data are stored. The removable storage unit 918 can be a floppy disk, magnetic tape, optical disc, digital versatile disc (DVD), optical storage disk, and / or any other computer data storage device. The removable storage disk drive 914 reads from and / or writes to the removable storage unit 918 in a known manner.

[0187] In some embodiments, the auxiliary storage 910 may include other tools, media, or other methods for allowing computer programs and / or other instructions and / or data to be accessed by the exemplary computer system 900. For example, such tools, media, or other methods may include removable storage unit 922 and interface 920. Examples of removable storage unit 922 and interface 920 may include a program cartridge and cartridge interface (e.g., found in video game devices), a removable memory chip (e.g., an erasable programmable read-only memory (EPROM) or programmable read-only memory (PROM)) and associated socket, a memory stick and universal serial bus (USB) port, a memory card and associated memory card slot, and / or any other removable storage unit and associated interface. In some embodiments, the auxiliary storage 910, removable storage unit 918, and / or removable storage unit 922 may include previously referenced... Figure 8 The exemplary method 800 describes one or more of the operations.

[0188] The exemplary computer system 900 may further include a communication or network interface 924. The communication interface 924 enables the exemplary computer system 900 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and commonly labeled with reference numeral 928). For example, the communication interface 924 may allow the exemplary computer system 900 to communicate with the remote device 928 via a communication path 926, which may be wired and / or wireless, and may include any combination of local area networks (LANs), wide area networks (WANs), the Internet, etc. Control logic and / or data may be transmitted to and from the exemplary computer system 900 via the communication path 926.

[0189] In various embodiments, when executing program instructions stored in main memory 908, the processor 904 of exemplary computer system 900 is configured to perform the following operations: arranging a first memory array region having a first side in a layout region; arranging a second memory array region having a second side in the layout region, wherein the second side faces the first side; arranging a pin region between the first memory array region along the first side and the second memory array region along the second side, the pin region having a first region containing n-well taps, a second region containing n-well taps, and an intermediate region disposed between the first and second regions and containing p-well taps, wherein a first edge region of the first region is arranged along the first side of the first memory array region, and a second edge region of the second region is arranged along the second side of the second memory array region; completing an integrated circuit layout including the first memory array region, the second memory array region, and the pin region for manufacturing purposes; generating an IC design layout diagram of the integrated circuit from the layout including the first memory array region, the second memory array region, and the pin region for manufacturing purposes; and providing the IC design layout diagram as a tangible output. The output is used to manufacture an IC that includes a first memory array region, a second memory array region, and a well pin region. In various embodiments, the IC design layout can be expressed in GDSII file format or DFII file format.

[0190] In various embodiments, the p-well tap unit includes a continuous OD region configured to provide reverse bias to different PN junctions in a first memory array region and a second memory array region. In various embodiments, the tap region has a width of approximately M*2-3 polysilicon pitch, where M is a memory array not adjacent to another memory array region, having the polysilicon pitch width of the edge regions of the n-well tap unit and the p-well tap unit. In various embodiments, the distance between different n-wells in the first region and in the second region is approximately 3 times the polysilicon pitch width. In various embodiments, the intermediate region has approximately 5 times the polysilicon pitch width.

[0191] In various embodiments, when executing program instructions stored in main memory 908, the processor 904 of exemplary computer system 900 is configured to further perform the following operations: arrange a first tapless edge region along a first opposite edge of a first memory array region, the first opposite edge being located on a side opposite to a first side of the first memory array region, wherein the first tapless edge region does not include an n-well tap or a p-well tap. In various embodiments, when executing program instructions stored in main memory 908, the processor 904 of exemplary computer system 900 is configured to further perform the following operations: arrange a second tapless edge region along a second opposite edge of a second memory array region, the second opposite edge being located on a side opposite to a second side of the second memory array region, wherein the second tapless edge region does not include an n-well tap or a p-well tap.

[0192] In various embodiments, the arrangement of the first memory array region and the arrangement of the second memory array region include inserting a plurality of static random access memory (SRAM) cells in the layout region. In various embodiments, the insertion of the plurality of SRAM cells includes inserting a plurality of gate full-ring field-effect transistors into a six-transistor SRAM circuit topology.

[0193] The operations described in the foregoing embodiments can be implemented with various configurations and architectures. Therefore, some or all of the operations described in the foregoing embodiments, for example... Figure 8 The exemplary method 800 can be implemented in hardware, software, or both. In some embodiments, it includes tangible means or articles of art that include a tangible computer-usable or readable medium on which control logic (software) is stored, also referred to herein as a computer program product or program storage device. This includes, but is not limited to, the exemplary computer system 900, main memory 908, auxiliary memory 910, and removable storage units 918 and 922, as well as tangible articles embodying any combination thereof. When such control logic is executed by one or more data processing means (e.g., the exemplary computer system 900), it causes these data processing means to operate as described herein.

[0194] Figure 10 This document describes an exemplary IC manufacturing system 1000 and its associated IC manufacturing processes, based on some embodiments. In some embodiments, the layout described herein, for example... Figure 4 The layout plan, along with related layout plans and circuit structures, can be manufactured using Manufacturing System 1000.

[0195] IC manufacturing system 1000 includes a design studio 1020, a photomask studio 1030, and an IC manufacturer / producer (“fab”) 1050, each of which interacts with each other in the design, development, and manufacturing cycle and / or services related to IC device 1060. The design studio 1020, photomask studio 1030, and fab 1050 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each of the design studio 1020, photomask studio 1030, and fab 1050 interacts with each other and provides and / or receives services from each other. In some embodiments, two or more of the design studio 1020, photomask studio 1030, and fab 1050 coexist in a common facility and use common resources.

[0196] Design Studio 1020 produced IC design layout schematic 1022. IC design layout schematic 1022 includes various geometric patterns, such as... Figure 4 The layout plan view and those related to the circuit structure are included. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1060 to be manufactured. Various thin layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1022 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, and conductive segments or vias for interlayer interconnection. The design studio 1020 performs appropriate design procedures to form the IC design layout diagram 1022. The design procedures include one or more of logic design, physical design, or place and route design. The IC design layout diagram 1022 can be presented in one or more data files containing geometric pattern information. For example, the IC design layout diagram 1022 can be represented in Graphics Data System II (GDSII) file format or DFII file format.

[0197] Photomask studio 1030 includes data preparation 1032 and photomask fabrication 1044. Photomask studio 1030 uses an IC design layout schematic 1022 to fabricate one or more photomasks 1045 for fabricating various thin layers of an IC device 1060. Photomask studio 1030 performs photomask data preparation 1032, in which the IC design layout schematic 1022 is converted into a representative data file (“RDF”). Photomask data preparation 1032 provides the RDF to photomask fabrication 1044. Photomask fabrication 1044 includes a photomask writer that converts the RDF into an image on a substrate, such as a photomask (reticle) 1045 or a semiconductor wafer 1053. The IC design layout schematic 1022 can be manipulated by photomask data preparation 1032 to conform to the specific characteristics of the photomask writer and / or the requirements of the fabrication plant 1050. Figure 10 In this context, data preparation 1032 and photomask fabrication 1044 can be collectively referred to as "photomask data preparation".

[0198] In some embodiments, data preparation 1032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout. (See schematic 1022). In some embodiments, data preparation 1032 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) can also be used, which treats OPC as an inverse imaging problem.

[0199] In some embodiments, data preparation 1032 includes a mask rule checker (MRC) that can check an IC design layout schematic 1022 that has undergone OPC processes using a set of mask creation rules. These rules include geometric and / or connectivity constraints to ensure sufficient margins to address variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout schematic 1022 to compensate for constraints during photomask fabrication 1044, which can reverse some modifications performed by OPC to meet the photomask creation rules.

[0200] In some embodiments, data preparation 1032 includes lithography process checking (LPC), a simulation of the process to be performed by manufacturing plant 1050 to manufacture IC device 1060. LPC simulates this process based on IC design layout schematic 1022 to create a simulated device to be manufactured, such as IC device 1060. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the equipment used for IC manufacturing, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), and other suitable factors. In some embodiments, after creating the simulated device to be manufactured via LPC, and if the simulated device does not meet design criteria, OPC and / or MRC may be repeated to further refine the IC design layout schematic 1022.

[0201] In some embodiments, data preparation 1032 includes additional features such as logic operations (LOPs) to modify the IC design layout schematic 1022 according to manufacturing guidelines. The processes applied to the IC design layout schematic 1022 during data preparation 1032 may be performed in a different order than described above.

[0202] Following data preparation 1032 and during photomask fabrication 1044, a photomask 1045, or a group of photomasks 1045, is fabricated based on a modified IC design layout schematic 1022. In some embodiments, photomask fabrication 1044 includes performing one or more photolithographic exposures based on the IC design layout schematic 1022. In some embodiments, an electron beam or multiple electron beam mechanism is used to form a pattern on the photomask (photomask or tracing sheet) 1045 based on the modified IC design layout schematic 1022.

[0203] Various techniques can be used to form the photomask 1045. In some embodiments, binary technology is used to form the photomask 1045. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, can be used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer. The radiation beam is blocked by the opaque areas and transmits through the transparent areas. For example, a binary photomask version of photomask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary photomask.

[0204] In some embodiments, a phase-shifting technique is used to form the photomask 1045. In the phase-shift mask (PSM) version of the photomask 1045, various features in the pattern formed on the phase-shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. For example, the phase-shift mask may be an attenuated PSM or an alternating PSM.

[0205] The photomask produced by photomask fabrication 1044 is used in a variety of processes. For example, this photomask can be used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0206] Manufacturing plant 1050 includes wafer fabrication 1052. Manufacturing plant 1050 may include one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, manufacturing plant 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility providing back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility providing other services for foundry operations.

[0207] Manufacturing plant 1050 uses a photomask 1045 manufactured by photomask workshop 1030 to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by manufacturing plant 1050 using photomask 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based on IC design layout schematic 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1053 further includes various doped regions, dielectric features, multilayer interconnects, and other suitable features.

[0208] In some ways, the techniques described herein relate to a method of manufacturing a semiconductor device for arranging memory cells. The method of manufacturing the aforementioned semiconductor device includes: arranging a first memory array region having a first side in a layout region; arranging a second memory array region having a second side facing the first side in the layout region; arranging a well-connected pin region between the first memory array region along the first side and the second memory array region along the second side, the well-connected pin region having a first region including a first n-well tap unit, a second region including a second n-well tap unit, and an intermediate region disposed between the first region and the second region and including a p-well tap unit, wherein a first edge region of the first region is arranged along the first side of the first memory array region, and a second edge region of the second region is arranged along the second side of the second memory array region; and manufacturing an integrated circuit based on the arrangement of the first memory array region, the arrangement of the second memory array region, and the arrangement of the well-connected pin region; wherein the well-connected pin region has a width of approximately M*2-3 polysilicon pitch, where M is the polysilicon pitch width of an edge region having one n-well tap unit and one p-well tap unit of a memory array not adjacent to another memory array region; and wherein the arrangement of the first memory array region, the arrangement of the second memory array region, and the arrangement of the well-connected pin region are executed by one or more processors.

[0209] In some embodiments, the techniques described herein relate to a method of manufacturing the aforementioned semiconductor device, wherein: the p-well tap cell includes a continuous oxide definition (OD) region configured to provide reverse bias to a PN junction in a first memory array region and to different PN junctions in a second memory array region.

[0210] In some embodiments, the techniques described herein relate to a method of manufacturing the aforementioned semiconductor device, wherein the distance between n-wells in the first region and different n-wells in the second region is approximately three times the polysilicon pitch.

[0211] In some embodiments, the techniques described herein relate to a method of manufacturing the aforementioned semiconductor device, wherein the intermediate region has a width approximately five times the width of the polysilicon pitch.

[0212] In some embodiments, the techniques described herein relating to the manufacturing method of the aforementioned semiconductor device further include arranging a first tap-free edge region along a first opposite edge of a first memory array region, wherein the first opposite edge is located on a side opposite to a first side of the first memory array region, and the first tap-free edge region does not include an n-well tap or a p-well tap.

[0213] In some embodiments, the techniques described herein relating to the manufacturing method of the aforementioned semiconductor device further include arranging a second tap-free edge region along a second opposite edge of a second memory array region, wherein the second opposite edge is located on a side opposite to a second side of the second memory array region, and the second tap-free edge region does not include an n-well tap or a p-well tap.

[0214] In some embodiments, the techniques described herein relate to a method of manufacturing the aforementioned semiconductor device, wherein the arrangement of a first memory array region and the arrangement of a second memory array region include inserting a plurality of static random access memory (SRAM) cells in the layout region.

[0215] In some embodiments, the techniques described herein relate to a method of manufacturing the aforementioned semiconductor device, wherein the insertion of a plurality of SRAM cells in a layout region includes the insertion of a plurality of gate full-ring field-effect transistors in a six-transistor SRAM circuit topology.

[0216] In some ways, the techniques described herein relate to a computer system. The aforementioned computer system includes a memory configured to store a plurality of instructions; and a processor configured to perform the following operations when executing the plurality of instructions: arranging a first memory array region having a first side in a layout region; arranging a second memory array region having a second side facing the first side in the layout region; arranging a well pin region between the first memory array region along the first side and the second memory array region along the second side, the well pin region having a first region including a first n-well tap unit, a second region including a second n-well tap unit, and an intermediate region disposed between the first region and the second region and including a p-well tap unit, wherein a first edge region of the first region is arranged along the first side of the first memory array region, and a second edge region of the second region is arranged along the second side of the second memory array region; completing an integrated circuit layout including the first memory array region, the second memory array region, and the well pin region for manufacturing; and generating an IC design layout diagram of an integrated circuit from the integrated circuit layout including the first memory array region, the second memory array region, and the well pin region; wherein the p-well tap unit includes a continuous oxide definition (OD) region, the OD region being configured to provide reverse bias to different PN junctions in the first memory array region and the second memory array region.

[0217] In some embodiments, the technology described herein relates to the aforementioned computer system, wherein: the well pin region has a width of approximately M*2-3 polysilicon pitch, where M is the polysilicon pitch width of the edge region of a memory array arranged not adjacent to another memory array region, having an n-well tap unit and a p-well tap unit.

[0218] In some embodiments, the techniques described herein relate to the aforementioned computer system, wherein the distance between n-wells in the first region and different n-wells in the second region has approximately 3 polysilicon spacing.

[0219] In some embodiments, the techniques described herein relate to the aforementioned computer system, wherein the intermediate region has a width of approximately 5 polysilicon pitches.

[0220] In some embodiments, the technology described herein relates to the aforementioned computer system, wherein the processor is further configured to perform the following operations: arranging a first tapless edge region along a first opposite edge of a first memory array region, wherein the first opposite edge is located on a side opposite to a first side of the first memory array region, and the first tapless edge region does not include an n-well tap or a p-well tap.

[0221] In some embodiments, the technology described herein relates to the aforementioned computer system, wherein the processor is further configured to perform the following operations: arranging a second tapless edge region along a second opposite edge of a second memory array region, wherein the second opposite edge is located on a side opposite to a second side of the second memory array region, and the second tapless edge region does not include an n-well tap or a p-well tap.

[0222] In some embodiments, the techniques described herein relate to the aforementioned computer system, wherein the arrangement of the first memory array region and the arrangement of the second memory array region include inserting a plurality of static random access memory (SRAM) cells in the layout region.

[0223] In some embodiments, the techniques described herein relate to the aforementioned computer system in which multiple SRAM cells are inserted in a layout area, including the insertion of multiple gate full-ring field-effect transistors in a six-transistor SRAM circuit topology.

[0224] In some embodiments, the technology described herein relates to a semiconductor device. The semiconductor device includes: a first memory array region having a first side; a second memory array region having a second side facing the first side, wherein the first memory array region and the second memory array region include a plurality of static random access memory (SRAM) cells; and a well-pin region disposed between the first memory array region along the first side and the second memory array region along the second side, the well-pin region having a first region including a first n-well tap unit, a second region including a second n-well tap unit, and an intermediate region disposed between the first region and the second region and including a p-well tap unit, wherein a first edge region of the first region is arranged along the first side of the first memory array region, and a second edge region of the second region is arranged along the second side of the second memory array region; wherein the p-well tap unit includes a continuous oxide definition (OD) region configured to provide reverse bias to PN junctions in the first memory array region and different PN junctions in the second memory array region.

[0225] In some embodiments, the techniques described herein relate to the aforementioned semiconductor device, wherein: the distance between n-wells in the first region and different n-wells in the second region has a polysilicon pitch of approximately 3; and the intermediate region has a width of approximately 5 polysilicon pitch.

[0226] In some embodiments, the technology described herein relating to the aforementioned semiconductor device further includes: a first tap-free edge region disposed along a first opposite edge of a first memory array region, wherein the first opposite edge is located on a side opposite to a first side of the first memory array region, and the first tap-free edge region does not include an n-well tap or a p-well tap; and a second tap-free edge region disposed along a second opposite edge of a second memory array region, wherein the second opposite edge is located on a side opposite to a second side of the second memory array region, and the second tap-free edge region does not include an n-well tap or a p-well tap.

[0227] In some embodiments, the techniques described herein relate to the aforementioned semiconductor device, wherein a plurality of SRAM cells include a plurality of gate full-ring field-effect transistors disposed in a six-transistor SRAM circuit topology.

[0228] The foregoing outlines the features of various embodiments or examples to enable those skilled in the art to better understand the manner of this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor device, characterized by comprising: comprises: a first memory array region having a first side; a second memory array region having a second side facing the first side, wherein the first memory array region and the second memory array region comprise a plurality of static random access memory cells; and a well contact region disposed between the first memory array region along the first side and the second memory array region along the second side, the well contact region having a first region comprising a first n-well contact cell, a second region comprising a second n-well contact cell, and an intermediate region disposed between the first region and the second region and comprising a p-well contact cell, wherein a first edge region of the first region is disposed along the first side of the first memory array region and a second edge region of the second region is disposed along the second side of the second memory array region, wherein the p-well contact cell comprises a continuous oxide definition region configured to provide a reverse bias to a P-N junction in the first memory array region and a different P-N junction in the second memory array region.

2. The semiconductor device of claim 1, wherein: a distance between an n-well in the first region and a different n-well in the second region has a distance of 3 times a polysilicon pitch.

3. The semiconductor device of claim 1, wherein: the intermediate region has a width of 5 times a polysilicon pitch.

4. The semiconductor device according to claim 1, wherein further comprising: a first untapped edge region disposed along a first opposing edge of the first memory array region, wherein the first opposing edge is on a side opposite the first side of the first memory array region.

5. The semiconductor device according to claim 4, wherein further comprising: a first input / output region disposed at the first opposing edge of the first memory array region, wherein the first untapped edge region is between the first memory array region and the first input / output region.

6. The semiconductor device according to claim 1, wherein further comprising: a second untapped edge region disposed along a second opposing edge of the second memory array region, wherein the second opposing edge is on a side opposite the second side of the second memory array region.

7. The semiconductor device of claim 6, wherein: the second untapped edge region does not include an n-well contact cell or a p-well contact cell.

8. The semiconductor device of claim 1, wherein: the well contact region has a width of M*2-3 polysilicon pitches, where M is a polysilicon pitch width of an edge region of a memory array having one n-well contact cell and one p-well contact cell that is not disposed adjacent to another memory array region.

9. The semiconductor device of claim 1, wherein: an n-well in the first region extends into the intermediate region; and a different n-well in the second region extends into the intermediate region.

10. The semiconductor device according to claim 1, wherein The static random access memory cell includes a plurality of gate-all-around field effect transistors disposed in a six-transistor static random access memory circuit topology.

Images