Display panel and display device

Abstract

The utility model relates to a display panel and a display device. The display panel comprises a plurality of pixel regions; the display panel further comprises an array substrate, an anode layer and a pixel definition layer. The anode layer is arranged on one side of the array substrate, and the anode layer comprises a plurality of anodes arranged corresponding to the plurality of pixel areas; the pixel definition layer is arranged on the side, provided with the anode layer, of the array substrate and surrounds the pixel areas, and the pixel definition layer comprises a first retaining wall arranged along the first side edges of the pixel areas; wherein the first retaining wall comprises a first sub-part located on the side, away from the array substrate, of the anode, the orthographic projection, on the array substrate, of the first sub-part is located in the orthographic projection, on the array substrate, of the anode, and the maximum thickness of the first sub-part is smaller than or equal to 2.5 times of the thickness of the anode; according to the display panel, the film shrinkage degree of the pixel definition layer in the heating process in the manufacturing process can be reduced, so that the stress of the film shrinkage of the pixel definition layer on the anode is reduced, the probability of breakage of the anode is reduced, and the yield and the display effect of the display panel are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a new type of current-driven semiconductor light-emitting device. They emit light by controlling the carriers and activating organic materials, representing a self-emissive technology. Compared to passively emitting liquid crystal displays (LCDs), self-emissive OLED displays offer advantages such as faster response times, higher contrast ratios, and wider viewing angles. Furthermore, they are easily made flexible and are widely favored in the industry, with many believing that OLED display panels are highly likely to become the mainstream product of the next generation of display technology.

[0003] The OLED display panel includes an array substrate, an anode on the array substrate, and a pixel definition layer on the anode. During the heating process of the pixel definition layer, the shrinkage of the pixel definition layer will generate a large stress on the anode, causing the anode to crack due to stress, resulting in display defects and other phenomena in the display panel. Utility Model Content

[0004] This application provides a display panel and display device that can reduce the stress on the anode caused by film shrinkage in the pixel definition layer, thereby reducing the probability of anode cracking.

[0005] This application embodiment provides a display panel, the display panel including a plurality of pixel areas;

[0006] Array substrate;

[0007] An anode layer is disposed on one side of the array substrate, and the anode layer includes a plurality of anodes disposed corresponding to a plurality of pixel regions;

[0008] A pixel definition layer is disposed on the side of the array substrate where the anode layer is provided and surrounds each pixel region. The pixel definition layer includes a first barrier wall disposed along a first side edge of the pixel region.

[0009] The first barrier includes a first sub-section located on the side of the anode away from the array substrate. The orthographic projection of the first sub-section on the array substrate is located within the orthographic projection of the anode on the array substrate. The maximum thickness of the first sub-section is less than or equal to 2.5 times the thickness of the anode.

[0010] In one embodiment of this application, the maximum thickness of the first sub-part is greater than or equal to the thickness of the anode.

[0011] In one embodiment of this application, the first barrier further includes a second sub-part connected to the first sub-part, wherein the orthographic projection of the second sub-part on the array substrate does not overlap with the orthographic projection of the anode on the array substrate;

[0012] The thickness of the first sub-part decreases along the direction of the second sub-part it is connected to on the side closest to it.

[0013] In one embodiment of this application, the pixel region includes two first sides and two second sides arranged opposite to each other, and a plurality of pixel regions are arranged along a first direction and a second direction, wherein the first direction is parallel to the first side and the second direction is parallel to the second side.

[0014] The first barrier between two adjacent pixel regions along the second direction includes two first sub-parts and one second sub-part, wherein the second sub-part is connected between the two first sub-parts, and the two first sub-parts are respectively located on the two anodes corresponding to the two pixel regions.

[0015] In one embodiment of this application, the pixel definition layer further includes a second barrier wall disposed along the second side, at least a portion of the second barrier wall being located on the side of the anode away from the array substrate, and the distance from the side of the second barrier wall away from the array substrate to the array substrate being greater than the distance from the side of the first barrier wall away from the array substrate to the array substrate.

[0016] In one embodiment of this application, the pixel definition layer further includes a third barrier wall disposed along the second side, the third barrier wall being located between the anode and the second barrier wall;

[0017] The third retaining wall is connected to the first retaining wall at the intersection of the first side and the second side, and the material of the third retaining wall is the same as that of the first retaining wall.

[0018] In one embodiment of this application, the maximum thickness of the third barrier wall located on the side of the anode away from the array substrate is greater than or equal to the thickness of the anode, and less than or equal to 2.5 times the thickness of the anode.

[0019] In one embodiment of this application, the light-emitting functional layer includes a first light-emitting pixel group, a second light-emitting pixel group, and a third light-emitting pixel group arranged alternately along the first direction. The first light-emitting pixel group includes a plurality of first light-emitting pixels arranged along the second direction, the second light-emitting pixel group includes a plurality of second light-emitting pixels arranged along the second direction, and the third light-emitting pixel group includes a plurality of third light-emitting pixels arranged along the second direction.

[0020] The display panel further includes a cathode layer disposed on the side of the light-emitting functional layer away from the array substrate, the cathode layer covering a plurality of first light-emitting pixels, a plurality of second light-emitting pixels, a plurality of third light-emitting pixels, and the side of the first barrier away from the array substrate.

[0021] In one embodiment of this application, the anode material includes silver.

[0022] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including the display panel.

[0023] This application provides a display panel and display device. By limiting the thickness of the pixel definition layer located on the anode, the maximum thickness of the first sub-part located on the anode is less than or equal to 2.5 times the thickness of the anode. This effectively reduces the film shrinkage of the pixel definition layer during the heating process, thereby reducing the stress generated by the film shrinkage of the pixel definition layer on the anode, reducing the probability of anode cracking, and improving the yield and display effect of the display panel.

[0024] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0027] Figure 1 This is a schematic diagram of a planar distribution of a display panel provided in an embodiment of this application;

[0028] Figure 2 Provided for the embodiments of this application Figure 1 A schematic diagram of a cross-sectional structure obtained along line AA.

[0029] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of a planar distribution of the light-emitting functional layer provided in an embodiment of this application;

[0031] Figure 5 Provided for the embodiments of this application Figure 1 A schematic diagram of another cross-sectional structure obtained along line AA;

[0032] Figure 6 Provided for the embodiments of this application Figure 1 A schematic diagram of a cross-sectional structure obtained along line BB;

[0033] Figure 7 A thickness variation verification curve of the first sub-part provided for embodiments of this application;

[0034] Figure 8 Provided for the embodiments of this application Figure 1 A schematic diagram of a cross-sectional structure obtained along the CC line;

[0035] Figure 9 This is a schematic diagram of another planar distribution of the display panel provided in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 10. Array substrate; 101. Pixel area; 1011. First side; 1012. Second side; 11. First light-emitting pixel group; 111. First light-emitting pixel; 12. Second light-emitting pixel group; 121. Second light-emitting pixel; 13. Third light-emitting pixel group; 131. Third light-emitting pixel; 14. Substrate; 15. Thin-film transistor layer; 151. Thin-film transistor; 1511. Semiconductor; 1512. First gate; 1513. Second gate; 1514. Source; 1515. Drain; 152. Buffer layer; 153. First gate insulating layer; 154. Second gate insulating layer; 155. First interlayer dielectric layer; 156. Second interlayer dielectric layer; 16. First planarization layer; 17. Second planarization layer; 18. Transition section;

[0038] 20. Anode layer; 21. Anode; 211. First sublayer; 212. Second sublayer; 213. Third sublayer;

[0039] 30. Pixel definition layer; 31. First barrier; 311. First sub-section; 312. Second sub-section; 32. Second barrier; 33. Third barrier;

[0040] 40. Cathode layer. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0042] Currently, OLED display panels include an array substrate, an anode on the array substrate, and a pixel definition layer on the anode. During the heating process of the pixel definition layer, the shrinkage of the pixel definition layer will generate significant stress on the anode. The anode is prone to cracking due to stress, which leads to the precipitation of anode material. The pixel definition layer cannot effectively cover the precipitated anode material, which can easily cause a short circuit between the anode and the electrode above (such as the cathode layer), resulting in dark spots on the display panel.

[0043] Please refer to Figure 1 and Figure 2 This application provides a display panel, which includes a plurality of pixel regions 101. The display panel also includes an array substrate 10, an anode layer 20, and a pixel definition layer 30. The anode layer 20 is disposed on one side of the array substrate 10 and includes a plurality of anodes 21 disposed corresponding to the plurality of pixel regions 101. The pixel definition layer 30 is disposed on the side of the array substrate 10 where the anode layer 20 is disposed and surrounds each pixel region 101. The pixel definition layer 30 includes a first barrier 31 disposed along a first side 1011 of the pixel region 101.

[0044] The first barrier 31 includes a first sub-part 311 located on the side of the anode 21 away from the array substrate 10. The orthographic projection of the first sub-part 311 on the array substrate 10 is located within the orthographic projection of the anode 21 on the array substrate 10. The maximum thickness H1 of the first sub-part 311 is less than or equal to 2.5 times the thickness H2 of the anode 21.

[0045] In the implementation process, this application embodiment limits the thickness of the pixel definition layer 30 located on the anode 21, so that the maximum thickness H1 of the first sub-part 311 located on the anode 21 is less than or equal to 2.5 times the thickness H2 of the anode 21. This effectively reduces the degree of film shrinkage of the pixel definition layer 30 during the heating process, thereby reducing the stress generated by the film shrinkage of the pixel definition layer 30 on the anode 21, reducing the probability of the anode 21 cracking, and improving the yield and display effect of the display panel.

[0046] Specifically, please continue to combine Figure 1 , Figure 2 as well as Figure 3 The display panel includes the array substrate 10, an anode layer 20 disposed on the array substrate 10, a pixel definition layer 30 disposed on the anode layer 20, a light-emitting functional layer and a cathode layer 40 disposed on the anode layer 20 and the pixel definition layer 30.

[0047] In some embodiments, the array substrate 10 includes a substrate 14 and a thin-film transistor layer 15 disposed on the substrate 14; the substrate 14 may be a rigid substrate, such as a glass substrate; or, the substrate 14 may be a flexible substrate, such as a substrate formed of polyimide. When the substrate 14 is a flexible substrate, the substrate 14 may be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates may be bonded together by adhesive sub-layers.

[0048] In some embodiments, the thin-film transistor layer 15 includes a buffer layer 152 disposed on the substrate 14 and a thin-film transistor 151 disposed on the side of the buffer layer 152 away from the substrate 14. The thin-film transistor 151 includes a semiconductor 1511 located on the buffer layer 152, and the semiconductor 1511 may be formed of polycrystalline silicon or a metal oxide (such as indium gallium zinc oxide). The semiconductor 1511 is divided into a channel region and source and drain regions formed on both sides of the channel region. The thin-film transistor layer 15 further includes a first gate insulating layer 153 covering the semiconductor 1511. The thin-film transistor 151 also includes a first gate 1512 formed on the first gate insulating layer 153, the first gate 1512 overlapping the channel region. The first gate 1512 may be formed as multiple layers or a single layer comprising low-resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance. The thin-film transistor layer 15 further includes a second gate insulating layer 154, which covers the first gate 1512. The thin-film transistor 151 also includes a second gate 1513 located on the second gate insulating layer 154, overlapping the first gate 1512. The second gate 1513 can be formed as multiple layers or a single layer comprising low-resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance. The thin-film transistor layer 15 also includes a first interlayer insulating layer 155 formed on the second gate 1513. The first interlayer insulating layer 155, the first gate insulating layer 153, and the second gate insulating layer 154 include source contact holes and drain contact holes, with the source region and the drain region exposed through the source contact holes and drain contact holes, respectively.

[0049] The thin-film transistor 151 further includes a source 1514 and a drain 1515 disposed on the same layer. Both the source 1514 and the drain 1515 are formed on the first interlayer insulating layer 155. The source 1514 is connected to the source region through the source contact hole, and the drain 1515 is connected to the drain region through the drain contact hole. The source 1514 and the drain 1515 can be multiple layers or a single layer formed of low-resistance materials such as Al, Ti, Mo, Cu, Ni, or their alloys, or materials with high corrosion resistance. For example, the source 1514 and the drain 1515 can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single-layer or multi-layer structures.

[0050] In some embodiments, the thin-film transistor layer 15 further includes a second interlayer insulating layer 156 located on the side of the first interlayer insulating layer 155 away from the substrate 14, the second interlayer insulating layer 156 covering the source 1514 and the drain 1515.

[0051] In some embodiments, the array substrate 10 further includes a first planarization layer 16, a second planarization layer 17, and a transition portion 18 disposed on the side of the second interlayer insulating layer 156 away from the first interlayer insulating layer 155; wherein, the first planarization layer 16 is located between the second interlayer insulating layer 156 and the second planarization layer 17, the transition portion 18 is located on the first planarization layer 16 and covered by the second planarization layer 17, the transition portion 18 passes through the first planarization layer 16 and is connected to the source electrode 1514 or the drain electrode 1515, and in this embodiment, the transition portion 18 is connected to the drain electrode 1515 as an example.

[0052] In some embodiments, the anode layer 20 is disposed on the side of the second planarization layer 17 away from the first planarization layer 16. The anode layer 20 includes a plurality of anodes 21 disposed corresponding to a plurality of pixel regions 101, and the anodes 21 are disposed within the corresponding pixel regions 101 and partially extend outside the pixel regions 101. The anodes 21 are connected to the source electrode 1514 or the drain electrode 1515 through the adapter portion 18.

[0053] In some embodiments, the pixel definition layer 30 is disposed on the second planarization layer 17. Meanwhile, the pixel definition layer 30 is located on the side of the anode layer 20 away from the array substrate 10, and the pixel definition layer 30 has a plurality of pixel openings. The plurality of pixel openings are correspondingly disposed with a plurality of anodes 21, and the pixel openings expose a portion of the surface of the corresponding anode 21.

[0054] It is understood that the pixel opening is an opening in the pixel definition layer 30 corresponding to the pixel area 101, and the pixel definition layer 30 covers the portion of the anode 21 that extends beyond the pixel area 101, and the pixel definition layer 30 is arranged around the plurality of pixel areas 101.

[0055] In some embodiments, the pixel region 101 includes two first sides 1011 and two second sides 1012 arranged opposite to each other, and the direction parallel to the first side 1011 is defined as the first direction X, and the direction parallel to the second side 1012 is defined as the second direction Y. The plurality of pixel regions 101 are arranged in multiple rows and columns along the first direction X and the second direction Y.

[0056] In some embodiments, the first direction X and the second direction Y are perpendicular.

[0057] In some embodiments, in the pixel area 101, two oppositely arranged first sides 1011 are parallel to each other, and two oppositely arranged second sides 1012 are parallel to each other. The two second sides 1012 are connected between the two first sides 1011, so that the pixel area 101 is rectangular, and the length of the first side 1011 can be less than the length of the second side 1012.

[0058] In some embodiments, the light-emitting functional layer includes a plurality of light-emitting pixels, and the plurality of light-emitting pixels are disposed corresponding to a plurality of pixel regions 101 and located on the anode 21 within the corresponding pixel region 101.

[0059] In some embodiments, please combine Figure 1 , Figure 2 as well as Figure 4 The light-emitting functional layer includes a first light-emitting pixel group 11, a second light-emitting pixel group 12, and a third light-emitting pixel group 13 arranged alternately along the first direction X. The first light-emitting pixel group 11 includes a plurality of first light-emitting pixels 111 arranged along the second direction Y. The second light-emitting pixel group 12 includes a plurality of second light-emitting pixels 121 arranged along the second direction Y. The third light-emitting pixel group 13 includes a plurality of third light-emitting pixels 131 arranged along the second direction Y.

[0060] In some embodiments, the first light-emitting pixel 111 is disposed on the anode 21 in the corresponding pixel area 101 and may be a red organic light-emitting layer, the second light-emitting pixel 121 is disposed on the anode 21 in the corresponding pixel area 101 and may be a green organic light-emitting layer, and the third light-emitting pixel 131 is disposed on the anode 21 in the corresponding pixel area 101 and may be a blue organic light-emitting layer.

[0061] Furthermore, please combine Figure 1 , Figure 4 , Figure 5 as well as Figure 6 The display panel further includes a cathode layer 40 disposed on the side of the light-emitting functional layer away from the array substrate 10, the cathode layer 40 covering the light-emitting functional layer and the pixel definition layer 30.

[0062] In some embodiments, the pixel definition layer 30 includes a first barrier 31 disposed along the first side 1011. The first barrier 31 extends along the first direction X and is located on the upper and lower sides of a plurality of pixel areas 101 in each row, and is located between two adjacent pixel areas 101 along the second direction Y. In the case of two adjacent pixel areas 101 along the second direction Y, the first barrier 31 covers a portion of the surface of the two anodes 21 corresponding to the two pixel areas 101 and the interval area between the two anodes 21.

[0063] In some embodiments, the anode 21 is made of silver. During the heating process of the pixel definition layer 30, the shrinkage of the pixel definition layer 30 will generate significant stress on the anode 21. The anode 21 is prone to cracking due to stress, which causes silver to precipitate out of the anode 21. The pixel definition layer 30 cannot effectively cover the precipitated silver, which can easily lead to a short circuit between the anode 21 and the cathode layer 40 above it, resulting in dark spots on the display panel.

[0064] In this embodiment, the first barrier 31 includes a first sub-part 311 disposed on the side of the anode 21 away from the array substrate 10, wherein the maximum thickness H1 of the first sub-part 311 is less than or equal to 2.5 times the thickness H2 of the anode 21, and the cathode layer 40 covers a plurality of first light-emitting pixels 111, a plurality of second light-emitting pixels 121, a plurality of third light-emitting pixels 131, and the side of the first sub-part 311 away from the array substrate 10; thereby, this embodiment can effectively reduce the degree of film shrinkage of the pixel definition layer 30 during the heating process, reduce the stress generated by the film shrinkage of the pixel definition layer 30 on the anode 21, reduce the probability of the anode 21 cracking, and improve the yield and display effect of the display panel.

[0065] Furthermore, in some embodiments, the first barrier 31 further includes a second sub-part 312 connected to the first sub-part 311, the orthographic projection of the second sub-part 312 on the array substrate 10 not overlapping with the orthographic projection of the anode 21 on the array substrate 10; the thickness of the first sub-part 311 on the side connected to the second sub-part 312 decreases in the direction close to the second sub-part 312; thus, at the edge D of the anode 21, the thickness of the first barrier 31 is smaller, and the distance between the anode 21 and the cathode layer 40 is also smaller, therefore, the anode 21 and the cathode layer 40 are prone to short-circuiting at the edge D of the anode 21; in this embodiment, the maximum thickness H1 of the first sub-part 311 is greater than or equal to the thickness H2 of the anode 21, that is, in this embodiment, the thickness of the first sub-part 311 cannot be too large or too small. If the thickness of the first sub-part 311 is too small, it is easy for a short circuit to occur between the anode 21 and the cathode layer 40 at D.

[0066] In some embodiments, such as Figure 6 As shown, the first barrier 31 between two adjacent pixel regions 101 along the second direction Y includes two first sub-parts 311 and one second sub-part 312, wherein the second sub-part 312 is connected between the two first sub-parts 311, the two first sub-parts 311 are respectively located on the two anodes 21 corresponding to the two pixel regions 101, and the second sub-part 312 is located between the two anodes 21 corresponding to the two pixel regions 101.

[0067] Please combine Figure 5 as well as Figure 7 In this embodiment of the application, the relationship between the thickness H2 of the anode 21 and the maximum thickness H1 of the first sub-part 311 is verified to obtain... Figure 7 The graph shown indicates that when the maximum thickness H1 of the first sub-part 311 is greater than or equal to the thickness H2 of the anode 21, and less than or equal to 2.5 times the thickness H2 of the anode 21, the anode 21 will not crack and deposit silver, and the anode 21 will not short-circuit with the cathode layer 40.

[0068] Furthermore, the material of the anode 21 may include silver, and the material of the anode 21 may also include at least one of indium tin oxide, indium zinc oxide, and tungsten oxide. For example, the anode 21 may include a first sub-layer 211, a second sub-layer 212, and a third sub-layer 213 stacked together, and the second sub-layer 212 is located between the first sub-layer 211 and the third sub-layer 213. The first sub-layer 211 and the third sub-layer 213 may both be indium tin oxide layers, and the second sub-layer 212 may be a silver layer.

[0069] Furthermore, please combine Figure 1 , Figure 4 , Figure 8 as well as Figure 9 In some embodiments, the pixel definition layer 30 further includes a second barrier 32 disposed along the second side 1012, wherein the second barrier 32 extends along the second direction Y and is located on the left and right sides of the pixel area 101, and the second barrier 32 is disposed between two adjacent pixel areas 101 along the first direction X.

[0070] At least a portion of the second barrier 32 is located on the side of the anode 21 away from the array substrate 10, and the distance from the side of the second barrier 32 away from the array substrate 10 to the array substrate 10 is greater than the distance from the side of the first barrier 31 away from the array substrate 10 to the array substrate 10.

[0071] Wherein, the first barrier 31 is located between two adjacent pixel areas 101 along the second direction Y, and the second barrier 32 is located between two adjacent pixel areas 101 along the first direction X. The distance from the side of the second barrier 32 away from the array substrate 10 to the array substrate 10 is greater than the distance from the side of the first barrier 31 away from the array substrate 10 to the array substrate 10. Thus, two adjacent light-emitting pixels along the second direction Y can be connected, and two adjacent light-emitting pixels along the first direction X are spaced apart.

[0072] In some embodiments, the pixel definition layer 30 further includes a third baffle 33 disposed along the second side 1012. The third baffle 33 may extend along the second direction Y and is located between two adjacent pixel regions 101 along the first direction X. The third baffle 33 is located between the anode 21 and the second baffle 32, i.e., at the second side 1012 of the pixel region 101. The pixel definition layer 30 is a stacked structure of the third baffle 33 and the second baffle 32. Figure 7 As shown, the thickness of the pixel definition layer 30 at the second side 1012 is greater than the thickness of the pixel definition layer 30 at the first side 1011.

[0073] In some embodiments, the third barrier 33 is connected to the first barrier 31 at the intersection of the first side 1011 and the second side 1012. The material of the third barrier 33 is the same as that of the first barrier 31, that is, the first barrier 31 and the third barrier 33 can be an integrally formed structure, and the first barrier 31 and the third barrier 33 can be formed in the same photomask.

[0074] It is understandable that, since the first barrier wall 31 and the third barrier wall 33 can be integrally formed, and the first barrier wall 31 and the third barrier wall 33 can be formed in the same photomask, the maximum thickness H3 of the third barrier wall 33 located on the side of the anode 21 away from the array substrate 10 is greater than or equal to the thickness H2 of the anode 21, and less than or equal to 2.5 times the thickness H2 of the anode 21. This can also reduce the probability of the anode 21 cracking at the second side 1012 layer, resulting in silver precipitation, and the probability of a short circuit between the anode 21 and the cathode layer 40.

[0075] In summary, by limiting the thickness of the pixel definition layer 30 located on the anode 21, the maximum thickness H1 of the first sub-part 311 on the anode 21 is less than or equal to 2.5 times the thickness H2 of the anode 21. This effectively reduces the film shrinkage of the pixel definition layer 30 during the heating process, thereby reducing the stress on the anode 21 caused by the film shrinkage of the pixel definition layer 30, lowering the probability of the anode 21 cracking, and improving the yield and display effect of the display panel. At the same time, the maximum thickness H1 of the first sub-part 311 is greater than or equal to the thickness H2 of the anode 21, avoiding the probability of a short circuit between the anode 21 and the cathode layer 40 at the edge.

[0076] In addition, this application embodiment also provides a display device, which includes the display panel described in the above embodiments.

[0077] It is understood that since the display device includes the display panel described in the above embodiments, the display device has the same beneficial effects as the display panel.

[0078] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0080] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0081] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of pixel regions; An array substrate; An anode layer disposed on one side of the array substrate, the anode layer comprising a plurality of anodes disposed corresponding to the plurality of pixel regions; A pixel definition layer disposed on the side of the array substrate provided with the anode layer and surrounding each of the pixel regions, the pixel definition layer comprising a first barrier wall disposed along a first side of the pixel region; The first barrier wall comprises a first sub-portion located on the side of the anode away from the array substrate, a projection of the first sub-portion on the array substrate is located within a projection of the anode on the array substrate, and a maximum thickness of the first sub-portion is less than or equal to 2.5 times the thickness of the anode.

2. The display panel of claim 1, wherein, The maximum thickness of the first sub-portion is greater than or equal to the thickness of the anode.

3. The display panel of claim 1 or 2, wherein, The first barrier wall further comprises a second sub-portion connected to the first sub-portion, a projection of the second sub-portion on the array substrate does not overlap with the projection of the anode on the array substrate; The thickness of the first sub-portion on the side close to the second sub-portion decreases along the direction close to the second sub-portion.

4. The display panel of claim 3, wherein, The pixel region comprises two first sides disposed oppositely and two second sides disposed oppositely, a plurality of pixel regions are arranged along a first direction and a second direction, the first direction is parallel to the first side, and the second direction is parallel to the second side; The first barrier wall between two adjacent pixel regions along the second direction comprises two first sub-portions and one second sub-portion, wherein the second sub-portion is connected between the two first sub-portions, and the two first sub-portions are respectively located on the two anodes corresponding to the two pixel regions.

5. The display panel of claim 4, wherein, The pixel definition layer further comprises a second barrier wall disposed along the second side, at least part of the second barrier wall is located on the side of the anode away from the array substrate, and the distance from the side of the second barrier wall away from the array substrate to the array substrate is greater than the distance from the side of the first barrier wall away from the array substrate to the array substrate.

6. The display panel of claim 5, wherein, The pixel definition layer further comprises a third barrier wall disposed along the second side, the third barrier wall is located between the anode and the second barrier wall; The third barrier wall is connected to the first barrier wall at the intersection of the first side and the second side, and the material of the third barrier wall is the same as that of the first barrier wall.

7. The display panel of claim 6, wherein, The maximum thickness of the third barrier wall on the side of the anode away from the array substrate is greater than or equal to the thickness of the anode and less than or equal to 2.5 times the thickness of the anode.

8. The display panel of claim 4, wherein, The display panel further comprises a light-emitting functional layer disposed on the anode layer and the pixel definition layer, the light-emitting functional layer comprises a first light-emitting pixel group, a second light-emitting pixel group and a third light-emitting pixel group arranged alternately along the first direction, the first light-emitting pixel group comprises a plurality of first light-emitting pixels arranged along the second direction, the second light-emitting pixel group comprises a plurality of second light-emitting pixels arranged along the second direction, and the third light-emitting pixel group comprises a plurality of third light-emitting pixels arranged along the second direction; The display panel further comprises a cathode layer disposed on a side of the light-emitting functional layer away from the array substrate, the cathode layer covering a side of the first barrier wall away from the array substrate.

9. The display panel of claim 1, wherein, The material of the anode comprises silver.

10. A display device, characterized by comprising: The display device comprises the display panel according to any one of claims 1 to 9.

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