Core board pin detection system
The core board pin detection system solves the problem of pin reliability that cannot be detected in existing technologies, and enables accurate detection of pin status and fault identification.
Patent Information
- Application Number
- CN202520253055.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2035-02-18
AI Technical Summary
Existing technology cannot effectively detect the pin reliability of core boards with different pin counts, resulting in defective products entering the market.
A core board pin detection system was designed, including a detection module, an expansion module, and a main control module. The detection module collects pin potentials, the expansion module controls the data transmission channel, and the main control module performs fault diagnosis.
It enables precise detection of core board pins, improves the scalability of the detection system, and can identify defects such as cold solder joints, missing solder joints, and short circuits.
Smart Images
Figure CN223756870U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of circuit test especially relates to a core board pin detection system. BACKGROUND
[0002] In the prior art, the core board is a module with MCU and other peripheral circuits, which includes multiple pins to be electrically connected with other modules. The core board has the problems of internal component virtual welding, missing welding, short circuit and reverse welding due to complex process, technical and production capacity limitations of the patch factory and other factors. The newly manufactured core board product includes defective products.
[0003] The problem of the defective core board may be internal component virtual welding, missing welding, short circuit, and reverse welding. The defects of the core board can reduce the reliability of the pins of the core board. The prior art cannot detect the pin reliability of the defective core board with different pin numbers. UTILITY MODEL CONTENT
[0004] The utility model provides a kind of core board pin detection system to solve the problem of how to detect the pin reliability of core board with different pin numbers at present.
[0005] The utility model provides a kind of core board pin detection system, comprising: detection module, expansion module and main control module;
[0006] The input end of the detection module is connected one-to-one with the pins of the core board to be tested, and the output end of the detection module is connected with the first input end of the main control module.
[0007] The detection module is used to collect the output potential of the pins of the core board to be tested.
[0008] The first end of the expansion module is connected with the output end of the main control module, and the second end of the expansion module is connected with the control end of the detection module.
[0009] The expansion module is used to turn on or turn off the data transmission channel between the input end of the detection module and the main control module.
[0010] Optionally, the detection module comprises at least one first encoder.
[0011] The first end of the first encoder is connected one-to-one with the pins of the core board to be tested, the second end of the first encoder is connected with the output end of the detection module, and the control end of the first encoder is connected with the control end of the detection module.
[0012] Optionally, the detection module further comprises at least one first encoder and an inverter.
[0013] The first end of the first encoder is connected with the pins of the core board to be tested one by one, the second end of the first encoder is connected with the first end of the inverter, and the second end of the inverter is connected with the output end of the detection module.
[0014] Optionally, the first encoder comprises a 74LS147 encoder.
[0015] Optionally, the key selection module is further included.
[0016] The output end of the key selection module is connected with the second input end of the main control module, the key selection module is used for outputting a control signal according to a key operation, and the expansion module is used for turning on or turning off a data transmission channel between the input end of the detection module and the main control module according to the control signal.
[0017] Optionally, the key selection module comprises a key group and a second encoder.
[0018] The output end of the key group is connected with the input end of the second encoder, and the output end of the second encoder is connected with the output end of the key selection module; and the key group is used for receiving a key input signal.
[0019] Optionally, the second encoder comprises a 74LS147 encoder.
[0020] Optionally, the expansion module comprises at least one buffer.
[0021] The data ends between adjacent at least one buffer are connected; wherein the input end of at least one buffer is connected with the first end of the expansion module, and the output end of the buffer is connected with the data end of the detection module.
[0022] The buffer is used for sending a data signal to the detection module to turn on or turn off the data transmission channel between the input end of the detection module and the main control module.
[0023] Optionally, the expansion module comprises at least one buffer.
[0024] The data ends between adjacent at least one buffer are connected; wherein the input end of at least one buffer is connected with the first end of the expansion module, and the output end of the buffer is connected with the power supply end of the detection module.
[0025] The buffer is used for powering on or powering off the detection module, and the buffer turns on or turns off the data transmission channel between the input end of the detection module and the main control module by powering on or powering off the detection module.
[0026] Optionally, the buffer comprises a 74HC595 buffer. BRIEF DESCRIPTION OF DRAWINGS
[0027] In order to make the technical solutions in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings described in the following are only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.
[0028] Figure 1 The structural schematic diagram of a core plate pin detection system provided by the embodiment of the present application is shown in the figure.
[0029] Figure 2 The structural schematic diagram of another core plate pin detection system provided by the embodiment of the present application is shown in the figure.
[0030] Figure 3 The structural schematic diagram of another core plate pin detection system provided by the embodiment of the present application is shown in the figure.
[0031] Figure 4 The structural schematic diagram of another core plate pin detection system provided by the embodiment of the present application is shown in the figure.
[0032] Figure 5 The structural schematic diagram of another core plate pin detection system provided by the embodiment of the present application is shown in the figure.
[0033] Figure 6 The circuit diagram of a core plate pin detection system provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION
[0034] In order to make the technical solutions in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings described in the following are only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.
[0035] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0036] Figure 1 A core board pin detection system structure diagram proposed by the embodiments of the present application is shown in FIG. 1, which comprises a detection module 102, an expansion module 103 and a main control module 101. Figure 1 The input end of the detection module 102 is connected to the pins of the core board to be tested one by one, and the output end of the detection module 102 is connected to the first input end of the main control module 101. The detection module 102 is used to collect the output potential of the pins of the core board to be tested. The first end of the expansion module 103 is connected to the output end of the main control module 101, and the second end of the expansion module 103 is connected to the control end of the detection module 102. The expansion module 103 is used to turn on or turn off the data transmission channel between the input end of the detection module 102 and the main control module 101.
[0037] Specifically, in the detection module 102, the output potential of each pin on the core board to be tested is collected. The output potential refers to the voltage level on the pin, which can reflect the state of the pin. Optionally, the state of the pin includes high potential output or low potential output of the pin.
[0038] Exemplarily, the core board pins are pulled low in order sequence. The output potentials of the core board pins in each order sequence are collected. Assuming that the core board has five pins, the core board pins are pulled low in the order of pin 1 to pin 5, and the output potentials of the core board pins are collected. When the output potentials of the core board pins are as shown in Table 1, it can be seen that the five pins of the core board output low potentials in turn in the order T1-T5, and the detection module 102 can collect the output potentials of the five pins of the core board and send them to the main control module 101. The main control module 101 can determine that the core board pin quality is good according to the core board pin potential output. When the output potentials of the core board pins are as shown in Table 2, it can be seen that in the T2 order, the core board pin 2 should theoretically output a low-level signal, but actually the output potential of the core board pin 2 is a high-level signal. The pin potential data collected by the detection module 102 is sent to the main control module 101, and the main control module 101 can determine that the core board pin 2 has a virtual welding, a missing welding or a missing welding, etc. so that the core board pin 2 cannot be pulled low according to the theoretical order. When the output potentials of the core board pins are as shown in Table 2, it can be seen that in the T1 and T2 orders, the core board pins 1 and 2 are pulled low at the same time. The pin potential data collected by the detection module 102 is sent to the main control module 101, and the main control module 101 can determine that the core board pins 1 and 2 have a short circuit or a sticking, etc. so that the core board pins 1 and 2 are pulled low at the same time.
[0039]
[0040] Table 1
[0041]
[0042]
[0043] Table 2
[0044]
[0045] Table 3
[0046] The first end of the expansion module 103 is connected with the output end of the master control module 101, and the second end of the expansion module 103 is connected with the control end of the detection module 102; the expansion module 103 is used for turning on or turning off the data transmission channel between the input end of the detection module 102 and the master control module 101. The detection module 102 of the core board pin detection system has a plurality of input ports to match the core boards with different pin numbers. The expansion module 103 is used for turning on or turning off the data transmission channel between the input end of the detection module 102 and the master control module 101, so that when the input end of the detection module 102 is connected with the pins of the core board to be detected, the data transmission channel between the input end of the detection module 102 and the master control module 101 is turned on. When the input end of the detection module 102 is not connected with the pins of the core board to be detected, the data transmission channel between the input end of the detection module 102 and the master control module 101 is turned off.
[0047] In the core board pin detection system provided in the embodiment of the utility model, the input end of the detection module is connected with the pins of the core board to be detected one by one, and the output potential of the pins of the core board to be detected is collected. The master control module detects the pin reliability of the core board to be detected according to the output potential of the pins of the core board collected by the detection module. The expansion module can turn on or turn off the data transmission channel between the input end of the detection module and the master control module. In the core board pin detection system provided in the embodiment of the utility model, the accurate detection of the state of each pin on the core board is realized. Meanwhile, the expansion module is used for turning on or turning off the data transmission channel between the input end of the detection module and the master control module, so that the expansibility of the detection module in the core board pin detection system is improved.
[0048] On the basis of the above-mentioned embodiments, Figure 2 The structure diagram of another core board pin detection system provided in the embodiment of the utility model is shown in the figure, Figure 2 As shown, the detection module 102 comprises: at least one first encoder 1021; the first end of the first encoder 1021 is connected with the pins of the core board to be detected one by one, the second end of the first encoder 1021 is connected with the output end of the detection module 102, and the control end of the first encoder is connected with the control end of the detection module.
[0049] Specifically, Figure 2 Two first encoders 1021 are shown in the figure, the first end of the first encoder 1021 is connected with the pins of the core board to be detected one by one to collect the output potential of the pins of the core board. The control end of the first encoder 1021 is connected with the expansion module 103, and the expansion module 103 controls the data transmission channel between the input end of the detection module 102 and the master control module 101 to be turned on or turned off by controlling the opening or closing of a certain first encoder 1021.
[0050] On the basis of the above-mentioned embodiments,Figure 3 The structure diagram of another core board pin detection system provided by the embodiment of the utility model is shown in the figure, Figure 3 As shown in the figure, the detection module 102 further comprises: at least one first encoder 1021 and a NOT gate 1022; the first end of the first encoder 1021 is connected to the pins of the core board to be tested one by one, the second end of the first encoder 1021 is connected to the first end of the NOT gate 1022, and the second end of the NOT gate 1022 is connected to the output end of the detection module 102. The first encoder 1021 comprises: a 74LS147 encoder.
[0051] Specifically, the 74LS147 encoder adopts a 16-pin package and is a 10-wire-4-wire 8421 BCD code priority encoder. The 74LS147 encoder has 9 input ends and 4 output ends. When a certain input end is 0, it represents that a certain decimal number is input. When the 9 input ends are all 1, it represents that the input is the decimal number 0. The 4 output ends reflect the BCD code output of the input decimal number. The input end and the output end of the 74LS147 priority encoder are both low-level effective, that is, when a certain input end is low-level 0, the 4 output ends output the corresponding 8421 BCD code with low-level 0. When the 9 inputs are all 1, the 4 outputs are also all 1, representing the 8421 BCD code output of the input decimal number 0.
[0052] Table 4 below is the input-output truth table of the 74LS147 encoder. When the first encoder 1021 is a 74LS147 encoder, and the second end of the first encoder 1021 is connected to the first end of the NOT gate 1022, and the second end of the NOT gate 1022 is connected to the output end of the detection module 102, the host control module 101 can determine which pin of the core board to be tested is pulled low according to the decimal value of the received data. For example, as shown in Table 4 below, when the pin 5 of the core board to be tested is pulled low, the corresponding input value of the first encoder 1021 is: X, X, X, X, 0, 1, 1, 1, 1; the corresponding output of the first encoder 1021 is 1, 0, 1, 0. After being inverted by the NOT gate 1022, the data received by the host control module 101 is 0, 1, 0, 1; converting 0, 1, 0, 1 into a decimal number is 5, which corresponds to the current pin order of the core board that is pulled low, so that it can be determined which pin of the core board to be tested is pulled low.
[0053]
[0054] Table 4
[0055] On the basis of the above embodiments, Figure 4 The structure diagram of another core board pin detection system provided by the embodiment of the utility model is shown in the figure, Figure 4As shown, the core board pin detection system also includes: a key selection module 104; the output terminal of the key selection module 104 is connected to the second input terminal of the main control module 101, the key selection module 104 is used to output control signals according to key operation, and the expansion module 103 is used to turn on or off the data transmission channel between the input terminal of the detection module 102 and the main control module 101 according to the control signal.
[0056] The key selection module 104 includes: a key group 1042 and a second encoder 1041; the output terminal of the key group 1042 is connected to the input terminal of the second encoder 1041, and the output terminal of the second encoder 1041 is connected to the output terminal of the key selection module 104; the key group 1042 is used to receive key input signals.
[0057] The second encoder 1041 includes: a 74LS147 encoder.
[0058] Specifically, such as Figure 4 As shown, in the key selection module 104, the second encoder 1041 encodes the key input signal input by the key group 1042 and sends it to the main control module 101. The expansion module 103 turns on or off the data transmission channel between the input terminal of the detection module 102 and the main control module 101 according to the control signal.
[0059] Based on the above embodiments, Figure 5 This is a schematic diagram of another core board pin detection system provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the expansion module 103 includes: at least one buffer 1031; a data terminal connection between adjacent buffers 1031; wherein the input terminal of at least one buffer 1031 is connected to the first terminal of the expansion module 103, and the output terminal of the buffer 1031 is connected to the data terminal of the detection module 102; the buffer 1031 is used to send data signals to the detection module 102 to turn on or off the data transmission channel between the input terminal of the detection module 102 and the main control module 101.
[0060] The expansion module 103 includes: at least one buffer 1031; a data terminal connection between adjacent buffers 1031; wherein the input terminal of at least one buffer 1031 is connected to a first terminal of the expansion module 103, and the output terminal of the buffer 1031 is connected to the power supply terminal of the detection module 102; the buffer 1031 is used to power on or power off the detection module 102, and the buffer 1031 connects or disconnects the data transmission channel between the input terminal of the detection module 102 and the main control module 101 by powering on or powering off the detection module 102. The buffer 1031 includes a 74HC595 buffer.
[0061] Specifically, in the expansion module 103, at least one buffer 1031 is included. The buffer 1031 turns on or turns off the data transmission channel between the input end of the detection module 102 and the main control module 101. Among them, the buffer 1031 sends a data signal to the detection module 102 to turn on or turn off the data transmission channel between the input end of the detection module 102 and the main control module 101, or by powering on or powering off the detection module 102 to turn on or turn off the data transmission channel between the input end of the detection module 102 and the main control module 101.
[0062] 74HC595 buffer is an 8-bit serial input, parallel output shift register, with tri-state output function. When more devices need to be controlled, multiple 74HC595 can be cascaded to achieve, so that a clock signal can be used to control the data shift and output of multiple 74HC595. In the embodiment of the utility model, at least one 74HC595 buffer is cascaded to power on or power off the detection module 102 to turn on or turn off the data transmission channel between the input end of the detection module 102 and the main control module 101.
[0063] On the basis of the above embodiments, Figure 6 The circuit diagram of the core board pin detection system provided by the embodiment of the utility model is shown in Figure 6 The detection module 102 is two 74LS147 encoders U2, and the input pins of the 74LS147 encoders U2 are connected one by one with the pins of the two core boards U0 to collect the pin potential of the core board U0. The value obtained after the output end of the 74LS147 encoder U2 is inverted by the inverter can determine the pin name pulled down by the core board U0.
[0064] For example, when the 9 pins of the core board U0 are pulled down in turn, and the data received by the main control chip U1 is as shown in the following table 5, it indicates that the 9 pins of the core board U0 are normal. The data value received by the main control chip U1 is converted into decimal as the number 1, 2, 3, 4, 5, 6, 7, 8, 9.
[0065]
[0066]
[0067] Table 5
[0068] When the data received by the master chip U1 is as shown in Table 6 below, it can be seen from the second last row that when pin 2 of the core board U0 is pulled low, the pin potential theoretical output value X, 0, 1, 1, 1, 1, 1, 1, 1, the data value received by the master chip U1 in theory should be 0010. However, as shown in the table below, the data value received by the master chip U1 is 0000. Therefore, looking up the input and output truth table of the 74LS147 encoder of Table 4, it can be seen that the input value of the first encoder 1021 is 1, 1, 1, 1, 1, 1, 1, 1, 1, that is, the output pin 2 of the core board U0 is not normally pulled low. The data value received by the master chip U1 is converted to decimal, in turn, 1, 0, 3, 4, 5, 6, 7, 8, 9, it can be seen that the pin 2 of the core board U0 is faulty, and according to the input value of the first encoder 1021, 1, 1, 1, 1, 1, 1, 1, 1, 1, it can be judged that the fault of the pin 2 of the core board U0 is virtual welding, missing welding or missing welding.
[0069]
[0070]
[0071] Table 6
[0072] When the data received by the master chip U1 is as shown in Table 7 below, as shown in the table below, when pin 2 of the core board U0 is pulled low, the data value received by the master chip U1 is 0011. Looking up the input and output truth table of the 74LS147 encoder of Table 4, it can be seen that the input value of the first encoder 1021 is X, X, 0, 1, 1, 1, 1, 1, 1, that is, the output pin 3 of the core board U0 is pulled low. The data value received by the master chip U1 is converted to decimal, in turn, 1, 3, 3, 4, 5, 6, 7, 8, 9, it can be seen that the pin 2 of the core board U0 is faulty. At the same time, according to the input value of the first encoder 1021, X, X, 0, 1, 1, 1, 1, 1, 1, it can be judged that when pin 2 is pulled low, pin 3 is pulled low instead, so it can be judged that pin 2 and pin 3 of the core board U0 are shorted or stuck.
[0073]
[0074]
[0075] Table 7
[0076] In the expansion module 103, two 74HC59 buffers U3 are included, and the 8 parallel outputs of the 74HC59 buffers U3 are connected with the power supply VCC end of two 74LS147 encoders U2, respectively controlling the power-on of the two 74LS147 encoders U2 to turn on or turn off the data transmission channel between the input end of the detection module 102 and the main control module 101. The serial output end and the serial data input end between the two 74HC59 buffers U3 are connected to realize cascading. Figure 6 In the provided embodiment, the control of 16 74LS147 encoders U2 can be realized. The expandability of the detection module in the core board pin detection system is improved.
[0077] In the key selection module 104, a 74LS147 encoder U2 and a key group are included. By pressing the key group, the corresponding pin of the 74LS147 encoder U2 in the key selection module 104 is pulled low to change the input value of the 74LS147 encoder U2, so as to send a corresponding data signal to the main control chip 101. The expansion module 103 turns on or turns off the data transmission channel between the input end of the detection module and the main control module according to the input signal of the key selection module 104.
[0078] In the core board pin detection system provided in the embodiment of the utility model, the encoder 74LS147 is used as the encoder of the detection module to collect the potential information of the core board, and the main control module can judge the fault position and the fault type of the core board pin according to the received potential information. In the expansion module, the buffer 74HC595 is used to control the power-on or power-off of the encoder of the detection module, so as to turn on or turn off the data transmission channel between the input end of the detection module and the main control module, and the expandability of the detection module in the core board pin detection system is improved.
[0079] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the utility model can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the utility model can be achieved, which is not limited herein.
[0080] The above specific embodiments do not constitute a limitation on the protection scope of the utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principles of the utility model should be included in the protection scope of the utility model.
Claims
1. A core board pin detection system, characterized by, The application relates to a detection module, an expansion module and a main control module. The input end of the detection module is connected with the pins of a core board to be detected in one-to-one correspondence, and the output end of the detection module is connected with the first input end of the main control module. The detection module is used for collecting the output potential of the pins of the core board to be detected. The first end of the expansion module is connected with the output end of the main control module, and the second end of the expansion module is connected with the control end of the detection module. The expansion module is used for turning on or turning off the data transmission channel between the input end of the detection module and the main control module. The detection module comprises at least one first encoder.
2. The core board pin detection system of claim 1, wherein, The first end of the first encoder is connected with the pins of the core board to be detected in one-to-one correspondence, the second end of the first encoder is connected with the output end of the detection module, and the control end of the first encoder is connected with the control end of the detection module. The detection module further comprises at least one first encoder and a NOT gate.
3. The core board pin detection system of claim 1, wherein, The first end of the first encoder is connected with the pins of the core board to be detected in one-to-one correspondence, the second end of the first encoder is connected with the first end of the NOT gate, and the second end of the NOT gate is connected with the output end of the detection module. The first encoder comprises a 74LS147 encoder.
4. The core board pin detection system of claim 3, wherein, The application further relates to a key selection module.
5. The core board pin detection system of claim 1, wherein, The output end of the key selection module is connected with the second input end of the main control module, and the key selection module is used for outputting a control signal according to a key operation. The expansion module is used for turning on or turning off the data transmission channel between the input end of the detection module and the main control module according to the control signal. The key selection module comprises a key group and a second encoder. The output end of the key group is connected with the input end of the second encoder, the output end of the second encoder is connected with the output end of the key selection module, and the key group is used for receiving a key input signal.
6. The coreboard pin detection system of claim 5, wherein, The second encoder comprises a 74LS147 encoder. The expansion module comprises at least one buffer.
7. The coreboard pin detection system of claim 6, wherein, The data ends of adjacent at least one buffer are connected, the input end of at least one buffer is connected with the first end of the expansion module, and the output end of the buffer is connected with the data end of the detection module.
8. The core board pin detection system of claim 1, wherein, The buffer is used for sending a data signal to the detection module to turn on or turn off the data transmission channel between the input end of the detection module and the main control module. The expansion module comprises at least one buffer. The data ends of adjacent at least one buffer are connected, the input end of at least one buffer is connected with the first end of the expansion module, and the output end of the buffer is connected with the power supply end of the detection module.
9. The coreboard pin detection system of claim 1, wherein, The buffer is used for powering on or powering off the detection module, and the buffer turns on or turns off the data transmission channel between the input end of the detection module and the main control module by powering on or powering off the detection module. The buffer comprises a 74HC595 buffer. 10. The core board pin detection system of claim 8, wherein,