Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a substrate as well as a shading layer, a semiconductor layer, a gate layer, a first source-drain electrode layer and a second source-drain electrode layer which are arranged on the substrate, the shading layer comprises a first polar plate, the first source-drain electrode layer comprises a second polar plate arranged opposite to the first polar plate, the second source-drain electrode layer comprises a third polar plate arranged opposite to the second polar plate, and the third polar plate is arranged on the substrate. The semiconductor layer or the grid layer further comprises a fourth polar plate, and the first polar plate, the second polar plate, the third polar plate and the fourth polar plate form a storage capacitor of the display panel; according to the display panel, the three layers of capacitance plates are prepared from the materials of the shading layer, the first source-drain electrode layer and the second source-drain electrode layer in the display panel, the capacitance plate is prepared from the material of one of the semiconductor layer and the grid electrode layer, a conductive layer does not need to be additionally arranged for preparing the capacitance plate, the structure of a storage capacitor is simplified, and the preparation cost of the display panel is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, and in particular to a display panel and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) is a new type of current-type semiconductor light-emitting device, which is used for controlling carriers and exciting organic materials to emit light for display.

[0003] The storage capacitor of the current OLED display panel usually separately sets a conductive layer as a capacitor plate of a capacitor structure, and forms the capacitor structure with the light shielding layer and the semiconductor layer of the bottom layer. The capacitor structure is relatively complex, the process is more, and the preparation cost of the product is increased. UTILITY MODEL CONTENT

[0004] The present application provides a display panel and a display device to solve the technical problem of the complex capacitor structure of the existing OLED display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] The present application provides a display panel, which comprises:

[0007] a substrate substrate;

[0008] a light shielding layer arranged on one side of the substrate substrate, the light shielding layer comprising a first plate;

[0009] a semiconductor layer arranged on a side of the light shielding layer away from the substrate substrate;

[0010] a gate layer arranged on a side of the semiconductor layer away from the substrate substrate;

[0011] a first source-drain layer arranged on a side of the gate layer away from the substrate substrate, the first source-drain layer comprising a second plate arranged opposite to the first plate;

[0012] a second source-drain layer arranged on a side of the first source-drain layer away from the substrate substrate, the second source-drain layer comprising a third plate arranged opposite to the second plate;

[0013] a pixel layer comprising a first pixel definition layer and a second pixel definition layer, the first pixel definition layer being arranged on a side of the second source-drain layer away from the substrate substrate, and the second pixel definition layer being arranged on a surface of the first pixel definition layer away from the substrate substrate;

[0014] The semiconductor layer or the gate layer further comprises a fourth plate, the fourth plate is arranged between the first plate and the second plate, and the first plate, the second plate, the third plate and the fourth plate constitute a storage capacitor of the display panel.

[0015] Optionally, the display panel comprises a display area and a non-display area, at least one first transistor is arranged in the display area, and at least one second transistor is arranged in the non-display area.

[0016] The semiconductor layer comprises a first active part of the first transistor and a second active part of the second transistor, and the mobility of the first active part is less than or equal to the mobility of the second active part.

[0017] Optionally, the display panel further comprises:

[0018] A buffer layer is arranged between the semiconductor layer and the light shielding layer.

[0019] The surface of the first active part and the second active part away from the gate layer side is in contact with the buffer layer, and the mobility of the first active part is equal to the mobility of the second active part.

[0020] Optionally, the display panel further comprises:

[0021] A buffer layer is arranged between the semiconductor layer and the light shielding layer.

[0022] A protective layer comprises a first part located in the display area and a second part located in the non-display area, the first part is arranged on the surface of the first active part away from the light shielding layer side, and the second part is arranged between the second active part and the buffer layer.

[0023] The mobility of the first active part is less than the mobility of the second active part.

[0024] Optionally, the semiconductor layer comprises the fourth plate, and the fourth plate is in contact with the surface of the buffer layer away from the light shielding layer side.

[0025] Optionally, the protective layer further comprises a third part arranged between the buffer layer and the fourth plate.

[0026] The gate layer comprises the fourth plate, and the fourth plate is arranged on the side of the third part away from the light shielding layer.

[0027] Optionally, the semiconductor layer further comprises a third active part arranged between the third part and the buffer layer, and the mobility of the third active part is the same as the mobility of the first active part.

[0028] The third active part is in contact with the buffer layer on one side, and in contact with the third part on the other side.

[0029] Optionally, the display panel further comprises:

[0030] A passivation layer is arranged between the first source-drain layer and the second source-drain layer, and the passivation layer covers the first source-drain layer.

[0031] A first planar layer is arranged on the side of the passivation layer away from the substrate, and part of the second source-drain is in contact with the surface of the side of the first planar layer away from the substrate.

[0032] The first planar layer is provided with a first opening, and the third plate is arranged in the first opening.

[0033] Optionally, the display panel further comprises:

[0034] A first planar layer is arranged between the first source-drain layer and the second source-drain layer.

[0035] A second planar layer is arranged on the side of the first planar layer away from the substrate.

[0036] The photosensitivity of the second planar layer is greater than or equal to the photosensitivity of the first planar layer.

[0037] Optionally, the display panel further comprises:

[0038] An anode layer is arranged on the side of the second source-drain layer away from the substrate, and the anode layer comprises a fifth plate arranged opposite to the third plate, and the first plate, the second plate, the third plate, the fourth plate and the fifth plate constitute a storage capacitor of the display panel.

[0039] The application further provides a display device comprising the display panel.

[0040] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0042] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0043] Figure 1 A simplified structural diagram of the display panel provided in the embodiments of this application;

[0044] Figure 2 for Figure 1 The first structural diagram of the mid-section MM;

[0045] Figure 3 for Figure 1 The second structural diagram of the mid-section MM;

[0046] Figure 4 for Figure 1 The third structural diagram of the mid-section MM;

[0047] Figure 5 for Figure 1 The fourth structural diagram of the mid-section MM;

[0048] Figure 6 for Figure 1 The fifth structural diagram of the mid-section MM. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0050] Please see Figures 1 to 6 This application proposes a display panel 100, which includes a substrate 10 and a light-shielding layer LS, a semiconductor layer AS, a gate layer GE, a first source-drain layer SD1, and a second source-drain layer SD2 disposed on the substrate 10. The light-shielding layer LS is disposed on one side of the substrate 10, the gate layer GE is disposed on the side of the semiconductor layer AS away from the substrate 10, the semiconductor layer AS is disposed on the side of the light-shielding layer LS away from the substrate 10, the first source-drain layer SD1 is disposed on the side of the gate layer GE away from the substrate 10, and the second source-drain layer SD2 is disposed on the side of the first source-drain layer SD1 away from the substrate 10.

[0051] In the embodiment, the light shielding layer LS includes a first plate C1, the first source-drain layer SD1 includes a second plate C2 disposed opposite to the first plate C1, and the second source-drain layer SD2 includes a third plate C3 disposed opposite to the second plate C2.

[0052] In the embodiment, the semiconductor layer AS or the gate electrode layer GE further includes a fourth plate C4 disposed between the first plate C1 and the second plate C2, and the first plate C1, the second plate C2, the third plate C3 and the fourth plate C4 constitute a storage capacitor Cst of the display panel 100.

[0053] The application utilizes the materials of the light shielding layer LS, the first source-drain layer SD1 and the second source-drain layer SD2 in the display panel 100 to prepare three layers of capacitor plates, and utilizes the material of one of the semiconductor layer AS or the gate electrode layer GE to prepare one layer of capacitor plate, without the need of additionally disposing a conductive layer to prepare a capacitor plate, thereby simplifying the structure of the storage capacitor Cst and reducing the manufacturing cost of the display panel 100.

[0054] The technical solutions of the application will be described in detail in combination with specific embodiments.

[0055] Please refer to Figure 1 , the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and a plurality of sub-pixels PX for displaying are disposed in the display area AA. The non-display area NA can be a frame area of the display panel 100, and functional components for assisting the sub-pixels PX in the display area AA to display can be disposed in the non-display area NA.

[0056] Please refer to Figure 1 , a binding terminal PD can be disposed at the lower side of the display area AA, and the binding terminal PD can be connected with an external circuit. The binding terminal PD transmits signals input by the external circuit to the data wire, so as to drive the display panel 100 to display a picture. For example, the binding terminal PD can be connected with a chip or a chip on film, and is used to provide power supply and driving signals for the display panel 100.

[0057] Please refer to Figures 2 to 6 , the display panel 100 can include a substrate 10, an array layer 20 disposed on the substrate 10, a pixel layer 30 disposed on the array layer 20, a light-emitting functional layer 40 and an encapsulation layer 50.

[0058] In this embodiment, the substrate 10 can be made of materials such as glass, quartz, or polyimide; for example, when the display panel 100 is a flexible panel, the substrate 10 can be made of flexible materials such as polyimide, or can be composed of a laminate of flexible materials and inorganic materials; when the display panel 100 is a rigid panel, the substrate 10 can be made of rigid materials such as glass or quartz.

[0059] Please see Figures 2 to 6 The array layer 20 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., depending on the position of the gate and the semiconductor layer AS. There are no specific restrictions.

[0060] In this embodiment, at least one first transistor T1 is disposed in the display area AA, and at least one second transistor T2 is disposed in the non-display area NA; at the same time, a pixel driving circuit and a storage capacitor Cst are disposed in the display area AA, the pixel driving circuit includes the first transistor T1, and a gate driving circuit is disposed in the non-display area NA, the gate driving circuit including the second transistor T2.

[0061] It should be noted that, in order to simplify the manufacturing process, the first transistor T1 and the second transistor T2 in the display area AA and the non-display area NA can be fabricated simultaneously.

[0062] For example, please see Figures 2 to 6 The thin-film transistor shown can be a top-gate thin-film transistor. The array layer 20 can include a light-shielding layer LS disposed on the substrate 10, a buffer layer 201 disposed on the light-shielding layer LS, a semiconductor layer AS disposed on the buffer layer 201, a first gate insulating layer 202 disposed on the semiconductor layer AS, a gate layer GE disposed on the first gate insulating layer 202, an inter-insulating layer 203 disposed on the gate layer GE, a first source-drain layer SD1 disposed on the inter-insulating layer 203, a passivation layer 204 disposed on the first source-drain layer SD1, a first planarization layer 205 disposed on the passivation layer 204, a second source-drain layer SD2 disposed on the first planarization layer 205, and a second planarization layer 206 disposed on the second source-drain layer SD2.

[0063] It should be noted that the number of source and drain layers can be set according to the wiring space requirements. For example, the source and drain layers in this application can be two layers. At the same time, the number of gate layers GE can be set according to the wiring space and capacitance requirements. For example, the gate layer GE in this application is one layer.

[0064] It should be noted that the buffer layer 201, the first gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 can all be inorganic materials composed of elements such as nitrogen, silicon, oxygen, aluminum, etc., such as a single layer or a plurality of stacked inorganic film layers composed of one of silicon nitride, silicon oxide, and aluminum oxide.

[0065] It should be noted that the flat layer of the present application is provided to ensure the flatness of the film layer, and the number of flat layers is set according to the requirement of the flatness of the film layer, for example, the flat layer of the present application can be two layers.

[0066] Please refer to Figures 2 to 6 The pixel layer 30 can include a first pixel definition layer 310 and a second pixel definition layer 320, the first pixel definition layer 310 is arranged on the side of the second flat layer 206 away from the substrate 10, and the second pixel definition layer 320 is arranged on the surface of the first pixel definition layer 310 away from the substrate 10.

[0067] It should be noted that since the light-emitting layer 402 of the present application is prepared by an inkjet printing process, in order to reduce the precision of inkjet printing, the first pixel definition layer 310 of the present application can include a plurality of first shielding strips staggered horizontally and vertically, the horizontally and vertically staggered first shielding strips enclose a plurality of pixel openings corresponding to the sub-pixels, and the second pixel definition layer 320 includes a plurality of second shielding strips in the horizontal or vertical direction, the colors of the plurality of sub-pixels between any two adjacent second shielding strips are the same, so that in the inkjet printing process, the plurality of sub-pixels between any two adjacent second shielding strips can be printed simultaneously along the arrangement direction of the second shielding strips, thereby reducing the precision of inkjet printing and improving the process efficiency.

[0068] It should be noted that the first pixel definition layer 310 and the second pixel definition layer 320 of the present application can be formed in one process, i.e., the film layers of the first pixel definition layer 310 and the second pixel definition layer 320 are formed at the same time, and the first pixel definition layer 310 and the second pixel definition layer 320 are patterned in the same mask, so that the first pixel definition layer 310 forms a plurality of first shielding strips, and the second pixel definition layer 320 forms a plurality of second shielding strips, for example, the present application can include a plurality of first shielding strips extending in the second direction and arranged in the first direction, and a plurality of second shielding strips extending in the first direction and arranged in the second direction.

[0069] In the present embodiment, since the second shielding strip mainly serves to isolate sub-pixels of different colors, the thickness of the second shielding strip of the present application can be greater than the thickness of the first shielding strip.

[0070] It should be noted that the display panel 100 further comprises a support layer (not shown) provided integrally with the pixel layer 30, the support layer is provided on the surface of the second pixel definition layer 320 away from the first pixel definition layer 310, and the support layer and the pixel layer 30 can be formed in the same mask process, and the support layer can be used to carry a mask plate.

[0071] It should be noted that the materials of the pixel layer 30 and the support layer can be organic positive photoresist.

[0072] Please refer to Figures 2 to 6 The light-emitting functional layer 40 can include an anode layer 401 provided on the second planar layer, a light-emitting layer 402 provided on the anode layer 401, and a cathode layer 403 provided on the light-emitting layer 402. The anode layer 401 includes a plurality of anodes corresponding to the pixel openings one by one, and the light-emitting layer 402 can include a plurality of light-emitting pixels corresponding to the plurality of anodes one by one.

[0073] Please refer to Figures 2 to 6 The encapsulation layer 50 covers the pixel layer 30 and continuously covers the plurality of pixel openings and the plurality of light-emitting pixels; the encapsulation layer 50 can include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer which are sequentially stacked.

[0074] In the embodiment, the display panel can further include a color filter layer (not shown) provided on the encapsulation layer 50 and a cover layer (not shown) provided on the color filter layer, the color filter layer includes a plurality of color resist and a light shielding unit provided on both sides of the color resist, and one color resist corresponds to one light-emitting pixel; the cover layer is provided on the side of the color filter layer away from the substrate 10, and the cover layer can be a glass cover or a film formed directly on the color filter layer.

[0075] The structure of the array layer 20 in the present application Figure 2 will be described in detail below.

[0076] Please refer to Figure 2 The material of the light shielding layer LS can include Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the light shielding layer LS can be a laminated structure composed of a MoTi layer and a Cu layer.

[0077] In the embodiment, since the device effect of the transistor drifts under the action of light, the light shielding layer LS can be provided between the transistor and the substrate 10 to shield the active part in the transistor; the light shielding structure is provided in the non-display area NA, and external light cannot enter the area where the gate drive circuit is located, so the light shielding layer LS can be located in the display area AA, and the light shielding layer LS does not need to be provided in the non-display area NA.

[0078] Please refer toFigure 2 In the patterning process of the light shielding layer LS, the light shielding layer LS can be formed with a light shielding portion LS1 corresponding to the first transistor T1 and a first plate C1 of the storage capacitor Cst.

[0079] Referring to Figure 2 The buffer layer 201 covers the light shielding layer LS, and the material of the buffer layer 201 can be silicon nitride or silicon oxide, or a laminated structure of the two.

[0080] Referring to Figure 2 The semiconductor layer AS is disposed on the side of the buffer layer 201 away from the substrate 10, and the material of the semiconductor layer AS can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides. Figure 2 The material of the semiconductor layer AS in the above embodiment can be IGZO.

[0081] In the above embodiment, the semiconductor layer AS includes a first active portion AS1 of the first transistor T1 and a second active portion AS2 of the second transistor T2, and the materials of the first active portion AS1 and the second active portion AS2 can be the same, i.e., the mobility of the first active portion AS1 can be equal to the mobility of the second active portion AS2.

[0082] In the above embodiment, the surfaces of the first active portion AS1 and the second active portion AS2 away from the gate electrode layer GE are both in contact with the buffer layer 201.

[0083] In the above embodiment, the semiconductor layer AS can further include a fourth plate C4 corresponding to the first plate C1, the fourth plate C4 is in contact with the surface of the buffer layer 201 away from the light shielding layer LS, and the fourth plate C4 is disposed opposite to the first plate C1, and the second plate C2 is a capacitor plate of the storage capacitor Cst.

[0084] Referring to Figure 2 The first gate insulating layer 202 includes a first sub-portion 202a and a second sub-portion 202b, the first sub-portion 202a is disposed on the side of the first active portion AS1 away from the substrate 10, the second sub-portion 202b is disposed on the side of the second active portion AS2 away from the substrate 10, and the first gate insulating layer 202 is used to isolate the semiconductor layer AS from the upper conductive layer.

[0085] Referring to Figure 2The gate layer GE includes a first gate GE1 of the first transistor T1 and a second gate GE2 of the second transistor T2, the first gate GE1 is arranged on the side of the first sub-part 202a away from the substrate 10, and the second gate GE2 is arranged on the side of the second sub-part 202b away from the substrate 10.

[0086] In the embodiment, the material of the gate layer GE can include Cr, W, Ti, Ta, Mo, Al, Cu or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the first electrode layer 120 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0087] In the embodiment, the thickness of the gate layer GE can be 100-200 nm.

[0088] Referring to Figure 2 The interlayer insulating layer 203 is arranged on the side of the gate layer GE away from the substrate 10, the interlayer insulating layer 203 is entirely laid, and the interlayer insulating layer 203 covers the gate insulating layer and contacts the buffer layer 201.

[0089] Referring to Figure 2 The first source-drain layer SD1 includes a first source T1S and a first drain T1D of the first transistor T1, and a second source T2S and a second drain T2D of the second transistor T2, the first source T1S is connected through the first via hole HL1 and one end of the first active part AS1, the first drain T1D is connected through the second via hole HL2 and the other end of the first active part AS1, the second source T2S is connected through the third via hole HL3 and one end of the second active part AS2, and the second drain T2D is connected through the fourth via hole HL4 and the other end of the second active part AS2.

[0090] In the embodiment, the first source T1S is also electrically connected through the fifth via hole HL5 and the light shielding part LS1, so that the light shielding part LS1 is multiplexed as the bottom gate of the first transistor T1, and the turn-on rate of the first transistor T1 is improved.

[0091] In the embodiment, the first source-drain layer SD1 further includes a second plate C2 of the storage capacitor Cst, the second plate C2 is connected with the first plate C1 through the sixth via hole HL6, and the second plate C2 is arranged opposite to the fourth plate C4.

[0092] In the embodiment, the material of the first source-drain layer SD1 can include Cr, W, Ti, Ta, Mo, Al, Cu or the like metal or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a MoTi layer and a Cu layer, the thickness of the MoTi layer can be 10-30 nm, and the thickness of the Cu layer can be 400-600 nm.

[0093] Referring to Figure 2 The passivation layer 204 is arranged on the side of the first source-drain layer SD1 away from the substrate 10, the passivation layer 204 is fully laid, and the passivation layer 204 covers the first source-drain layer SD1 and is in contact with the interlayer insulation layer 203.

[0094] Referring to Figure 2 The first planarization layer 205 is arranged on the side of the passivation layer 204 away from the substrate 10, the first planarization layer 205 covers part of the passivation layer 204, and the first planarization layer 205 is provided with a first opening 205a.

[0095] In the embodiment, since the thickness of the first source-drain layer SD1 is relatively thick, there is a large step difference between the region where the first source-drain layer SD1 is arranged and the region where the first source-drain layer SD1 is not arranged, and the passivation layer 204 is an inorganic material with poor leveling property, so the flatness of the surface of the passivation layer 204 away from the substrate 10 is poor; and the material of the first planarization layer 205 can be an organic material with good leveling property, such as polyimide, thereby improving the flatness of the surface of the film layer.

[0096] Referring to Figure 2 The second source-drain layer SD2 includes a connection electrode CT located in the display area AA and a bus BS located in the non-display area NA, the connection electrode CT is connected with the first source electrode T1S through the seventh via hole HL7, and the bus BS can be connected with the second gate electrode GE2, the second source electrode T2S or the second drain electrode T2D in the second transistor T2 through the eighth via hole HL8.

[0097] In the embodiment, the bus BS can include a high-potential line, a low-potential line, a data line, a clock signal line and the like signal line; by arranging the bus BS on the side of the second transistor T2 away from the substrate 10, the application reduces the frame space of the bus BS occupying the display panel 100, and realizes a narrow frame design.

[0098] In the embodiment, the second source-drain layer SD2 can further include a third plate C3 of the storage capacitor Cst, the third plate C3 can be located in the first opening 205a, i.e., part of the second source-drain layer SD2 contacts the surface of the first planar layer 205 away from the substrate 10, and the third plate C3 can be connected with the fourth plate C4 through a ninth via hole HL9, and the third plate C3 is arranged opposite to the second plate C2.

[0099] In the embodiment, the depth of the first opening 205a can be less than or equal to the thickness of the first planar layer 205, for example, the depth of the first opening 205a is equal to the thickness of the first planar layer 205, the third plate C3 contacts the passivation layer 204 in the first opening 205a, and the arrangement of the first opening 205a reduces the distance between the second plate C2 and the third plate C3, and improves the capacitance of the storage capacitor Cst.

[0100] In the embodiment, the material of the first source-drain layer SD1 can include Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the first source-drain layer SD1 can be a laminated structure composed of a Ti layer, an Al layer and a Ti layer, the thickness of the Ti layer can be 40-60 nm, and the thickness of the Al layer can be 400-600 nm.

[0101] Referring to Figure 2 , the second planar layer 206 is arranged on the side of the second source-drain layer SD2 away from the substrate 10, and the material of the second planar layer 206 can be the same as that of the first planar layer 205, for example, the second planar layer 206 and the first planar layer 205 can both be made of a material with good flow flatness such as polyimide.

[0102] In the embodiment, the material of the second planar layer 206 can be different from that of the first planar layer 205, for example, the photosensitivity of the second planar layer 206 can be greater than that of the first planar layer 205, i.e., the photosensitivity of the second planar layer 206 is stronger, and the exposure process time can be reduced and the exposure process efficiency can be improved when the second planar layer 206 is exposed.

[0103] Referring to Figure 2 , the anode layer 401 is arranged on the side of the second planar layer 206 away from the substrate 10, and the anode layer 401 is connected with the connecting electrode CT through a tenth via hole HL10. The material of the anode layer 401 can include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0104] Please see Figure 3 The bonding terminal PD may include a first terminal PD1 and a second terminal PD2. The first terminal PD1 may be fabricated in the patterning process of the first source-drain layer SD1, and the second terminal PD2 may be fabricated in the patterning process of the second source-drain layer SD2. The second terminal PD2 is electrically connected to the first terminal PD1 through the eleventh via HL11.

[0105] exist Figure 3 In this application, four capacitor plates are fabricated using the materials of the light-shielding layer LS, the semiconductor layer AS, the first source-drain layer SD1, and the second source-drain layer SD2 in the display panel 100. This eliminates the need for an additional conductive layer to fabricate the capacitor plates, simplifying the structure of the storage capacitor Cst and reducing the fabrication cost of the display panel 100. At the same time, the parallel capacitor formed by the four capacitor plates increases the capacitance of the storage capacitor Cst.

[0106] Please see Figure 1 , Figure 3 For this application Figure 2 The second structural diagram of the mid-section MM. Figure 3 medium structure and Figure 3 The structures in the two are the same or similar, but the differences are:

[0107] Please see Figure 3 The material of the first active part AS1 is different from the material of the second active part AS2, and the mobility of the first active part AS1 is less than the mobility of the second active part AS2.

[0108] In this embodiment, the trend of narrow bezel design for the display panel 100 reduces the bezel size of the display panel 100. This requires increasing the driving current capability of the gate driving circuit to reduce the size of the driving circuit. This application increases the mobility of the second active part AS2 in the second transistor T2, thereby increasing the driving current capability of the transistor in the gate driving circuit and reducing the bezel size of the non-display area NA. This achieves a narrow bezel design while ensuring the driving stability of the non-display area NA.

[0109] In this embodiment, the material of the first active part AS1 can be IGZO, and the material of the second active part AS2 can be IGZTO, IZO (InZnO), or InIZO.

[0110] In this embodiment, in order to differentiate the mobility of the first active part AS1 and the second active part AS2, the first active part AS1 and the second active part AS2 need to be fabricated in two photomask processes. In order to prevent the influence of the later process on the active part in the earlier process, this application can provide a protective layer 207 between the two processes.

[0111] Referring to Figure 4 , the protective layer 207 can include a first portion 207a located at the display area AA and a second portion 207b located at the non-display area, the first portion 207a is arranged on the surface of the first active section AS1 away from the light shielding layer LS, and the second portion 207b is arranged between the second active section AS2 and the buffer layer 201.

[0112] In the embodiment, the protective layer 207 can be laid in an integral layer, or only the second portion 207b can be arranged. Figure 4 The structure shown in the figure; at the same time, the material of the protective layer 207 can be the same as that of the first gate insulating layer 202.

[0113] The application improves the driving current capacity of the transistor in the gate drive circuit by making the mobility of the second active section AS2 greater than that of the first active section AS1, reduces the frame size of the non-display area NA, and realizes the narrow frame design; at the same time, the protective layer 207 can protect the first active section AS1, avoiding the influence of the process of the second active section AS2 on the first active section AS1.

[0114] Referring to Figure 1 , Figure 4 for the application Figure 3 The third structure diagram of the cross section MM, Figure 4 The structure is the same as or similar to that in Figure 2 , except that:

[0115] Referring to Figure 3 , the gate electrode layer GE includes the fourth plate C4, and the fourth plate C4 is arranged on the side of the third portion 207c away from the light shielding layer LS.

[0116] At the same time, the protective layer 207 can also include a third portion 207c arranged between the buffer layer 201 and the fourth plate C4, and the first gate insulating layer 202 includes a third sub-section 202c arranged between the third portion 207c and the fourth plate C4, that is, the first plate C1 and the fourth plate C4 are spaced apart by the buffer layer 201, the third portion 207c and the third sub-section 202c.

[0117] Compared with Figure 4 and Figure 5 , Figure 5 The fourth plate C4 in the fourth plate C4 is prepared in the patterning process of the gate electrode layer GE; at the same time, the third portion 207c, the third sub-section 202c and the fourth plate C4 can be formed in one process, which simplifies the structure of the storage capacitor Cst, reduces the number of masks and reduces the process cost.

[0118] Please refer to Figure 1 , Figure 5 for the fourth structure diagram of the cross section MM in this application, Figure 4 Figure 5 the structure in this application is the same as or similar to the structure in Figure 6 , except that:

[0119] Please refer to Figure 6 , the semiconductor layer AS further includes a third active part AS3 arranged between the third part 207c and the buffer layer 201, one side of the third active part AS3 is in contact with the buffer layer 201, and the other side of the third active part AS3 is in contact with the third part 207c, that is, the first plate C1 and the fourth plate C4 are spaced apart by the buffer layer 201, the third active part AS3, the third part 207c and the third sub-part 202c.

[0120] In this embodiment, due to the shielding of the fourth plate C4, the third active part AS3 is not subjected to conductorization treatment, that is, the mobility of the third active part AS3 is the same as that of the first active part AS1.

[0121] Please refer to Figure 1 , Figure 6 for the fifth structure diagram of the cross section MM in this application, Figure 2 Figure 6 the structure in this application is the same as or similar to the structure in ​ , except that:

[0122] Please refer to ​ , the anode layer 401 can further include a fifth plate C5 arranged opposite to the third plate C3, the fifth plate C5 is electrically connected to the second plate C2 through a twelfth via hole HL12, and the first plate C1, the second plate C2, the third plate C3, the fourth plate C4 and the fifth plate C5 of the application are connected in parallel to form a storage capacitor Cst, which increases the capacitance of the storage capacitor Cst, effectively compensates the threshold voltage of the driving transistor, and improves the display picture of the display panel 100.

[0123] The application further provides a display device, which includes the display panel described above. It should be noted that the display device of the application can be any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigation devices, etc.

[0124] ​​The application provides a display panel and a display device; the display panel comprises a substrate, a light shielding layer, a semiconductor layer, a gate layer, a first source-drain layer and a second source-drain layer arranged on the substrate, the light shielding layer comprises a first plate, the first source-drain layer comprises a second plate arranged opposite to the first plate, the second source-drain layer comprises a third plate arranged opposite to the second plate, the semiconductor layer or the gate layer further comprises a fourth plate, and the first plate, the second plate, the third plate and the fourth plate constitute a storage capacitor of the display panel; the application utilizes the materials of the light shielding layer, the first source-drain layer and the second source-drain layer in the display panel to prepare three capacitor plates, and utilizes the material of one of the semiconductor layer or the gate layer to prepare one capacitor plate, so that an additional conductive layer is not needed to prepare the capacitor plate, the structure of the storage capacitor is simplified, and the preparation cost of the display panel is reduced

[0125] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0126] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0127] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0128] The above is only the preferred embodiment of the present application, and does not limit the present application in any form, but any simple modification, equivalent change and modification made according to the technical essence of the present application without departing from the technical solution content of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate; a light shielding layer provided on one side of the substrate substrate, the light shielding layer comprising a first plate; a semiconductor layer provided on a side of the light shielding layer away from the substrate substrate; a gate layer provided on a side of the semiconductor layer away from the substrate substrate; a first source-drain layer provided on a side of the gate layer away from the substrate substrate, the first source-drain layer comprising a second plate provided opposite the first plate; a second source-drain layer provided on a side of the first source-drain layer away from the substrate substrate, the second source-drain layer comprising a third plate provided opposite the second plate; a pixel layer comprising a first pixel definition layer and a second pixel definition layer, the first pixel definition layer being provided on a side of the second source-drain layer away from the substrate substrate, and the second pixel definition layer being provided on a surface of the first pixel definition layer away from the substrate substrate; wherein the semiconductor layer or the gate layer further comprises a fourth plate, the fourth plate being provided between the first plate and the second plate, and the first plate, the second plate, the third plate and the fourth plate forming a storage capacitor of the display panel.

2. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area, at least one first transistor is arranged in the display area, and at least one second transistor is arranged in the non-display area. The semiconductor layer comprises a first active part of the first transistor and a second active part of the second transistor, and the mobility of the first active part is less than or equal to the mobility of the second active part.

3. The display panel of claim 2, wherein, The display panel further comprises: a buffer layer provided between the semiconductor layer and the light shielding layer; wherein the surface of the first active part and the second active part away from the gate layer is in contact with the buffer layer, and the mobility of the first active part is equal to the mobility of the second active part.

4. The display panel of claim 2, wherein, The display panel further comprises: a buffer layer provided between the semiconductor layer and the light shielding layer; a protective layer comprising a first part located in the display area and a second part located in the non-display area, the first part being provided on a surface of the first active part away from the substrate substrate, and the second part being provided between the second active part and the buffer layer; wherein the mobility of the first active part is less than the mobility of the second active part.

5. The display panel of claim 4, wherein, The semiconductor layer comprises the fourth plate, and the fourth plate is in contact with the surface of the buffer layer away from the substrate substrate.

6. The display panel of claim 4, wherein, The protective layer further comprises a third part provided between the buffer layer and the fourth plate; wherein the gate layer comprises the fourth plate, and the fourth plate is provided on a side of the third part away from the substrate substrate.

7. The display panel of claim 6, wherein, The semiconductor layer further comprises a third active part provided between the third part and the buffer layer, and the mobility of the third active part is the same as the mobility of the first active part; wherein one side of the third active part is in contact with the buffer layer, and the other side of the third active part is in contact with the third part.

8. The display panel of any one of claims 1 to 7, wherein, The display panel further comprises: A passivation layer is disposed between the first source-drain layer and the second source-drain layer, and covers the first source-drain layer; A first planar layer is disposed on a side of the passivation layer away from the substrate, and a part of the second source-drain layer is in contact with a surface of the first planar layer away from the substrate; The first planar layer is provided with a first opening, and the third plate is disposed in the first opening.

9. The display panel of any one of claims 1 to 7, wherein, The display panel further comprises: A first planar layer is disposed between the first source-drain layer and the second source-drain layer; A second planar layer is disposed on a side of the first planar layer away from the substrate; The photosensitivity of the second planar layer is greater than or equal to the photosensitivity of the first planar layer.

10. The display panel of any one of claims 1 to 7, wherein, The display panel further comprises: An anode layer is disposed on a side of the second source-drain layer away from the substrate, and the anode layer comprises a fifth plate disposed opposite to the third plate, and the first plate, the second plate, the third plate, the fourth plate and the fifth plate constitute a storage capacitor of the display panel.

11. A display device comprising: The display device comprises the display panel according to any one of claims 1 to 10.

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