Power-off time sequence control circuit and communication equipment
By using voltage divider and switching units in communication equipment to control the power-down sequence of the DC-DC unit, the problems of high cost and complex design in the prior art are solved, and stable and low-cost power-down sequence control is achieved.
Patent Information
- Application Number
- CN202520467306.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2035-03-17
AI Technical Summary
Existing communication equipment uses a dedicated power timing control chip for power-down timing control, which involves a complex circuit design and is costly.
N power-down control modules are used, including voltage divider units, switching units, and DC-DC units. The voltage divider units control the switching units according to different voltages, so that the DC-DC units are turned off in sequence, thereby realizing power-down timing control and avoiding the need to program a dedicated chip.
It achieves stability and consistency in power-down timing control, reduces circuit costs, and simplifies the design process.
Smart Images
Figure CN223757051U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to communication equipment power supply technical field especially relates to a power down timing control circuit and communication equipment. BACKGROUND
[0002] The core chip (such as CPU, switching chip, PHY chip etc.) in communication equipment has multiple types of power supply voltage requirements, these chips have certain requirements on power-on timing, and also have strict requirements on power-down timing, need to meet the chip power-down timing requirements in peripheral power supply design, otherwise the damage of chip is likely to appear.
[0003] The existing power-down timing control scheme mainly includes power supply timing control chip (including CPLD) scheme and load capacitance size difference scheme, and the above two schemes have the following problems:
[0004] 1, power supply timing control chip (including CPLD) needs to be programmed, and the cost is higher, and the power supply voltage of power supply timing control chip itself needs to be guaranteed to be powered down last, and a separate power supply circuit needs to be additionally increased, and the design is complex, and the cost is higher.
[0005] 2, the capacitance value of load capacitance must have a large difference in load capacitance size difference scheme to ensure power-down timing, and the capacitance value design of load capacitance is difficult, and the stability and consistency of different voltage power-down delay time interval values are poor through load capacitance difference. INVENTION CONTENTS
[0006] The utility model embodiment provides a power down timing control circuit and communication equipment to solve the technical problem of higher circuit cost of the existing communication equipment in related art using special power supply timing control chip for power-down timing control.
[0007] In a first aspect, a power-down timing control circuit is provided, comprising:
[0008] N power-down control modules connected to a power supply, each of the N power-down control modules comprising: a voltage dividing unit, a switching unit and a DC-DC unit, the voltage dividing unit being connected to the power supply and the switching unit, and the switching unit being connected to the power supply and the DC-DC unit;
[0009] When the power supply voltage decreases, the N voltage dividing units are configured to control the corresponding switching units according to different voltages, so that the corresponding DC-DC units are sequentially turned off to stop outputting the power supply voltage, wherein the N voltage dividing units are different from each other, and N is a positive integer.
[0010] In some embodiments, the voltage dividing unit comprises a first voltage dividing sub-unit and a second voltage dividing sub-unit, the first voltage dividing sub-unit and the second voltage dividing sub-unit are connected with a power supply and the switch unit, the first voltage dividing sub-unit and the second voltage dividing sub-unit are respectively used for outputting a first power supply voltage and a second power supply voltage to the switch unit to control the corresponding switch unit.
[0011] In some embodiments, the first voltage dividing sub-unit comprises a first resistor and a second resistor, a first end of the first resistor is connected with the power supply, a second end of the first resistor is connected with the switch unit, a second end of the second resistor is connected with the second end of the first resistor, and a first end of the second resistor is grounded.
[0012] The second voltage dividing sub-unit comprises a third resistor and a fourth resistor, a first end of the third resistor is connected with the power supply, a second end of the third resistor is connected with the switch unit, a second end of the fourth resistor is connected with the second end of the third resistor, and a first end of the fourth resistor is grounded.
[0013] In some embodiments, the switch unit comprises a connected adjustable switch sub-unit and an enable switch sub-unit, the adjustable switch sub-unit is connected with the voltage dividing unit, and the enable switch sub-unit is connected with the voltage dividing unit, a power supply and the DC-DC unit.
[0014] When the power supply voltage decreases, N voltage dividing units are used to control the corresponding adjustable switch sub-unit to change the working state, and then drive the corresponding enable switch sub-unit to change the working state, so that the corresponding DC-DC unit is sequentially turned off to stop outputting the power supply voltage.
[0015] In some embodiments, the adjustable switch sub-unit comprises a voltage reference power supply, a comparator, a first transistor, a first diode and a second diode, a positive input end of the comparator is connected with the second end of the first resistor, a negative input end of the comparator is connected with the voltage reference power supply, an output end of the comparator is connected with a base of the first transistor, an emitter of the first transistor is grounded, a positive electrode of the first diode is connected with the positive input end of the comparator, a negative electrode of the first diode is connected with a collector of the first transistor, a positive electrode of the second diode is connected with the emitter of the first transistor, and a positive electrode of the second diode is connected with the collector of the first transistor.
[0016] When the power supply voltage drops, if the voltage output from the second end of the first resistor to the positive input end of the corresponding comparator is less than the voltage of the voltage reference power supply, the level signal output by the comparator causes the corresponding first transistor to be turned off, driving the corresponding enable switch subunit to change the working state, and causing the corresponding DC-DC unit to be turned off to stop outputting the power supply voltage.
[0017] In some embodiments, when the DC-DC unit is low-level off, the enable switch subunit comprises a first MOS tube and a first pull-up resistor, the gate of the first MOS tube is connected with the second end of the third resistor and the collector of the first transistor, the source of the first MOS tube is grounded, the drain of the first MOS tube is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with the power supply, and the second end of the first pull-up resistor is connected with the enable end of the DC-DC unit.
[0018] In some embodiments, when the DC-DC unit is high-level off, the enable switch subunit comprises a first MOS tube, a second MOS tube, a first pull-up resistor and a second pull-up resistor;
[0019] the gate of the first MOS tube is connected with the second end of the third resistor and the collector of the first transistor, the source of the first MOS tube and the source of the second MOS tube are grounded, the drain of the first MOS tube is connected with the gate of the second MOS tube, the drain of the second MOS tube is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with the power supply, the second end of the first pull-up resistor is connected with the gate of the second MOS tube, the first end of the second pull-up resistor is connected with the power supply, and the second end of the second pull-up resistor is connected with the enable end of the DC-DC unit.
[0020] In some embodiments, when the DC-DC unit is low-level off, the enable switch subunit comprises a second transistor and a first pull-up resistor, the base of the second transistor is connected with the second end of the third resistor and the collector of the first transistor, the emitter of the second transistor is grounded, the collector of the second transistor is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with the power supply, and the second end of the first pull-up resistor is connected with the enable end of the DC-DC unit.
[0021] In some embodiments, when the DC-DC unit is high-level off, the enable switch subunit comprises a second transistor, a third transistor, a first pull-up resistor and a second pull-up resistor;
[0022] The gate of the second triode is connected with the second end of the third resistor and the collector of the first triode, the emitter of the second triode and the emitter of the third triode are grounded, the collector of the second triode is connected with the base of the third triode, the collector of the third triode is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with a power supply, the second end of the first pull-up resistor is connected with the base of the third triode, the first end of the second pull-up resistor is connected with the power supply, and the second end of the second pull-up resistor is connected with the enable end of the DC-DC unit.
[0023] In a second aspect, a communication device is provided, comprising the power-off timing control circuit.
[0024] The beneficial effects brought by the technical scheme of the utility model include:
[0025] The utility model discloses a power-off timing control circuit and communication device, the power-off timing control circuit is equipped with N power-off control module, and the voltage dividing unit of N power-off control module is different, and when the power supply is powered off, corresponding DC-DC unit can be turned off in turn under different voltage control, and the output power supply voltage is stopped, and the power-off timing control function is realized. BRIEF DESCRIPTION OF DRAWINGS
[0026] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the drawings needed in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained without creative labor.
[0027] Figure 1 The utility model provides a kind of power-off timing control circuit for the principle diagram of the utility model embodiment;
[0028] Figure 2 The utility model provides a kind of power-off timing control circuit for the circuit diagram of the voltage dividing unit of the utility model embodiment;
[0029] Figure 3 The utility model provides a kind of adjustable switch subunit for the circuit diagram of the utility model embodiment;
[0030] Figure 4 The utility model provides a kind of power-off timing control circuit for the first circuit diagram of the utility model embodiment;
[0031] Figure 5A second circuit diagram of a power-off timing control circuit is provided for the embodiment of the utility model;
[0032] Figure 6 A third circuit diagram of a power-off timing control circuit is provided for the embodiment of the utility model;
[0033] Figure 7 A fourth circuit diagram of a power-off timing control circuit is provided for the embodiment of the utility model. DETAILED DESCRIPTION
[0034] In order to make the purpose, technical scheme and advantages of the embodiment of the utility model clearer, the technical scheme in the embodiment of the utility model will be described clearly and completely below in combination with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, rather than all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without making creative labor belong to the protection scope of the utility model.
[0035] The embodiment of the utility model provides a power-off timing control circuit, which can solve the technical problem of high circuit cost of the existing communication equipment using a special power timing control chip for power-off timing control.
[0036] Referring to Figure 1 The embodiment of the utility model provides a power-off timing control circuit, which comprises N power-off control modules connected with a power supply, wherein each power-off control module comprises a voltage dividing unit, a switching unit and a DC-DC unit, the voltage dividing unit is connected with the power supply and the switching unit, and the switching unit is connected with the power supply and the DC-DC unit. The output end of the DC-DC unit of each power-off control module is connected with a corresponding load.
[0037] When the power supply voltage drops, the N voltage dividing units control the corresponding switching units according to different voltages, so that the corresponding DC-DC units are sequentially turned off and stop outputting the power supply voltage. The N voltage dividing units are different from each other, and N is a positive integer.
[0038] The power-off timing control circuit in the embodiment of the application comprises N power-off control modules, and the voltage dividing units of the N power-off control modules are different from each other. When the power supply is powered off, the corresponding DC-DC units can be sequentially turned off under the control of different voltages to stop outputting the power supply voltage, so that the power-off timing control function is realized. Since the voltage dividing unit and the switching unit can be built by using basic electronic components, compared with the existing technology of using a special power-off timing control chip for power-off timing control, the circuit design is simple and the cost is low without programming.
[0039] As an optional embodiment, in one utility model embodiment, referring toFigure 1 As shown in the figure, the voltage dividing unit includes a first voltage dividing sub-unit and a second voltage dividing sub-unit, the first voltage dividing sub-unit and the second voltage dividing sub-unit are connected with the power supply and the switch unit, and the first voltage dividing sub-unit and the second voltage dividing sub-unit are respectively used to output a first power supply voltage and a second power supply voltage to the switch unit to control the corresponding switch unit.
[0040] Further, referring to Figure 2 As shown in the figure, the first voltage dividing sub-unit includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is connected with the power supply, a second end of the first resistor R1 is connected with the switch unit, a second end of the second resistor R2 is connected with the second end of the first resistor R1, and a first end of the second resistor R2 is grounded.
[0041] The second voltage dividing sub-unit includes a third resistor R3 and a fourth resistor R4, a first end of the third resistor R3 is connected with the power supply, a second end of the third resistor R3 is connected with the switch unit, a second end of the fourth resistor R4 is connected with the second end of the third resistor R3, and a first end of the fourth resistor R4 is grounded.
[0042] When the power supply voltage drops, by adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, the corresponding switch unit can be controlled under different voltage conditions, and the corresponding DC-DC unit is sequentially turned off to stop outputting the power supply voltage to the corresponding load.
[0043] As an optional implementation, in one utility model embodiment, referring to Figure 1 As shown in the figure, the switch unit includes a connected adjustable switch sub-unit and an enable switch sub-unit, the adjustable switch sub-unit is connected with the voltage dividing unit, and the enable switch sub-unit is connected with the voltage dividing unit, the power supply and the DC-DC unit.
[0044] When the power supply voltage drops, the N voltage dividing units are used to control the corresponding adjustable switch sub-unit to change the working state, and then drive the corresponding enable switch sub-unit to change the working state, so that the corresponding DC-DC unit is sequentially turned off.
[0045] Specifically, referring to Figure 3As shown, the adjustable switch subunit includes a voltage reference power supply Vref, a comparator U1, a first triode Q1, a first diode D1 and a second diode D2, the non-inverting input terminal of the comparator U1 is connected with the second terminal of the first resistor R1, the inverting input terminal of the comparator U1 is connected with the voltage reference power supply Vref, the output terminal of the comparator U1 is connected with the base of the first triode, the emitter of the first triode Q1 is grounded, the anode of the first diode D1 is connected with the non-inverting input terminal of the comparator U1, the cathode of the first diode D1 is connected with the collector of the first triode Q1, the anode of the second diode D2 is connected with the emitter of the first triode Q1, and the cathode of the second diode D2 is connected with the collector of the first triode Q1.
[0046] When the power supply voltage decreases, if the voltage output from the second terminal of the first resistor R1 to the non-inverting input terminal of the corresponding comparator U1 is less than the voltage of the voltage reference power supply, the comparator U1 outputs a low level signal to make the corresponding first triode Q1 cut off, drive the corresponding enable switch subunit to work, and make the corresponding DC-DC unit cut off to stop outputting the power supply voltage.
[0047] Referring to Figure 3 As shown, the adjustable switch subunit is provided with three pins: REF, AN and CA, which correspond to the non-inverting input terminal of the comparator U1, the emitter and the collector of the first triode Q1 respectively. When the power supply voltage starts to decrease, if the voltage input from the second terminal of the first resistor R1 to the REF pin is greater than or equal to the value of the voltage reference power supply Vref, the comparator U1 outputs a high level to the base of the first triode Q1. Since the collector (AN pin) of the first triode Q1 is grounded, the voltage difference between the base and the emitter of the first triode Q1 is greater than the turn-on voltage, so the first triode Q1 is turned on, CA and AN are connected, and CA is grounded. At this time, the working state of the corresponding enable switch subunit does not change (working in the first state), the corresponding DC-DC unit is turned on, and the power supply voltage is output to the subsequent load. When the power supply voltage continues to decrease, if the voltage input from the second terminal of the first resistor R1 to the REF pin is less than the value of the voltage reference power supply Vref, the comparator U1 outputs a low level to the base of the first triode Q1. Since the collector (AN pin) of the first triode Q1 is grounded, the voltage of the base and the emitter of the first triode Q1 is 0, so the first triode Q1 is cut off, CA and AN are not connected, and the output state of CA is high resistance. At this time, the working state of the corresponding enable switch subunit changes (working in the second state), the corresponding DC-DC unit is cut off, and the output of the power supply voltage to the subsequent load is stopped.
[0048] As an optional embodiment, in one utility model embodiment, when the DC-DC unit is low level off (positive logic enable off), the enable switch subunit includes a first MOS tube M1 and a first pull-up resistor RL1, the gate of the first MOS tube M1 is connected with the second end of the third resistor R3 and the collector of the first triode Q1, the source of the first MOS tube M1 is grounded, the drain of the first MOS tube M1 is connected with the enable end (EN) of the DC-DC unit, the first end of the first pull-up resistor RL1 is connected with the power supply, and the second end of the first pull-up resistor RL1 is connected with the enable end of the DC-DC unit.
[0049] Referring to Figure 4 As shown, the voltage on the REF that enables the CA and the AN of the adjustable switch subunit is Vth, when Vth is greater than or equal to Vref, the CA and the AN are connected, and the CA is 0; when Vth is less than Vref, the CA and the AN are not connected, and the CA is in a high resistance state. After the power supply of the device is powered off, the input voltage starts to drop, when the voltage Vth divided by the first resistor R1 and the second resistor R2 is greater than or equal to Vref, the CA and the AN are connected, and the value of the CA is 0, then the voltage difference between the gate and the source of the first MOS tube is 0, and the first MOS tube is cut off, at this time, it can be understood that the working state of the enable switch subunit does not change (working in the first state), the drain of the first MOS tube is in a high resistance state and is pulled to the input voltage value by the first pull-up resistor RL1, at this time, the input voltage value is higher than the threshold value of the enable end of the DC-DC unit, the DC-DC unit is turned on and outputs normally. The input voltage value continues to drop, when the voltage value Vth divided by the first resistor R1 and the second resistor R2 is less than Vref, the CA and the AN are not connected, and the CA is in a high resistance state, at this time, the voltage value divided by the third resistor R3 and the fourth resistor R4 pulls the CA in a high resistance state high, the voltage difference between the gate and the source of the first MOS tube is greater than the opening voltage of the first MOS tube, and the first MOS tube is turned on, at this time, it can be understood that the working state of the enable switch subunit changes (working in the second state), the drain and the source of the first MOS tube are turned on, since the source is already grounded, the drain voltage is also 0, then the enable end of the DC-DC unit is 0 level, the DC-DC unit is turned off, the output voltage is turned off, and the power-off control is realized.
[0050] From the above analysis, it can be seen that the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 can realize that when the input voltage drops to a certain expected voltage value, the voltage value Vth of the first resistor R1 and the second resistor R2 divided voltage is less than Vref, the DC-DC unit output voltage is turned off, and the power down control is realized. Different power down control modules can realize that when the input voltage drops to different expected voltage values, the voltage value Vth of the first resistor R1 and the second resistor R2 divided voltage is less than Vref, the output voltage of different DC-DC units is turned off, that is, the power down voltage turn-off value of each of the multiple DC-DC unit output voltages is different, thereby realizing the stable power down timing control of the multiple voltage output. Without programming the special power timing control chip, only by adjusting the value of the voltage dividing resistor, the setting of the power down voltage value of the different voltage power supply can be realized, and once the voltage dividing resistor value is determined, the power down voltage value is fixed, the power down interval time of different voltages is also fixed, the power down time interval of different voltages is controllable, and the power down timing control stability and consistency is good.
[0051] As an optional embodiment, in one utility model embodiment, when the DC-DC unit is high level off (negative logic enable off), the enable switch subunit includes a first MOS tube M1, a second MOS tube M2, a first pull-up resistor RL1 and a second pull-up resistor RL2.
[0052] The gate of the first MOS tube M1 is connected with the second end of the third resistor R3 and the collector of the first triode Q1, the source of the first MOS tube M1 and the source of the second MOS tube M2 are grounded, the drain of the first MOS tube M1 is connected with the gate of the second MOS tube, the drain of the second MOS tube M2 is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor RL1 is connected with the power supply, the second end of the first pull-up resistor RL1 is connected with the gate of the second MOS tube M2, the first end of the second pull-up resistor RL2 is connected with the power supply, and the second end of the second pull-up resistor RL2 is connected with the enable end of the DC-DC unit.
[0053] Similarly, referring to Figure 5As shown, the voltage on REF is set to Vth to make the CA and AN of the adjustable switch subunit conduct, when Vth is greater than or equal to Vref, CA and AN are connected, CA is 0; when Vth is less than Vref, CA and AN are not connected, CA is in a high impedance state. After the power of the device is turned off, the input voltage starts to drop, when the voltage Vth divided by the first resistor R1 and the first resistor R2 is greater than or equal to Vref, CA and AN are connected, the value of CA is 0, and the voltage difference between the gate and the source of the first MOS tube is 0, so the first MOS tube is cut off, the drain of the first MOS tube is in a high impedance state and is pulled to the input voltage value by the first pull-up resistor RL1, and the input is input to the gate of the second MOS tube, the voltage difference between the gate and the source of the second MOS tube is greater than the opening voltage of the second MOS tube, and the second MOS tube is turned on. At this time, it can be understood that the working state of the enable switch subunit is unchanged (working in the first state), the drain and the source of the second MOS tube are connected, and since the source is grounded, the drain of the second MOS tube is at 0 level, so that the DC-DC unit outputs normally and the output voltage is not powered off. The input voltage continues to drop, when the voltage value Vth divided by the first resistor R1 and the second resistor R2 is less than Vref, CA and AN are not connected, CA is in a high impedance state, and the voltage value divided by the third resistor R3 and the fourth resistor R4 pulls up CA in a high impedance state, the voltage difference between the gate and the source of the first MOS tube is greater than the opening voltage of the first MOS tube, the first MOS tube is turned on, the drain and the source of the first MOS tube are connected, and since the source is grounded, the drain voltage is also 0, so the voltage difference between the gate and the source of the second MOS tube is 0, and the second MOS tube is cut off. At this time, it can be understood that the working state of the enable switch subunit is changed (working in the second state), the drain of the second MOS tube is in a high impedance state and is pulled up to the input level of the enable end of the DC-DC unit by the second pull-up resistor RL2, and since the DC-DC unit is a negative logic enable, the DC-DC unit is turned off, the output voltage is turned off, and the power-off control is realized.
[0054] As an optional embodiment, in one utility model embodiment, as shown in Figure 6 As shown, when the DC-DC unit is turned off at a low level, the enable switch subunit comprises a second transistor Q2 and a first pull-up resistor R1, the base of the second transistor Q2 is connected with the second end of the third resistor R3 and the collector of the first transistor Q1, the emitter of the second transistor Q2 is grounded, the collector of the second transistor Q2 is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor RL1 is connected with the power supply, and the second end of the first pull-up resistor RL1 is connected with the enable end of the DC-DC unit. The second transistor Q2 is similar to the first MOS tube M1 in function, and the working principle is not repeated here.
[0055] As an optional embodiment, in one utility model embodiment, as shown inFigure 7 As shown, when the DC-DC unit is high level off, the enable switch subunit includes a second transistor Q2, a third transistor Q3, a first pull-up resistor RL1 and a second pull-up resistor RL2.
[0056] The gate of the second transistor Q2 is connected with the second end of the third resistor R3 and the collector of the first transistor Q1, the emitter of the second transistor Q2 and the emitter of the third transistor Q3 are grounded, the collector of the second transistor Q2 is connected with the base of the third transistor Q3, the collector of the third transistor Q3 is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor RL1 is connected with the power supply, the second end of the first pull-up resistor RL1 is connected with the base of the third transistor, the first end of the second pull-up resistor RL2 is connected with the power supply, and the second end of the second pull-up resistor RL2 is connected with the enable end of the DC-DC unit. The second transistor Q2 and the third transistor Q3 are similar to the functions of the first MOS tube M1 and the second MOS tube M2, and the working principle is not described herein.
[0057] The utility model embodiment further provides a kind of communication equipment, comprising the power-down timing control circuit of preceding description.
[0058] In the description of the utility model, it should be explained that the orientation or position relationship indicated by the terms "upper", "lower" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and is not indicative or suggestive of the device or element indicated must have a particular orientation, be constructed and operated with a particular orientation, so it cannot be understood as a limitation on the utility model. Unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected;It can be mechanically connected, or electrically connected;It can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For ordinary skilled in the art, the specific meaning of the above-mentioned terms in the utility model can be understood according to specific circumstances.
[0059] It should be noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
[0060] The above description is merely that of the specific embodiments of the present application, and enables those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A power down timing control circuit, characterized by, The power-off timing control circuit comprises: N power-off control modules connected with the power supply, each of the N power-off control modules comprising a voltage dividing unit, a switching unit and a DC-DC unit, the voltage dividing unit being connected with the power supply and the switching unit, the switching unit being connected with the power supply and the DC-DC unit; when the power supply voltage drops, the N voltage dividing units are used to control the corresponding switching units according to different voltages, so that the corresponding DC-DC units are sequentially turned off to stop outputting the power supply voltage; wherein the N voltage dividing units are different, and N is a positive integer.
2. The power-off timing control circuit according to claim 1, characterized in that: the voltage dividing unit comprises a first voltage dividing sub-unit and a second voltage dividing sub-unit, the first voltage dividing sub-unit and the second voltage dividing sub-unit being connected with the power supply and the switching unit, the first voltage dividing sub-unit and the second voltage dividing sub-unit being respectively used to output first power supply voltage and second power supply voltage to the switching unit to control the corresponding switching unit.
3. The power-off timing control circuit according to claim 2, characterized in that: the first voltage dividing sub-unit comprises a first resistor and a second resistor, a first end of the first resistor being connected with the power supply, a second end of the first resistor being connected with the switching unit, a second end of the second resistor being connected with the second end of the first resistor, and a first end of the second resistor being grounded; the second voltage dividing sub-unit comprises a third resistor and a fourth resistor, a first end of the third resistor being connected with the power supply, a second end of the third resistor being connected with the switching unit, a second end of the fourth resistor being connected with the second end of the third resistor, and a first end of the fourth resistor being grounded.
4. The power-off timing control circuit according to claim 3, characterized in that: the switching unit comprises a connected adjustable switching sub-unit and an enable switching sub-unit, the adjustable switching sub-unit being connected with the voltage dividing unit, and the enable switching sub-unit being connected with the voltage dividing unit, the power supply and the DC-DC unit; when the power supply voltage drops, the N voltage dividing units are used to control the corresponding adjustable switching sub-units to change the working state, and then drive the corresponding enable switching sub-units to change the working state, so that the corresponding DC-DC units are sequentially turned off to stop outputting the power supply voltage.
5. The power-off timing control circuit according to claim 4, characterized in that: the adjustable switching sub-unit comprises a voltage reference power supply, a comparator, a first transistor, a first diode and a second diode, a positive input end of the comparator being connected with the second end of the first resistor, a negative input end of the comparator being connected with the voltage reference power supply, an output end of the comparator being connected with a base of the first transistor, an emitter of the first transistor being grounded, a positive electrode of the first diode being connected with the positive input end of the comparator, a negative electrode of the first diode being connected with a collector of the first transistor, a positive electrode of the second diode being connected with the emitter of the first transistor, and a positive electrode of the second diode being connected with the collector of the first transistor. When the power supply voltage drops, if the voltage output from the second end of the first resistor to the positive input end of the corresponding comparator is less than the voltage of the voltage reference power supply, the level signal output by the comparator makes the corresponding first transistor cut off, drives the corresponding enable switch subunit to change the working state, and makes the corresponding DC-DC unit stop outputting the power supply voltage.
6. The power-down timing control circuit according to claim 5, characterized in that: When the DC-DC unit is in low-level shutdown, the enable switch subunit comprises a first MOS tube and a first pull-up resistor, the gate of the first MOS tube is connected with the second end of the third resistor and the collector of the first transistor, the source of the first MOS tube is grounded, the drain of the first MOS tube is connected with the enable end of the DC-DC unit, and the first end of the first pull-up resistor is connected with the power supply, and the second end of the first pull-up resistor is connected with the enable end of the DC-DC unit.
7. The power-down timing control circuit according to claim 5, characterized in that: When the DC-DC unit is in high-level shutdown, the enable switch subunit comprises a first MOS tube, a second MOS tube, a first pull-up resistor and a second pull-up resistor; the gate of the first MOS tube is connected with the second end of the third resistor and the collector of the first transistor, the source of the first MOS tube and the source of the second MOS tube are grounded, the drain of the first MOS tube is connected with the gate of the second MOS tube, the drain of the second MOS tube is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with the power supply, the second end of the first pull-up resistor is connected with the gate of the second MOS tube, the first end of the second pull-up resistor is connected with the power supply, and the second end of the second pull-up resistor is connected with the enable end of the DC-DC unit.
8. The power-down timing control circuit according to claim 5, characterized in that: When the DC-DC unit is in low-level shutdown, the enable switch subunit comprises a second transistor and a first pull-up resistor, the base of the second transistor is connected with the second end of the third resistor and the collector of the first transistor, the emitter of the second transistor is grounded, the collector of the second transistor is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with the power supply, and the second end of the first pull-up resistor is connected with the enable end of the DC-DC unit.
9. The power-down timing control circuit according to claim 5, characterized in that: When the DC-DC unit is in high-level shutdown, the enable switch subunit comprises a second transistor, a third transistor, a first pull-up resistor and a second pull-up resistor; The gate of the second triode is connected with the second end of the third resistor and the collector of the first triode, the emitter of the second triode and the emitter of the third triode are grounded, the collector of the second triode is connected with the base of the third triode, the collector of the third triode is connected with the enable end of the DC-DC unit, the first end of the first pull-up resistor is connected with a power supply, the second end of the first pull-up resistor is connected with the base of the third triode, the first end of the second pull-up resistor is connected with the power supply, and the second end of the second pull-up resistor is connected with the enable end of the DC-DC unit.
10. A communication device, characterized by The power-off timing control circuit according to any one of claims 1-9. The power-off timing control circuit according to any one of claims 1-9.