Memory drive circuit and memory

Abstract

The utility model provides a memory driving circuit and a memory, the memory driving circuit comprises an off-chip driving regulator, a chip selection signal receiver, a first data output module and a second data output module, the chip selection signal receiver is used for receiving a chip selection signal and generating a first control signal; the first data output module is coupled with the chip selection signal receiver and the off-chip driving calibrator, receives a first control signal from the chip selection signal receiver, obtains data output from the off-chip driving calibrator or outputs data to the off-chip driving calibrator; the first control signal is used for indicating closing of a clock receiver in the first data output module; the second data output module is coupled with the chip selection signal receiver and the off-chip driving regulator, receives the first control signal from the chip selection signal receiver, delays the first control signal to generate a first closing signal, and outputs the first closing signal to the off-chip driving regulator; the first closing signal is used for indicating the off-chip driving adjustor to be closed after the off-chip driving adjustor finishes outputting or inputting data.

Description

TECHNICAL FIELD

[0001] The disclosed embodiments of the present application relate to the technical field of storage, and more particularly, to a memory driving circuit and a memory. BACKGROUND

[0002] Current PSRAM protocol specifies that when reading the stored data, the data needs to be synchronized with the data select signal on the bus within a certain delay after the rising / falling edge of the clock signal issued by the user. On the other hand, the PSRAM protocol requires that the off-chip driver (OCD) be turned off within a certain time after the user ends reading by releasing the chip select signal to reduce power consumption. In some use scenarios, the last piece of data may not be sent out due to the OCD being turned off too early after the user ends reading, even causing the bus to be in a high impedance state and generating error data.

[0003] Therefore, how to improve the integrity of data transmission becomes a problem to be solved. CONTENT OF THE INVENTION

[0004] According to the embodiments of the present application, a memory driving circuit and a memory are provided to improve the integrity of data transmission.

[0005] According to an aspect of the present application, a memory driving circuit is disclosed, comprising an off-chip driver, a chip select signal receiver, a first data output module and a second data output module, the chip select signal receiver is configured to receive a chip select signal and generate a first control signal; the first data output module is coupled to the chip select signal receiver and the off-chip driver, the first data output module receives the first control signal from the chip select signal receiver and inputs data to the off-chip driver; the first control signal is configured to indicate the closing of a clock receiver in the first data output module; the second data output module is coupled to the chip select signal receiver and the off-chip driver, the second data output module receives the first control signal from the chip select signal receiver and performs a delay operation on the first control signal to generate a first closing signal, the first closing signal is configured to indicate the closing of the off-chip driver after the off-chip driver completes outputting data.

[0006] According to a second aspect of the present application, a memory is disclosed, comprising the above-mentioned memory driving circuit.

[0007] Since the first control signal can be used to indicate the shutdown of the clock receiver in the first data output module, after the clock receiver is shut down, the first data output module will not receive the clock signal any more, and will not continue to read data, that is, when the clock receiver receives the first control signal, the clock receiver will send the last clock signal to indicate that the first data output module obtains or outputs the last data from or to the off-chip drive trimmer. And since there is a certain time delay from the clock receiver sending the last clock signal to the data reaching the off-chip drive trimmer, the second data output module must shut down the off-chip drive trimmer after the certain time delay to ensure the integrity of the data. Since the first data output module and the second data output module are both coupled to the chip selection signal receiver and receive the first control signal from the chip selection signal receiver, the first data output module and the second data output module can synchronously receive the first control signal, and thus the first control signal can indicate the second data output module to generate the first shutdown signal after a certain time delay to indicate the off-chip drive trimmer to shut down after the off-chip drive trimmer completes the output or input of data, while indicating the first data output module to obtain or input data from or to the off-chip drive trimmer. Therefore, the above scheme prevents the data from being incomplete due to the off-chip drive trimmer shutting down too early by allowing the first data output module and the second data / output module to receive the first control signal, thereby improving the integrity of data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0008] The present application will be further described below in conjunction with the accompanying drawings and embodiments. In the drawings:

[0009] Figure 1 is a module schematic diagram of a memory drive circuit of some embodiments of the present application;

[0010] Figure 2 is a module schematic diagram of a memory drive circuit of some embodiments of the present application;

[0011] Figure 3 is a module schematic diagram of a memory drive circuit of some embodiments of the present application;

[0012] Figure 4 is a module schematic diagram of a memory of some embodiments of the present application. DETAILED DESCRIPTION

[0013] In order to make the skilled in the art better understand the technical solutions of the present application, the technical solutions of the present application are further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0014] The terms used in the embodiments of the present application are only for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0015] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0016] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0017] Reference to "embodiments" herein means that the specific features, structures or properties described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in the specification at each location does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0018] The present application provides a memory driving circuit, please refer to Figure 1 , Figure 1This is a schematic diagram of a memory driver circuit according to some embodiments of this application; in some embodiments, the memory driver circuit 100 includes an off-chip driver tuner. The system comprises a driver (OCD, also known as an offline driver adjuster) 101, a chip select signal receiver 102, a first data output module 103, and a second data output module 104. The chip select signal receiver 102 receives the chip select signal and generates a first control signal. The first data output module 103 is coupled to the chip select signal receiver 102 and the off-chip driver adjuster 101. The first data output module 103 receives the first control signal from the chip select signal receiver 102 and inputs data to the off-chip driver adjuster 101. The first control signal is used to indicate the shutdown of the clock receiver 1031 in the first data output module 103. The second data output module 104 is coupled to the chip select signal receiver 102 and the off-chip driver adjuster 101. The second data input / output module 104 receives the first control signal from the chip select signal receiver 102 and performs a delay operation on the first control signal to generate a first shutdown signal. The first shutdown signal is used to indicate the off-chip driver adjuster 101 to shut down after the off-chip driver adjuster 101 has completed outputting data.

[0019] like Figure 1 As shown, since the first control signal can be used to instruct the clock receiver in the first data output module 103 to turn off, after the clock receiver is turned off, the first data output module 103 will no longer receive clock signals and will not continue to read data. That is, when the clock receiver receives the first control signal, the clock receiver will send the last clock signal to instruct the first data output module 103 to output the last data to the external driver tuner 101. Furthermore, since there is a certain time delay between the clock receiver sending the last clock signal and the external driver tuner 101 outputting data, the second data output module 104 must turn off the external driver tuner 101 after this certain time delay to ensure data integrity. Both the first data output module 103 and the second data output module 104 are coupled to the chip select signal receiver 102 and both receive the first control signal from the chip select signal receiver 102. Therefore, the first data output module 103 and the second data output module 104 can receive the first control signal synchronously. Thus, the first control signal can instruct the first data output module 103 to acquire data from or input data to the external driver tuner 101, while simultaneously instructing the second data output module 104 to generate a first shutdown signal after a certain time delay, so as to instruct the external driver tuner 101 to shut down after it has finished outputting data.

[0020] Therefore, the above solution improves the integrity of data transmission by having both the first data output module 103 and the second data output module 104 receive the first control signal, thereby preventing data incompleteness caused by the premature shutdown of the off-chip driver tuner 101.

[0021] In some embodiments, please refer to Figure 2 , Figure 2 This is a schematic diagram of a memory driver circuit 100 according to other embodiments of this application; the first data output module 103 includes a clock receiver 1031 and a first data output control unit 1032. The clock receiver 1031 is coupled to a chip select signal receiver 102 to receive a first control signal CTL1 and a first clock signal T1, and to generate a second clock signal T2; the first data output control unit 1032 is coupled to the clock receiver 1031 to receive the second clock signal T2 and output data to the external driver tuner 101; wherein, the delay duration corresponding to the first shutdown signal CLS1 matches the delay duration corresponding to the second clock signal T2, so that the external driver tuner 101 is turned off only after outputting the last data. The delay between the clock receiver 1031 receiving the last first clock signal T1 before the arrival of the first control signal CTL1 and the external driver tuner 101 outputting data is T. dqsck That is, the delay duration corresponding to the second clock signal T2; the delay time from when the delay matching unit 1041 receives the first control signal CTL1 until the external driver tuner 101 is turned off is T. HZ That is, the delay duration corresponding to the first shutdown signal CLS1.

[0022] The clock receiver 1031 is used not only to receive the first control signal CTL1, but also to receive the first clock signal T1. After receiving the first clock signal T1, the clock receiver 1031 generates a second clock signal T2, which is transmitted to the first data output control unit 1032. The first data output control unit 1032 controls the operation of outputting data to the external driver tuner 101 according to the second clock signal T2. For example, the first data output control unit 1032 can release data to the external driver tuner 101 when it detects the rising edge of the second clock signal T2, or when it detects the falling edge of the second clock signal T2, and so on. From the time the clock receiver 1031 releases the second clock signal T2 until the external driver tuner 101 outputs the data released by the first data output control unit 1032, there is usually a certain time delay, which is the delay duration T corresponding to the second clock signal T2. dqsckThe clock receiver 1031 stops receiving the first clock signal T1 after receiving the first control signal CTL1. Since the clock receiver 1031 in the first data output module 103 and the second data output module 104 receive the first control signal CTL1 at the same time, in order to make the off-chip driving trimmer 101 be turned off after the last data output by the first data output control unit 1032 is released, the second data output module 104 also needs to send the first off signal CLS1 to the off-chip driving trimmer 101 after a certain time delay after receiving the first control signal CTL1, and the certain time delay is the delay time T HZ corresponding to the first off signal CLS1. HZ corresponding to the second clock signal T2. dqsck When the delay time T dqsck corresponding to the second clock signal T2 matches the delay time T HZ corresponding to the first off signal CLS1, the off-chip driving trimmer 101 can be turned off after the last data output by the first data output control unit 1032 is released.

[0023] In some embodiments, please continue to refer to Figure 2 , the second data output module 104 includes a delay matching unit 1041 and a second data output control unit 1042. The delay matching unit 1041 is coupled to the chip selection signal receiver 102 and delays the first control signal CTL1; the second data output control unit 1042 is coupled to the delay matching unit 1041 and generates the first off signal CLS1 based on the delayed first control signal CTL1.

[0024] As described in the foregoing embodiments, the time delay between the clock receiver 1031 outputting the last clock signal before receiving the first control signal and the off-chip driving trimmer 101 releasing data is represented as T dqsck , and the time between the delay matching unit 1041 receiving the first control signal CTL1 and the second data output module 104 generating the first off signal CLS1 to make the off-chip driving trimmer 101 be turned off is represented as T HZ , then the delay time (i.e. T HZ ) of the delay matching unit 1041 can be configured to be equal to T dqsck , that is, T HZ = T dqsck . At this time, when the clock receiver 1031 and the delay matching unit 1041 receive the first control signal CTL1 at the same time, then T dqsckAfter that, the off-chip driver trimmer 101 outputs data, and the second data output control unit 1042 sends the first close signal CLS1 to the off-chip driver trimmer 101 to close the off-chip driver trimmer 101. Therefore, through the above-mentioned delay matching operation, the off-chip driver trimmer 101 can always be closed after receiving the last data and sending the data to the bus, and the chip select signal is closed after the last clock signal arrives, thereby improving the integrity of data transmission, and T HZ There is no need to adjust according to the working environment, so the user's end adjustment T HZ troubles are also reduced. Moreover, the delay time of the signal through the first data output control unit 1032 until the off-chip driver trimmer outputs data is basically the same as the delay time of the signal through the delay matching unit 1041, so the off-chip driver trimmer is closed soon after the data is completely sent to the bus by the off-chip driver trimmer, thereby also saving power consumption.

[0025] In some embodiments, the connection relationship of the delay matching unit 1041 and the second data output control unit 1042 can not be limited to Figure 2 the embodiment shown in Figure 2 the embodiment shown in, the chip select signal receiver 102 is first connected to the delay matching unit 1041, and then connected to the second data input / output unit. But in some other embodiments, the chip select signal receiver 102 can be first connected to the second data input / output unit, and then connected to the delay matching unit 1041.

[0026] In some embodiments, the number of logic gates in the delay matching unit 1041 is the same as the number of logic gates in the first data output control unit 1032, and the length of the signal transmission path in the delay matching unit 1041 is equal to the length of the signal transmission path in the first data output control unit 1032.

[0027] The number of logic gates and the length of signal transmission path are configured to be the same, so that the delay time of the signal passing through the first data output control unit 1032 to the data output of the off-chip driver calibrator is substantially the same as the delay time of the signal passing through the delay matching unit 1041. Moreover, the signal passes through the same number of logic gates and the same length of path in the delay matching unit 1041 as in the first data output control unit 1032, so that even if the working environment changes, the delay time of the signal passing through the first data output control unit 1032 is always substantially the same as the delay time of the signal passing through the delay matching unit 1041, so that it is not necessary to adjust the delay time of the delay matching unit 1041 according to the working environment, thereby improving the environmental adaptability and convenience of the memory driving circuit. Furthermore, the delay time of the signal passing through the first data output control unit 1032 is substantially the same as the delay time of the signal passing through the delay matching unit 1041, so that the time when the off-chip driver calibrator is closed is close to the time when the off-chip driver calibrator completely sends data to the bus, thereby also being able to save power consumption.

[0028] In some embodiments, please refer to Figure 3 , Figure 3 is a module schematic diagram of the memory driving circuit 100 of some other embodiments of the present application; the first data output control unit 1032 and the second data output control unit 1042 have the same data output control circuit C; the clock receiver is coupled to the first signal input end of the data output control circuit C, and the delay matching unit 1041 is coupled to the second signal input end of the data output control circuit C; the data output control circuit C outputs the first closing signal through the first output end, and the data output control circuit C is coupled to the off-chip driver calibrator 101 through the second output end.

[0029] That is, the first data output control unit 1032 and the second data output control unit 1042 share one data output control circuit C. Therefore, the number of circuit elements can be saved, and the circuit volume can be reduced.

[0030] In some embodiments, please continue to refer to Figure 3 , the first data output module 103 further includes a data buffer unit 10321 coupled to the output end of the data output control circuit C and the off-chip driver calibrator 101 and the storage array M, and based on the third clock signal T3 output by the data output control circuit C, the data obtained from the storage array M is output to the off-chip driver calibrator 101, or the data obtained from the off-chip driver calibrator 101 is written into the storage array M.

[0031] The data buffer unit 10321 is configured to temporarily store data, for example, data fetched from the memory array M and temporarily stored in the data buffer unit 10321, and output the fetched data to the off-chip drive calibrator 101 upon receiving a third clock signal T3 outputted by the data output control circuit C.

[0032] In some embodiments, the number of logic gates included in the delay matching unit 1041 is the same as the number of logic gates included in the signal transmission paths in the data buffer unit 10321 and the data output control circuit IO, and the length of the signal transmission paths in the delay matching unit 1041 is the same as the length of the signal transmission paths between the data buffer unit 10321 and the data output control circuit IO.

[0033] In some embodiments, the data buffer unit 10321 outputs data fetched from the memory array M to the off-chip drive calibrator 101 or writes data fetched from the off-chip drive calibrator 101 to the memory array M in response to the occurrence of a falling edge or a rising edge of the third clock signal.

[0034] In some embodiments, the off-chip drive calibrator 101 is turned off in response to the first turn-off signal after processing data corresponding to the last falling edge or rising edge of the third clock signal. Thus, the integrity of data transmission can be improved.

[0035] The present application also provides a memory 400, please refer to Figure 4 , Figure 4 is a schematic diagram of a memory of some embodiments of the present application. The memory 400 includes the memory drive circuit 100 of any of the above embodiments. The memory also includes a memory array M configured to store data. It is worth noting that Figure 4 The memory 400 is only an example. In other embodiments, in addition to the memory array M and the memory drive circuit 100, the memory 400 also includes other circuits (such as a memory control circuit and a fuse circuit efuse, etc.).

[0036] Those skilled in the art will readily know that modifications and variations can be made to the apparatus and method while maintaining the teachings of the present application. Therefore, the above disclosure should be considered as limited only by the scope of the appended claims.

Claims

1. A memory drive circuit, characterized by, The chip includes: an off-chip drive trimmer; a chip select signal receiver receiving a chip select signal and generating a first control signal; a first data output module coupled to the chip select signal receiver and the off-chip drive trimmer, the first data output module receiving the first control signal from the chip select signal receiver and outputting data to the off-chip drive trimmer; the first control signal being used to indicate the shutdown of a clock receiver in the first data output module; and a second data output module coupled to the chip select signal receiver and the off-chip drive trimmer, the second data output module receiving the first control signal from the chip select signal receiver and performing a delay operation on the first control signal to generate a first shutdown signal, the first shutdown signal being used to indicate the shutdown of the off-chip drive trimmer after the off-chip drive trimmer finishes outputting data. The first data output module includes:

2. The memory drive circuit of claim 1, wherein, a clock receiver coupled to the chip select signal receiver and used to receive the first control signal and a first clock signal and generate a second clock signal; a first data output control unit coupled to the clock receiver, receiving the second clock signal and outputting data to the off-chip drive trimmer; wherein a delay time corresponding to the first shutdown signal matches a delay time corresponding to the second clock signal. The second data output module includes:

3. The memory drive circuit of claim 2, wherein, a delay matching unit coupled to the chip select signal receiver and used to perform a delay operation on the first control signal; a second data output control unit coupled to the delay matching unit and used to generate the first shutdown signal based on the delayed first control signal. The number of logic gates in the delay matching unit is the same as the number of logic gates in the first data output control unit, and the length of a signal transmission path in the delay matching unit is the same as the length of a signal transmission path in the first data output control unit.

4. The memory drive circuit of claim 3, wherein, The first data output control unit and the second data output control unit have the same data output control circuit; 5. The memory drive circuit of claim 3, wherein, the clock receiver is coupled to a first signal input end of the data output control circuit, and the delay matching unit is coupled to a second signal input end of the data output control circuit; the data output control circuit outputs the first shutdown signal through a first output end, and the data output control circuit is coupled to the off-chip drive trimmer through a second output end. The first data output module further includes:

6. The memory drive circuit of claim 5, wherein, a data buffer unit coupled to an output end of the data output control circuit and the off-chip drive trimmer and a memory array, and used to output data obtained from the memory array to the off-chip drive trimmer based on a third clock signal output by the data output control circuit. The number of logic gates in the delay matching unit is the same as the number of logic gates in a signal transmission path between the data buffer unit and the data output control circuit, and the length of a signal transmission path in the delay matching unit is the same as the length of a signal transmission path between the data buffer unit and the data output control circuit.

7. The memory drive circuit of claim 6, wherein, 8. The memory drive circuit of claim 6, wherein ​ The data buffer unit outputs the data fetched from the memory array to the off-chip driver trimmer in response to a falling edge or a rising edge of the third clock signal.

9. The memory drive circuit of claim 8, wherein, The off-chip driver trimmer is turned off in response to the first turn-off signal after processing the data corresponding to the last falling edge or rising edge of the third clock signal.

10. A memory, comprising: The memory includes the memory driver circuit as claimed in any one of claims 1-9.

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