Display device

Abstract

A display device includes: a first active pattern disposed on a substrate; a gate electrode disposed on the first active pattern and including a body portion overlapping the first active pattern in a plan view and a protruding portion protruding from the body portion in a first direction; a lower electrode disposed below the first active pattern and having a first side adjacent to an end portion of the protruding portion in a second direction opposite the first direction; and a first connection pattern disposed on the gate electrode and in contact with the first active pattern, where the first connection pattern covers a first side of the lower electrode.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a display device. More particularly, embodiments of the present application relate to a display device providing visual information. BACKGROUND

[0002] With the development of information technology, the importance of a display device, which is a connection medium between a user and information, is increasing. For example, the use of display devices such as a liquid crystal display (LCD) device, an organic light emitting display (OLED) device, a plasma display panel (PDP), and a quantum dot display device is increasing.

[0003] Generally, a display device includes a plurality of pixels, and each pixel typically includes a transistor, a capacitor, and a light emitting element. These transistors, capacitors, and light emitting elements are formed from a conductive layer. SUMMARY

[0004] According to embodiments of the present application, a display device includes a first active pattern disposed on a substrate, a gate electrode disposed on the first active pattern and including a main portion and a protruding portion, wherein the main portion overlaps the first active pattern in a plan view and the protruding portion protrudes from the main portion in a first direction, a lower electrode disposed below the first active pattern and having a first side edge adjacent to an end portion of the protruding portion in a second direction opposite to the first direction, and a first connection pattern disposed on the gate electrode and in contact with the first active pattern, wherein the first connection pattern covers the first side edge of the lower electrode.

[0005] In embodiments of the present application, in a plan view, the first connection pattern overlaps at least a portion of the protruding portion and is spaced apart from at least a portion of the protruding portion.

[0006] In embodiments of the present application, an upper surface of the gate electrode has a first step due to the lower electrode, an upper surface of an insulating layer between the gate electrode and the first connection pattern has a second step due to the first step of the upper surface of the gate electrode, and an upper surface of the first connection pattern has a third step due to the second step of the upper surface of the insulating layer.

[0007] In embodiments of the present application, the first connection pattern covers a portion of the insulating layer in which the second step is formed.

[0008] In embodiments of the present application, the first step of the upper surface of the gate electrode is formed in the main portion of the gate electrode.

[0009] In embodiments of the present application, the first connection pattern has a second side edge adjacent to the end portion of the protruding portion, and the second side edge is closer to the end portion of the protruding portion than the first side edge of the lower electrode.

[0010] In an embodiment of the present application, in a plan view, a shortest distance in the second direction from the end of the protruding portion to the first side of the lower electrode is greater than a shortest distance in the second direction from the end of the protruding portion to the second side of the first connection pattern.

[0011] In an embodiment of the present application, in a plan view, the second side of the first connection pattern is spaced apart from the first side of the lower electrode in the first direction.

[0012] In an embodiment of the present application, the lower electrode is spaced apart from the protruding portion in a plan view.

[0013] In an embodiment of the present application, the display device further includes: a first transistor and a second transistor, which are electrically connected to each other, and wherein the first transistor includes at least a portion of the gate electrode and the first active pattern.

[0014] In an embodiment of the present application, the display device further includes: a second active pattern, which is spaced apart from the first active pattern; and a gate line, which is spaced apart from the gate electrode and is disposed on the second active pattern, and wherein the second transistor includes at least a portion of the gate line and the second active pattern.

[0015] In an embodiment of the present application, the protruding portion protrudes toward the second active pattern.

[0016] In an embodiment of the present application, the display device further includes: a second connection pattern, which is connected to the protruding portion and the second active pattern, and wherein the second active pattern and the gate electrode are electrically connected to each other through the second connection pattern.

[0017] In an embodiment of the present application, the display device further includes: a data line, which is disposed on the substrate and is electrically connected to the second active pattern; and a third connection pattern, which is connected to the second active pattern and the data line.

[0018] In an embodiment of the present application, the display device further includes: a storage capacitor, which is electrically connected to the first transistor, and wherein the storage capacitor includes at least a portion of the lower electrode and at least a portion of the gate electrode.

[0019] In an embodiment of the present application, the second transistor is a switching transistor that transmits a data voltage based on a switching operation, and the first transistor is a driving transistor that generates a driving current corresponding to the data voltage.

[0020] In an embodiment of the present application, the protruding portion and the main portion are a single main body.

[0021] According to embodiments of the present application, a display device includes a display panel including a plurality of sub-pixels; a gate driver to provide a gate signal to the display panel; and a data driver to provide a data voltage to the display panel, and wherein each of the sub-pixels includes a first transistor, a second transistor, and a storage capacitor electrically connected to each other, the first transistor includes a first active pattern and at least a portion of a gate electrode disposed on the first active pattern, the second transistor includes a second active pattern and at least a portion of a gate line disposed on the second active pattern, wherein the second active pattern is spaced apart from the first active pattern, the storage capacitor includes at least a portion of a lower electrode and at least a portion of the gate electrode, wherein the lower electrode is disposed below the first active pattern, and the gate electrode includes a main portion and a protruding portion, wherein the main portion overlaps the first active pattern in a plan view, and the protruding portion protrudes from the main portion in a first direction and is spaced apart from the lower electrode in the plan view.

[0022] In embodiments of the present application, the display device further includes a first connection pattern disposed on the gate electrode and connected to the first active pattern, and a second connection pattern disposed on the same layer as the first connection pattern and connected to the protruding portion and the second active pattern, and wherein the first connection pattern overlaps at least a portion of the protruding portion and is spaced apart from at least a portion of the protruding portion, and wherein the second active pattern and the gate electrode are electrically connected to each other through the second connection pattern.

[0023] In embodiments of the present application, the second transistor is a switching transistor to transmit the data voltage provided from the data driver based on a switching operation, and the first transistor is a driving transistor to generate a driving current corresponding to the data voltage. BRIEF DESCRIPTION OF DRAWINGS

[0024] Embodiments of the present application will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present application.

[0025] Figure 1 is a plan view illustrating a display device according to embodiments of the present application.

[0026] Figure 2 is a block diagram illustrating Figure 1 a display device.

[0027] Figure 3 is a circuit diagram of a sub-pixel included in Figure 1 a display device.

[0028] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 ,Figure 10 、 Figure 11 and Figure 12 is a layout diagram illustrating a pixel included in a display device of Figure 1 .

[0029] Figure 13 is an enlarged view of the area A of Figure 10 .

[0030] Figure 14 is a cross-sectional view taken along line I-I' of Figure 13 .

[0031] Figure 15 is a cross-sectional view of a display device of Figure 1 . DETAILED DESCRIPTION

[0032] With regard to the embodiments of the present utility model disclosed herein, the structural descriptions and functional descriptions are only illustrative, for the purpose of explaining the embodiments of the present utility model, and the embodiments of the present utility model can be realized in various forms. Accordingly, the present utility model should not be interpreted as being limited to the embodiments described herein.

[0033] Terms such as "first", "second", etc. can be used to describe various components, but the components should not be limited by the terms. The above terms can be used for the purpose of distinguishing one component from another component. For example, a first component can be called a second component, and similarly, a second component can be called a first component, without departing from the spirit and scope of the present utility model.

[0034] Hereinafter, a display device according to an embodiment of the present utility model will be described in more detail with reference to the accompanying drawings. In the drawings and the specification, the same reference numerals are used for the same components, and redundant descriptions of the same components can be omitted or briefly described.

[0035] Figure 1 is a plan view illustrating a display device according to an embodiment of the present utility model, and Figure 2 is a block diagram illustrating a display device of Figure 1 .

[0036] Referring to Figure 1 and Figure 2 , a display device DD according to an embodiment of the present utility model can be divided into a display area DA and a peripheral area PA. The display area DA can display an image, and the peripheral area PA can be located around the display area DA. For example, the peripheral area PA can at least partially surround the display area DA.

[0037] The display device DD can include a display panel PNL, a data driver DDV, a gate driver GDV, and a controller CON.

[0038] The display panel PNL can include a plurality of pixels. For example, the pixels can be arranged in a matrix form along a first direction DR1, a second direction DR2 opposite to the first direction DR1, a third direction DR3 crossing the first direction DR1, and a fourth direction DR4 opposite to the third direction DR3.

[0039] Each of the pixels can include a plurality of sub-pixels. For example, the pixel PX can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can receive a data voltage DATA, a gate signal GS, a driving voltage ELVDD, a common voltage ELVSS, and an initialization voltage VINT.

[0040] In an embodiment of the present utility model, the second sub-pixel SPX2 can receive the data voltage DATA through the first data line 1510 and receive the gate signal GS through the gate line 3500. The first sub-pixel SPX1 can receive the data voltage DATA through the second data line 1520 and receive the gate signal GS through the gate line 3500. The third sub-pixel SPX3 can receive the data voltage DATA through the third data line 1530 and receive the gate signal GS through the gate line 3500.

[0041] The data driver DDV can generate the data voltage DATA based on the output image data ODAT and a data control signal DCTRL. For example, the data driver DDV can generate the data voltage DATA corresponding to the output image data ODAT and output the data voltage DATA in response to the data control signal DCTRL. The data control signal DCTRL can include an output data enable signal, a horizontal start signal, and a load signal.

[0042] In an embodiment of the present utility model, the data driver DDV can be connected to the display panel PNL through a printed circuit board PCB. For example, the data driver DDV can be implemented with a plurality of chips, and each of the chips can be attached to the printed circuit board PCB. However, the present utility model is not necessarily limited thereto. For example, the data driver DDV can be integrated inside the display panel PNL.

[0043] The gate driver GDV can generate the gate signal GS based on a gate control signal GCTRL. The gate signal GS can include a first scan signal SC and a second scan signal SS, which will be described later with reference to FIG. 6. Figure 3 For example, each of the first scan signal SC and the second scan signal SS can include a gate-on voltage turning on a transistor and a gate-off voltage turning off the transistor. The gate control signal GCTRL can include, for example, a vertical start signal or a clock signal, etc.

[0044] In an embodiment of the present utility model, the gate driver GDV can be integrated at both sides of the display panel PNL. For example, the gate driver GDV can be integrated at the left side and the right side of the display panel PNL. Accordingly, the response speed of the display panel PNL can be improved. However, the present utility model is not necessarily limited thereto. For example, the gate driver GDV can be connected to the display panel PNL through a printed circuit board.

[0045] The controller CON (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external main processor. For example, the input image data IDAT can be RGB data including red image data, green image data, and blue image data. The control signals CTRL can include, for example, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal. The controller CON can generate gate control signals GCTRL, data control signals DCTRL, and output image data ODAT based on the input image data IDAT and the control signals CTRL.

[0046] Figure 3 is a circuit diagram of a sub-pixel included in a display apparatus. Figure 1

[0047] Specifically, Figure 3 is a circuit diagram of a first sub-pixel SPX1 included in a display apparatus DD. A second sub-pixel SPX2 and a third sub-pixel SPX3 can have substantially the same circuit structure as the first sub-pixel SPX1.

[0048] Referring to Figure 3 , the first sub-pixel SPX1 can include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor C ST , and a light emitting element LED.

[0049] The first transistor T1 can include a first terminal, a second terminal, and a gate terminal. The first terminal of the first transistor T1 can receive a driving voltage ELVDD. The second terminal of the first transistor T1 can be connected to the light emitting element LED. The gate terminal of the first transistor T1 can be connected to the second transistor T2. The first transistor T1 can be a driving transistor that generates a driving current corresponding to a data voltage DATA. For example, the first transistor T1 can generate the driving current based on the driving voltage ELVDD and the data voltage DATA.

[0050] ​The second transistor T2 can include a first terminal, a second terminal, and a gate terminal. The first terminal of the second transistor T2 can receive the data voltage DATA. The second terminal of the second transistor T2 can be connected to the first transistor T1. The gate terminal of the second transistor T2 can receive the first scan signal SC. The second transistor T2 can be a switching transistor that transfers the data voltage DATA based on a switching operation. For example, the second transistor T2 can transfer the data voltage DATA in response to the first scan signal SC.

[0051] The third transistor T3 can include a first terminal, a second terminal, and a gate terminal. The first terminal of the third transistor T3 can be connected to the first transistor T1. The second terminal of the third transistor T3 can receive the initialization voltage VINT. The gate terminal of the third transistor T3 can receive the second scan signal SS. The third transistor T3 can transfer the initialization voltage VINT in response to the second scan signal SS.

[0052] The storage capacitor C ST may include a first terminal and a second terminal. The storage capacitor C ST first terminal can be connected to the gate terminal of the first transistor T1. The second terminal of the storage capacitor C ST may be connected to the first terminal of the third transistor T3. The storage capacitor C ST may maintain a voltage level of the gate terminal of the first transistor T1 during a deactivation period of the first scan signal SC.

[0053] The light emitting element LED can include a first terminal and a second terminal. The first terminal of the light emitting element LED can be connected to the second terminal of the first transistor T1. The second terminal of the light emitting element LED can receive the common voltage ELVSS. The light emitting element LED can emit light having a luminance corresponding to a driving current. The light emitting element LED can include an organic light emitting element using an organic material as a light emitting layer, an inorganic light emitting element using an inorganic material as a light emitting layer, or the like.

[0054] Figures 4 to 12 is a layout diagram illustrating a pixel included in the display device of Figure 1 .

[0055] Specifically, Figure 4 is a layout diagram illustrating a first conductive pattern. Figure 5 is a layout diagram illustrating a semiconductor pattern. Figure 6 is a layout diagram in which a semiconductor pattern is stacked on a first conductive pattern. Figure 7 is a layout diagram illustrating a second conductive pattern. Figure 8 is a layout diagram in which a second conductive pattern is stacked on a semiconductor pattern. Figure 9 is a layout diagram illustrating a third conductive pattern. Figure 10is a layout in which the third conductive pattern is stacked on the second conductive pattern. Figure 11 is a layout illustrating the fourth conductive pattern, and Figure 12 is a layout in which the fourth conductive pattern is stacked on the third conductive pattern.

[0056] Hereinafter, a layer-by-layer structure of a pixel PX included in a display device DD will be described with reference to Figure 2 and Figures 4 to 12 A layer-by-layer structure of a pixel PX included in a display device DD will be described with reference to

[0057] Referring to Figure 2 and Figure 4 , a first conductive pattern 1000 can be disposed on a substrate SUB. The first conductive pattern 1000 can include a common voltage line 1100, an initialization voltage line 1200, a driving voltage line 1300, a first lower electrode 1410, a second lower electrode 1420, a third lower electrode 1430, a first data line 1510, a second data line 1520, and a third data line 1530.

[0058] The substrate SUB can include a transparent material or an opaque material. Examples of materials that can be used as the substrate SUB in embodiments of the present disclosure can include glass, quartz, and plastic. These can be used alone or in combination with each other.

[0059] The common voltage line 1100 can be disposed on the substrate SUB and can extend in a third direction DR3 and a fourth direction DR4. The common voltage line 1100 can supply a common voltage ELVSS to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0060] The initialization voltage line 1200 can be disposed on the substrate SUB and can extend in the third direction DR3 and the fourth direction DR4. The initialization voltage line 1200 can be spaced apart from the common voltage line 1100 and can supply an initialization voltage VINT to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0061] The driving voltage line 1300 can be disposed on the substrate SUB and can extend in the third direction DR3 and the fourth direction DR4. The driving voltage line 1300 can be spaced apart from the initialization voltage line 1200 and the common voltage line 1100 and can supply a driving voltage ELVDD to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0062] The first lower electrode 1410 can be disposed on the substrate SUB and can be spaced apart from the driving voltage line 1300. In an embodiment of the present application, the first lower electrode 1410 can be electrically connected to the initialization voltage line 1200. For example, the first lower electrode 1410 can correspond to a second terminal of the storage capacitor included in the first sub-pixel SPX1. Figure 3 The storage capacitor C ST described in the first sub-pixel SPX1.

[0063] In addition, the second lower electrode 1420 can be spaced apart from the first lower electrode 1410 and can correspond to a second terminal of the storage capacitor included in the second sub-pixel SPX2. The third lower electrode 1430 can be spaced apart from the second lower electrode 1420 and the first lower electrode 1410 and can correspond to a second terminal of the storage capacitor included in the third sub-pixel SPX3. For example, the second lower electrode 1420 can be disposed between the first lower electrode 1410 and the third lower electrode 1430.

[0064] In addition, the first lower electrode 1410, the second lower electrode 1420, and the third lower electrode 1430 can have substantially the same planar profile (e.g., shape) as each other. The planar profile of each of the first lower electrode 1410, the second lower electrode 1420, and the third lower electrode 1430 will be described in more detail later with reference to Figure 13

[0065] The first data line 1510 can be disposed on the substrate SUB and can extend in the third direction DR3 and the fourth direction DR4. The first data line 1510 can supply a data voltage DATA to the second sub-pixel SPX2.

[0066] In addition, the second data line 1520 can be spaced apart from the first data line 1510 and can supply a data voltage DATA to the first sub-pixel SPX1. The third data line 1530 can be spaced apart from the second data line 1520 and can supply a data voltage DATA to the third sub-pixel SPX3.

[0067] However, the connection relationship between the first data line 1510, the second data line 1520, and the third data line 1530 and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is not limited thereto. The connection relationship between the first data line 1510, the second data line 1520, and the third data line 1530 and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be appropriately set as needed.

[0068] ​In an embodiment of the present utility model, the first conductive pattern 1000 can be formed of metal, alloy, conductive metal oxide, or transparent conductive material, etc. For example, the first conductive pattern 1000 can include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In addition, the first conductive pattern 1000 can be composed of a single layer or multiple layers.

[0069] Reference Figure 2 , Figure 4 , Figure 5 and Figure 6 The buffer layer BFR can be disposed on the first conductive pattern 1000 and cover the first conductive pattern 1000. The buffer layer BFR can prevent metal atoms or impurities from diffusing into the semiconductor pattern 2000 from the substrate SUB. In addition, the buffer layer BFR can control the heat supply rate during a crystallization process for forming the semiconductor pattern 2000.

[0070] The semiconductor pattern 2000 can be disposed on the buffer layer BFR and include a first active pattern 2110, a second active pattern 2120, a third active pattern 2130, a fourth active pattern 2210, a fifth active pattern 2220, a sixth active pattern 2230, a seventh active pattern 2310, an eighth active pattern 2320, and a ninth active pattern 2330.

[0071] In an embodiment of the present utility model, the first active pattern 2110, the second active pattern 2120, the third active pattern 2130, the fourth active pattern 2210, the fifth active pattern 2220, the sixth active pattern 2230, the seventh active pattern 2310, the eighth active pattern 2320, and the ninth active pattern 2330 can be spaced apart from each other.

[0072] The first active pattern 2110, the second active pattern 2120, and the third active pattern 2130 can be arranged along a third direction DR3 (or a fourth direction DR4) and can overlap the first lower electrode 1410, the second lower electrode 1420, and the third lower electrode 1430, respectively.

[0073] In an embodiment of the present utility model, the first active pattern 2110 can be electrically connected to the driving voltage line 1300 and transmit a driving voltage ELVDD to the first sub-pixel SPX1. For example, the first active pattern 2110 can correspond to a first terminal and a second terminal of a first transistor T1 included in the first sub-pixel SPX1.

[0074] In addition, the second active pattern 2120 can be electrically connected to the driving voltage line 1300 and transmit the driving voltage ELVDD to the second sub-pixel SPX2. The third active pattern 2130 can be electrically connected to the driving voltage line 1300 and transmit the driving voltage ELVDD to the third sub-pixel SPX3.

[0075] The fourth active pattern 2210, the fifth active pattern 2220, and the sixth active pattern 2230 can be arranged along the third direction DR3 (or the fourth direction DR4).

[0076] In an embodiment of the present application, the fourth active pattern 2210 can be electrically connected to the second data line 1520 and transmit the data voltage DATA to the first sub-pixel SPX1. For example, the fourth active pattern 2210 can correspond to the first terminal and the second terminal of the second transistor T2 included in the first sub-pixel SPX1.

[0077] In addition, the fifth active pattern 2220 can be electrically connected to the first data line 1510 and transmit the data voltage DATA to the second sub-pixel SPX2. The sixth active pattern 2230 can be electrically connected to the third data line 1530 and transmit the data voltage DATA to the third sub-pixel SPX3.

[0078] The seventh active pattern 2310, the eighth active pattern 2320, and the ninth active pattern 2330 can be arranged along the third direction DR3 (or the fourth direction DR4) and can overlap the initialization voltage line 1200.

[0079] In an embodiment of the present application, the seventh active pattern 2310 can be electrically connected to the initialization voltage line 1200 and transmit the initialization voltage VINT to the first sub-pixel SPX1. For example, the seventh active pattern 2310 can correspond to the first terminal and the second terminal of the third transistor T3 included in the first sub-pixel SPX1.

[0080] In addition, the eighth active pattern 2320 can be electrically connected to the initialization voltage line 1200 and transmit the initialization voltage VINT to the second sub-pixel SPX2. The ninth active pattern 2330 can be electrically connected to the initialization voltage line 1200 and transmit the initialization voltage VINT to the third sub-pixel SPX3.

[0081] In an embodiment of the present utility model, the semiconductor pattern 2000 can be formed of a silicon semiconductor material or an oxide semiconductor material. Examples of the silicon semiconductor material that can be used as the semiconductor pattern 2000 can include amorphous silicon or polycrystalline silicon, etc. Examples of the oxide semiconductor material that can be used as the semiconductor pattern 2000 can include IGZO (InGaZnO) or ITZO (InSnZnO), etc. These can be used alone or in combination with each other.

[0082] Referring to Figure 2 , Figure 5 , Figure 7 and Figure 8 , a gate insulating layer GI can be disposed on the semiconductor pattern 2000 and cover the semiconductor pattern 2000. In an embodiment of the present utility model, the gate insulating layer GI can be formed of an insulating material. Examples of the insulating material that can be used as the gate insulating layer GI can include silicon oxide, silicon nitride, or silicon oxynitride, etc. These can be used alone or in combination with each other.

[0083] The second conductive pattern 3000 can be disposed on the gate insulating layer GI and include a first double pattern 3100, a first gate line 3200, a second double pattern 3310, a third double pattern 3320, a fourth double pattern 3330, a first gate electrode 3410, a second gate electrode 3420, a third gate electrode 3430, and a second gate line (or gate line) 3500.

[0084] The first double pattern 3100 can overlap the common voltage line 1100 and can extend in a third direction DR3 (or a fourth direction DR4). The first double pattern 3100 can be electrically connected to the common voltage line 1100. The first double pattern 3100 can reduce the resistance of the common voltage line 1100. Accordingly, a voltage drop of the common voltage ELVSS can be prevented.

[0085] The first gate line 3200 can extend in the third direction DR3 (or the fourth direction DR4) and overlap the seventh active pattern 2310, the eighth active pattern 2320, and the ninth active pattern 2330. The first gate line 3200 can supply the second scan signal SS to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0086] The second double pattern 3310, the third double pattern 3320, and the fourth double pattern 3330 can be arranged in the third direction DR3 (or the fourth direction DR4) and overlap the driving voltage line 1300. The second double pattern 3310, the third double pattern 3320, and the fourth double pattern 3330 can be electrically connected to the driving voltage line 1300 and reduce the resistance of the driving voltage line 1300. Accordingly, a voltage drop of the driving voltage ELVDD can be prevented.

[0087] The first gate electrode 3410, the second gate electrode 3420, and the third gate electrode 3430 can be arranged in the third direction DR3 (or the fourth direction DR4).

[0088] In an embodiment of the present application, the first gate electrode 3410 can be electrically connected to the fourth active pattern 2210 and overlap the first active pattern 2110. Accordingly, the first gate electrode 3410 can correspond to a gate terminal of the first transistor T1 included in the first sub-pixel SPX1.

[0089] Further, the second gate electrode 3420 can be electrically connected to the fifth active pattern 2220 and overlap the second active pattern 2120. The third gate electrode 3430 can be electrically connected to the sixth active pattern 2230 and overlap the third active pattern 2130.

[0090] The first gate electrode 3410 can include a first body portion 3412 and a first protruding portion 3414. In a plan view, the first body portion 3412 can overlap the first active pattern 2110. For example, the first gate electrode 3410 (e.g., the first body portion 3412) can correspond to a gate terminal of the first transistor T1 included in the first sub-pixel SPX1. Further, in a plan view, the first body portion 3412 can overlap the first lower electrode 1410. For example, the first gate electrode 3410 (e.g., the first body portion 3412) can correspond to a first terminal of the storage capacitor C ST included in the first sub-pixel SPX1.

[0091] The first protruding portion 3414 can protrude from the first body portion 3412 in the first direction DR1. For example, the first protruding portion 3414 can protrude from the first body portion 3412 toward the fourth active pattern 2210.

[0092] In an embodiment of the present application, the first protruding portion 3414 can be completely spaced apart from the first lower electrode 1410 in a plan view. For example, the first lower electrode 1410 can have a shape that does not overlap the first protruding portion 3414 in a plan view. This will be described in more detail later with reference to FIGS. 13 and 14. Figure 13

[0093] Further, the first body portion 3412 and the first protruding portion 3414 can be integrated with each other. For example, the first body portion 3412 and the first protruding portion 3414 can be a single body. For example, the first body portion 3412 and the first protruding portion 3414 can be integrally formed and connected to each other without an interface therebetween.

[0094] ​The second gate electrode 3420 can include a second body portion 3422 and a second protruding portion 3424. The second body portion 3422 can overlap the second active pattern 2120 in a plan view. For example, the second gate electrode 3420 (e.g., the second body portion 3422) can correspond to a gate terminal of a first transistor included in the second sub-pixel SPX2. Also, the second body portion 3422 can overlap the second lower electrode 1420 in a plan view. For example, the second gate electrode 3420 (e.g., the second body portion 3422) can correspond to a first terminal of a storage capacitor included in the second sub-pixel SPX2.

[0095] The second protruding portion 3424 can protrude from the second body portion 3422 in the first direction DR1. For example, the second protruding portion 3424 can protrude from the second body portion 3422 toward the fifth active pattern 2220. In an embodiment of the present disclosure, the second protruding portion 3424 can be completely spaced apart from the second lower electrode 1420 in a plan view. For example, the second lower electrode 1420 can have a shape that does not overlap the second protruding portion 3424 in a plan view.

[0096] Also, the second body portion 3422 and the second protruding portion 3424 can be integrated with each other. For example, the second body portion 3422 and the second protruding portion 3424 can be a single body. For example, the second body portion 3422 and the second protruding portion 3424 can be integrally formed and connected to each other without an interface therebetween.

[0097] The third gate electrode 3430 can include a third body portion 3432 and a third protruding portion 3434. The third body portion 3432 can overlap the third active pattern 2130 in a plan view. For example, the third gate electrode 3430 (e.g., the third body portion 3432) can correspond to a gate terminal of a first transistor included in the third sub-pixel SPX3. Also, the third body portion 3432 can overlap the third lower electrode 1430 in a plan view. For example, the third gate electrode 3430 (e.g., the third body portion 3432) can correspond to a first terminal of a storage capacitor included in the third sub-pixel SPX3.

[0098] The third protruding portion 3434 can protrude from the third body portion 3432 in the first direction DR1. For example, the third protruding portion 3434 can protrude from the third body portion 3432 toward the sixth active pattern 2230. In an embodiment of the present disclosure, the third protruding portion 3434 can be completely spaced apart from the third lower electrode 1430 in a plan view. For example, the third lower electrode 1430 can have a shape that does not overlap the third protruding portion 3434 in a plan view.

[0099] Further, the first, second, and third gate electrodes 3410, 3420, and 3430 can have substantially the same planar profile (shape) as each other. For example, the first, second, and third body portions 3412, 3422, and 3432 can have substantially the same planar profile as each other, and the first, second, and third protruding portions 3414, 3424, and 3434 can have substantially the same planar profile as each other. Later, the planar profile of each of the first, second, and third gate electrodes 3410, 3420, and 3430 will be described in more detail with reference to FIGS. 34A and 34B. Figure 13 The planar profile of each of the first, second, and third gate electrodes 3410, 3420, and 3430 will be described in more detail.

[0100] The gate line 3500 can extend in the third direction DR3 (or the fourth direction DR4) and overlap the fourth, fifth, and sixth active patterns 2210, 2220, and 2230. The gate line 3500 can provide a first scan signal SC to the first, second, and third sub-pixels SPX1, SPX2, and SPX3. For example, the gate line 3500 can correspond to the gate line 350 of FIG. 35. Figure 3 The gate terminal of the second transistor T2 described above.

[0101] The second conductive pattern 3000 can be formed of a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc. For example, the second conductive pattern 3000 can include silver (Ag), an alloy including silver, molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. Further, the second conductive pattern 3000 can consist of a single layer or multiple layers.

[0102] Referring to Figure 2 , Figure 7 , Figure 9 and Figure 10 The interlayer insulating layer ILD can be disposed on and cover the second conductive pattern 3000. In an embodiment of the present application, the interlayer insulating layer ILD can be formed of an insulating material. For example, the interlayer insulating layer ILD can include silicon oxide, silicon nitride, or silicon oxynitride, etc. These can be used alone or in combination with each other. Further, the interlayer insulating layer ILD can consist of a single layer or multiple layers.

[0103] The third conductive pattern 4000 can be disposed on the interlayer insulating layer ILD, and include a gate connection line 4100, a common voltage contact pattern 4200, an initialization voltage contact pattern 4300, a first driving voltage contact pattern 4410, a second driving voltage contact pattern 4420, a third driving voltage contact pattern 4430, a first connection pattern 4510, a second connection pattern 4520, a third connection pattern 4530, a fourth connection pattern 4610, a fifth connection pattern 4620, a sixth connection pattern 4630, a seventh connection pattern 4710, an eighth connection pattern 4720, and a ninth connection pattern 4730.

[0104] The gate connection line 4100 can extend in the first direction DR1 (or the second direction DR2). The gate connection line 4100 can contact the gate line 3500 through at least one contact hole. The gate connection line 4100 can transmit a first scan signal SC to the gate line 3500.

[0105] The common voltage contact pattern 4200 can overlap the common voltage line 1100 and the first double pattern 3100, and extend in the third direction DR3 (or the fourth direction DR4). The common voltage contact pattern 4200 can be connected to the common voltage line 1100 and the first double pattern 3100 through at least one contact hole.

[0106] The initialization voltage contact pattern 4300 can overlap the initialization voltage line 1200, and can extend in the third direction DR3 (or the fourth direction DR4). The initialization voltage contact pattern 4300 can be connected to the initialization voltage line 1200, the seventh active pattern 2310, the eighth active pattern 2320, and the ninth active pattern 2330 through at least one contact hole. The initialization voltage contact pattern 4300 can transmit an initialization voltage VINT from the initialization voltage line 1200 to the seventh active pattern 2310, the eighth active pattern 2320, and the ninth active pattern 2330.

[0107] The first driving voltage contact pattern 4410, the second driving voltage contact pattern 4420, and the third driving voltage contact pattern 4430 can be arranged in the third direction DR3 (or in the fourth direction DR4).

[0108] The first driving voltage contact pattern 4410 can be connected to the driving voltage line 1300, the first active pattern 2110, and the second double pattern 3310 through at least one contact hole. The first driving voltage contact pattern 4410 can transmit a driving voltage ELVDD from the driving voltage line 1300 to the first active pattern 2110.

[0109] The second driving voltage contact pattern 4420 can be connected to the driving voltage line 1300, the second active pattern 2120, and the third dual pattern 3320 by at least one contact hole. The second driving voltage contact pattern 4420 can transmit the driving voltage ELVDD from the driving voltage line 1300 to the second active pattern 2120.

[0110] The third driving voltage contact pattern 4430 can be connected to the driving voltage line 1300, the third active pattern 2130, and the fourth dual pattern 3330 by at least one contact hole. The third driving voltage contact pattern 4430 can transmit the driving voltage ELVDD from the driving voltage line 1300 to the third active pattern 2130.

[0111] The first connection pattern 4510, the second connection pattern 4520, and the third connection pattern 4530 can be disposed in the third direction DR3 (or the fourth direction DR4).

[0112] The first connection pattern 4510 can be connected to the first lower electrode 1410, the seventh active pattern 2310, and the first active pattern 2110 by at least one contact hole. The first connection pattern 4510 can transmit the initialization voltage VINT from the seventh active pattern 2310 to the first lower electrode 1410.

[0113] The second connection pattern 4520 can be connected to the second lower electrode 1420, the eighth active pattern 2320, and the second active pattern 2120 by at least one contact hole. The second connection pattern 4520 can transmit the initialization voltage VINT from the eighth active pattern 2320 to the second lower electrode 1420.

[0114] The third connection pattern 4530 can be connected to the third lower electrode 1430, the ninth active pattern 2330, and the third active pattern 2130 by at least one contact hole. The third connection pattern 4530 can transmit the initialization voltage VINT from the ninth active pattern 2330 to the third lower electrode 1430.

[0115] The first connection pattern 4510 can overlap at least a portion of the first protruding portion 3414 of the first gate electrode 3410 in a plan view. For example, the first connection pattern 4510 can cover at least a portion of the first protruding portion 3414 of the first gate electrode 3410 in a plan view. In an embodiment of the present application, a portion of the first connection pattern 4510 overlapping the first protruding portion 3414 can be spaced apart from the first lower electrode 1410 in a plan view. For example, since the first lower electrode 1410 has a shape spaced apart from the first protruding portion 3414 entirely in a plan view, the portion of the first connection pattern 4510 overlapping the first protruding portion 3414 can be spaced apart from the first lower electrode 1410 in a plan view. This will be described later with reference to FIGS. 19A and 19B.Figure 13 A more detailed description will be given.

[0116] In addition, the first connection pattern 4510 can be spaced apart from at least a portion of the first protruding portion 3414 of the first gate electrode 3410. For example, the first connection pattern 4510 can partially overlap the first protruding portion 3414. However, the present application is not necessarily limited thereto.

[0117] In addition, the second connection pattern 4520 can overlap at least a portion of the second protruding portion 3424 of the second gate electrode 3420 in a plan view. In addition, the third connection pattern 4530 can overlap at least a portion of the third protruding portion 3434 of the third gate electrode 3430 in a plan view.

[0118] In addition, the first connection pattern 4510, the second connection pattern 4520, and the third connection pattern 4530 can have substantially the same planar profile (shape) as each other. A more detailed description of the planar profile of each of the first connection pattern 4510, the second connection pattern 4520, and the third connection pattern 4530 will be given later with reference to FIGS. 5A and 5B. Figure 13 A more detailed description will be given of the planar profile of each of the first connection pattern 4510, the second connection pattern 4520, and the third connection pattern 4530.

[0119] The fourth connection pattern 4610, the fifth connection pattern 4620, and the sixth connection pattern 4630 can be arranged in the third direction DR3 (or the fourth direction DR4).

[0120] The fourth connection pattern 4610 can overlap the fourth active pattern 2210 and the first gate electrode 3410. In addition, the fourth connection pattern 4610 can be connected to the fourth active pattern 2210 and the first gate electrode 3410 through at least one contact hole. For example, the fourth connection pattern 4610 can overlap and contact the fourth active pattern 2210 and the first protruding portion 3414. For example, the fourth connection pattern 4610 can connect the fourth active pattern 2210 and the first gate electrode 3410 to each other. Accordingly, the fourth connection pattern 4610 can transmit the data voltage DATA from the fourth active pattern 2210 to the first gate electrode 3410.

[0121] The fifth connection pattern 4620 can overlap the fifth active pattern 2220 and the second gate electrode 3420. Also, the fifth connection pattern 4620 can be connected to the fifth active pattern 2220 and the second gate electrode 3420 through at least one contact hole. For example, the fifth connection pattern 4620 can overlap and contact the fifth active pattern 2220 and the second protruding portion 3424. For example, the fifth connection pattern 4620 can connect the fifth active pattern 2220 and the second gate electrode 3420 to each other. Accordingly, the fifth connection pattern 4620 can transmit the data voltage DATA from the fifth active pattern 2220 to the second gate electrode 3420.

[0122] The sixth connection pattern 4630 can overlap the sixth active pattern 2230 and the third gate electrode 3430. Also, the sixth connection pattern 4630 can be connected to the sixth active pattern 2230 and the third gate electrode 3430 through at least one contact hole. For example, the sixth connection pattern 4630 can overlap and contact the sixth active pattern 2230 and the third protruding portion 3434. For example, the sixth connection pattern 4630 can connect the sixth active pattern 2230 and the third gate electrode 3430 to each other. Accordingly, the sixth connection pattern 4630 can transmit the data voltage DATA from the sixth active pattern 2230 to the third gate electrode 3430.

[0123] The seventh connection pattern 4710, the eighth connection pattern 4720, and the ninth connection pattern 4730 can be disposed in the third direction DR3 (or the fourth direction DR4).

[0124] The seventh connection pattern 4710 can be connected to the second data line 1520 and the fourth active pattern 2210 through at least one contact hole. For example, the seventh connection pattern 4710 can connect the second data line 1520 and the fourth active pattern 2210 to each other. Accordingly, the seventh connection pattern 4710 can transmit the data voltage DATA from the second data line 1520 to the fourth active pattern 2210.

[0125] The eighth connection pattern 4720 can be connected to the first data line 1510 and the fifth active pattern 2220 through at least one contact hole. For example, the eighth connection pattern 4720 can connect the first data line 1510 and the fifth active pattern 2220 to each other. Accordingly, the eighth connection pattern 4720 can transmit the data voltage DATA from the first data line 1510 to the fifth active pattern 2220.

[0126] The ninth connection pattern 4730 can be connected to the third data line 1530 and the sixth active pattern 2230 through at least one contact hole. For example, the ninth connection pattern 4730 can connect the third data line 1530 and the sixth active pattern 2230 to each other. Accordingly, the ninth connection pattern 4730 can transmit the data voltage DATA from the third data line 1530 to the sixth active pattern 2230.

[0127] The third conductive pattern 4000 can be formed of a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc. For example, the third conductive pattern 4000 can include silver (Ag), an alloy including silver, molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. Also, the third conductive pattern 4000 can be composed of a single layer or multiple layers.

[0128] Referring to Figure 2 , Figure 9 , Figure 11 and Figure 12 , a via insulation layer VIA can be disposed on the third conductive pattern 4000 and cover the third conductive pattern 4000. The via insulation layer VIA can be formed of an insulating material. For example, the via insulation layer VIA can include a photoresist, a polyacrylic resin, a polyimide resin, or an acrylic resin, etc.

[0129] The fourth conductive pattern 5000 can be disposed on the via insulation layer VIA and can include a first pixel electrode 5100, a second pixel electrode 5200, and a third pixel electrode 5300.

[0130] The first pixel electrode 5100 can be connected to the first connection pattern 4510 through at least one contact hole. The first pixel electrode 5100 can receive the initialization voltage VINT or the driving current through the first connection pattern 4510. The second pixel electrode 5200 can be connected to the second connection pattern 4520 through at least one contact hole. The second pixel electrode 5200 can receive the initialization voltage VINT or the driving current through the second connection pattern 4520. The third pixel electrode 5300 can be connected to the third connection pattern 4530 through at least one contact hole. The third pixel electrode 5300 can receive the initialization voltage VINT or the driving current through the third connection pattern 4530.

[0131] Figure 13 is an enlarged view of the area A of Figure 10 , and Figure 14 is alongFigure 13 a cross-sectional view taken along line I-I' of FIG. 1.

[0132] In Figure 13 , for ease of description, a third conductive pattern 4000 and components under an interlayer insulating layer ILD are also illustrated, and a contact hole is omitted.

[0133] Referring to Figure 10 , Figure 13 and Figure 14 , the first lower electrode 1410 can have a first side edge 1410-S adjacent to the end 3414-E of the first protruding portion 3414 of the first gate electrode 3410 in the second direction DR2. The first side edge 1410-S can be one of several side edges that define a planar profile (shape) of the first lower electrode 1410.

[0134] The first side edge 1410-S can be recessed toward an interior of the first lower electrode 1410 than other side edges of the first lower electrode 1410. For example, the first side edge 1410-S can be recessed with respect to other side edges of the first lower electrode 1410 that face the first direction DR1. For example, the first lower electrode 1410 can have a planar profile (shape) in which a portion corresponding to the first protruding portion 3414 is partially recessed, and thus, the first side edge 1410-S can be defined.

[0135] The first side edge 1410-S of the first lower electrode 1410 can overlap the first connection pattern 4510 in a plan view, and can be covered by the first connection pattern 4510.

[0136] For example, the first connection pattern 4510 can have a second side edge 4510-S adjacent to the end 3414-E of the first protruding portion 3414 in the second direction DR2, and the second side edge 4510-S can be closer to the end 3414-E of the first protruding portion 3414 than the first side edge 1410-S of the first lower electrode 1410. The second side edge 4510-S can be one of several side edges that define a planar profile (shape) of the first connection pattern 4510.

[0137] For example, the first lower electrode 1410 can have a planar profile (shape) in which a portion corresponding to the first protruding portion 3414 is partially recessed, and thus, the first side edge 1410-S can be defined at a position farther from the end 3414-E of the first protruding portion 3414 in the second direction DR2 than the second side edge 4510-S.

[0138] For example, the second side 4510-S of the first connection pattern 4510 can be spaced apart from the first side 1410-S of the first lower electrode 1410 in the first direction DR1. For example, a shortest distance L1 from the end 3414-E of the first protrusion 3414 to the first side 1410-S of the first lower electrode 1410 in the second direction DR2 can be greater than a shortest distance L2 from the end 3414-E of the first protrusion 3414 to the second side 4510-S of the first connection pattern 4510 in the second direction DR2. As a result, in a plan view, the first side 1410-S, the second side 4510-S, and the end 3414-E of the first protrusion 3414 can be sequentially arranged in the first direction DR1.

[0139] In an embodiment of the present application, the first side 1410-S of the first lower electrode 1410 can overlap the first main portion 3412 of the first gate electrode 3410 in a plan view, and can be covered by the first main portion 3412. For example, the first lower electrode 1410 can have a planar profile (shape) in which a portion corresponding to the first protrusion 3414 is partially recessed, so as to be completely spaced apart from the first protrusion 3414 in a plan view. Accordingly, the first side 1410-S can overlap the first main portion 3412, and be covered by the first main portion 3412.

[0140] As Figure 14 As illustrated in FIG. 1, the upper surface 3410-U of the first gate electrode 3410 can have a first step ST1 due to the first lower electrode 1410. For example, the upper surface of the buffer layer BFR and the upper surface of the gate insulating layer GI can have a step due to the first side 1410-S of the first lower electrode 1410, and accordingly, the upper surface 3410-U of the first gate electrode 3410 can have the first step ST1.

[0141] In an embodiment of the present application, the first step ST1 can be defined in the first main portion 3412 of the first gate electrode 3410. For example, since the first side 1410-S of the first lower electrode 1410 overlaps the first main portion 3412, the first step ST1 formed by the first side 1410-S can be defined in the first main portion 3412 of the first gate electrode 3410.

[0142] The upper surface ILD-U of the interlayer insulating layer ILD can have a second step ST2 due to the first step ST1. Further, the upper surface 4510-U of the first connection pattern 4510 can have a third step ST3 due to the second step ST2. For example, the first step ST1, the second step ST2, and the third step ST3 can be sequentially defined by the first side 1410-S of the first lower electrode 1410.

[0143] The first connection pattern 4510 can cover a portion of the interlayer insulating layer ILD in which the second step ST2 is defined. For example, the first connection pattern 4510 can be formed such that a second side edge 4510-S is closer to the end portion 3414-E of the first protruding portion 3414 than a first side edge 1410-S of the first lower electrode 1410. Accordingly, the first connection pattern 4510 can cover a portion of the interlayer insulating layer ILD in which the second step ST2 is defined due to the first side edge 1410-S. For example, the first connection pattern 4510 can cover a portion of the interlayer insulating layer ILD in which the second step ST2 is defined and a portion adjacent to the portion in which the second step ST2 is defined.

[0144] A void or a crack can occur in a portion of the interlayer insulating layer ILD in which the second step ST2 is defined, and when impurities, moisture, or oxygen, etc. flow through the void or the crack, deterioration of the display device DD can occur. For example, an etching material used in a process after the interlayer insulating layer ILD is formed can flow through the void or the crack, and accordingly, the reliability of the display device DD can be deteriorated due to deterioration of the interlayer insulating layer ILD or a component under the interlayer insulating layer ILD.

[0145] According to an embodiment of the present application, the first lower electrode 1410 can have a planar profile (shape) in which a portion corresponding to the first protruding portion 3414 is partially recessed, and accordingly, has the first side edge 1410-S. Further, the first connection pattern 4510 can cover the first side edge 1410-S. For example, the first connection pattern 4510 can have a second side edge 4510-S closer to the end portion 3414-E of the first protruding portion 3414 than the first side edge 1410-S of the first lower electrode 1410.

[0146] Accordingly, the first connection pattern 4510 can cover a portion of the interlayer insulating layer ILD in which the second step ST2 is defined due to the first side edge 1410-S. Accordingly, inflow of impurities, moisture, or oxygen, etc. through the portion of the interlayer insulating layer ILD in which the second step ST2 is defined can be reduced or prevented. Accordingly, deterioration of the interlayer insulating layer ILD or a component under the interlayer insulating layer ILD can be prevented. Accordingly, the reliability of the display device DD can be improved.

[0147] Meanwhile, Figure 4 and Figure 13The planar profile (shape) of the first lower electrode 1410 illustrated in FIG. 13 is merely an example, and the present application is not necessarily limited thereto. For example, the planar profile of the first lower electrode 1410 can be modified in various ways as needed, as long as the first lower electrode 1410 has the first side edge 1410-S because the portion of the first lower electrode 1410 corresponding to the first protruding portion 3414 is partially recessed.

[0148] Furthermore, as described above, the planar profile (shape) of each of the second lower electrode 1420 and the third lower electrode 1430 can be substantially the same as the planar profile of the first lower electrode 1410. The planar profile of each of the second gate electrode 3420 and the third gate electrode 3430 can be substantially the same as the planar profile of the first gate electrode 3410, and the planar profile of each of the second connection pattern 4520 and the third connection pattern 4530 can be substantially the same as the planar profile of the first connection pattern 4510. Therefore, the description of the planar profile of each of the second lower electrode 1420, the third lower electrode 1430, the second gate electrode 3420, the third gate electrode 3430, the second connection pattern 4520, and the third connection pattern 4530 will be omitted. Figure 13 and Figure 14 The relationship between the first lower electrode 1410, the first gate electrode 3410, and the first connection pattern 4510 described above can be equally applied throughout the specification. Therefore, the redundant description is omitted.

[0149] Figure 15 is a cross-sectional view of a display device illustrated in Figure 1

[0150] Referring to Figure 15 , the display device DD can include a substrate SUB, a first lower electrode 1410, a second lower electrode 1420, and a third lower electrode 1430, a first active pattern 2110, a second active pattern 2120, and a third active pattern 2130, a first gate electrode 3410, a second gate electrode 3420, and a third gate electrode 3430, a first connection pattern 4510, a second connection pattern 4520, and a third connection pattern 4530, a first pixel electrode 5100, a second pixel electrode 5200, and a third pixel electrode 5300, a first light emitting layer 6100, a second light emitting layer 6200, a third light emitting layer 6300, a common electrode 7000, an encapsulation layer TFE, a bank layer BK, a first color conversion layer CVL1, a second color conversion layer CVL2, a third color conversion layer CVL3, a refractive layer LR, a light blocking layer BM, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a planarization layer OC. Hereinafter, the repeated description will be omitted.

[0151] A pixel definition layer PDL can be disposed on the via insulating layer VIA. The pixel definition layer PDL can be formed of an insulating material. For example, the pixel definition layer PDL can include a photoresist, a polyacrylic resin, a polyimide resin, or an acrylic resin, etc. These materials can be used alone or in combination with each other. ​

[0152] An opening to expose the first pixel electrode 5100, the second pixel electrode 5200, and the third pixel electrode 5300 can be formed in the pixel definition layer PDL.

[0153] The first light emitting layer 6100 can be disposed on the first pixel electrode 5100. The second light emitting layer 6200 can be disposed on the second pixel electrode 5200, and the third light emitting layer 6300 can be disposed on the third pixel electrode 5300. The first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300 can be formed of an organic material, and emit light of a preset color. For example, the first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300 can emit blue light. However, the present embodiment is not necessarily limited thereto. In addition, in the present embodiment, the first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300 can emit light of different colors. Figure 15 In the present embodiment, the first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300 are illustrated as not being connected, but the present embodiment is not necessarily limited thereto. For example, the first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300 can be formed to be continuously connected to each other.

[0154] The common electrode 7000 can be disposed on the first light emitting layer 6100, the second light emitting layer 6200, and the third light emitting layer 6300. The common electrode 7000 can be a plate electrode. In the present embodiment, the common voltage ELVSS can be supplied to the common electrode 7000. Figure 2

[0155] The first pixel electrode 5100, the first light emitting layer 6100, and the common electrode 7000 can form a first light emitting element ED1. For example, the first light emitting element ED1 can correspond to a light emitting element LED of the present embodiment. In addition, the second pixel electrode 5200, the second light emitting layer 6200, and the common electrode 7000 can form a second light emitting element ED2. The third pixel electrode 5300, the third light emitting layer 6300, and the common electrode 7000 can form a third light emitting element ED3. Figure 3

[0156] The encapsulation layer TFE can be disposed on the common electrode 7000. The encapsulation layer TFE can be formed of an insulating material. For example, the encapsulation layer TFE can have a structure in which an inorganic layer and an organic layer are alternately stacked together. The encapsulation layer TFE can prevent foreign substances from penetrating into the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3.

[0157] The bank layer BK can be disposed on the encapsulation layer TFE. The bank layer BK can be formed of a light-blocking material, and can block light emitted from a lower portion. In addition, an opening to expose the encapsulation layer TFE can be formed in the bank layer BK.

[0158] ​​The first color conversion layer CVL1 can overlap the first light emitting layer 6100. In an embodiment of the present disclosure, the first color conversion layer CVL1 can convert a wavelength of light emitted from the first light emitting layer 6100. For example, the first color conversion layer CVL1 can include a phosphor, a scatterer, or a quantum dot, etc. In an embodiment of the present disclosure, when light emitted from the first light emitting layer 6100 passes through the first color conversion layer CVL1, green light can be emitted.

[0159] The second color conversion layer CVL2 can overlap the second light emitting layer 6200. In an embodiment of the present disclosure, the second color conversion layer CVL2 can convert a wavelength of light emitted from the second light emitting layer 6200. For example, the second color conversion layer CVL2 can include a phosphor, a scatterer, or a quantum dot, etc. In an embodiment of the present disclosure, when light emitted from the second light emitting layer 6200 passes through the second color conversion layer CVL2, red light can be emitted.

[0160] The third color conversion layer CVL3 can overlap the third light emitting layer 6300. In an embodiment of the present disclosure, the third color conversion layer CVL3 can scatter a wavelength of light emitted from the third light emitting layer 6300. For example, the third color conversion layer CVL3 can include a transparent polymer material or a scatterer, etc. In an embodiment of the present disclosure, when light emitted from the third light emitting layer 6300 passes through the third color conversion layer CVL3, blue light can be emitted.

[0161] In an embodiment of the present disclosure, the refractive layer LR can be disposed on the first color conversion layer CVL1, the second color conversion layer CVL2, and the third color conversion layer CVL3. The refractive layer LR can have a predetermined refractive index different from a refractive index of an adjacent layer. Accordingly, light efficiency of the display device DD can be improved. Further, in an embodiment of the present disclosure, the refractive layer LR can be disposed under the first color conversion layer CVL1, the second color conversion layer CVL2, and the third color conversion layer CVL3. Further, in an embodiment of the present disclosure, the refractive layer LR can include a first refractive layer and a second refractive layer, and the first refractive layer can be disposed on the first color conversion layer CVL1, the second color conversion layer CVL2, and the third color conversion layer CVL3, and the second refractive layer can be disposed under the first color conversion layer CVL1, the second color conversion layer CVL2, and the third color conversion layer CVL3.

[0162] The black matrix BM can be disposed on the refractive layer LR. The black matrix BM can be formed of a light-blocking material, and can block light emitted from a lower portion. Further, an opening exposing the refractive layer LR can be formed in the black matrix BM.

[0163] The first color filter CF1 can overlap the first color conversion layer CVL1. In an embodiment of the present application, the first color filter CF1 can transmit light of a wavelength corresponding to green light.

[0164] The second color filter CF2 can overlap the second color conversion layer CVL2. In an embodiment of the present application, the second color filter CF2 can transmit light of a wavelength corresponding to red light.

[0165] The third color filter CF3 can overlap the third color conversion layer CVL3. In an embodiment of the present application, the third color filter CF3 can transmit light of a wavelength corresponding to blue light.

[0166] The planarization layer OC can be provided on the first color filter CF1, the second color filter CF2, and the third color filter. The planarization layer OC can be formed of an organic material, and can provide a substantially planar upper surface.

[0167] Further, reference is made to Figure 15 The structure of the display device DD described can be changed in various ways depending on the embodiment, and is not necessarily limited thereto.

[0168] The present application can be applied to, for example, various display devices and electronic devices including the same. For example, the present application is applicable to various display devices such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet computers, car navigation systems, televisions, computer monitors, and laptop computers, and electronic devices including the same.

[0169] While the present application has been described with reference to embodiments thereof, it is to be understood that various other changes can be made and equivalents employed therein without departing from the scope of the application.

Claims

1. A display device comprising: a first active pattern provided over a substrate; a gate electrode provided over the first active pattern and including a main portion and a protruding portion, wherein the main portion overlaps the first active pattern in a plan view, and the protruding portion protrudes from the main portion in a first direction; a lower electrode provided below the first active pattern and having a first side edge adjacent to an end portion of the protruding portion in a second direction opposite to the first direction; and a first connection pattern provided over the gate electrode and in contact with the first active pattern, wherein the first connection pattern covers the first side edge of the lower electrode.

2. The display device according to claim 1, wherein in the plan view, the first connection pattern overlaps at least a portion of the protruding portion and is spaced apart from at least a portion of the protruding portion.

3. The display device according to claim 1, wherein an upper surface of the gate electrode has a first step due to the lower electrode, an upper surface of an insulating layer between the gate electrode and the first connection pattern has a second step due to the first step of the upper surface of the gate electrode, and an upper surface of the first connection pattern has a third step due to the second step of the upper surface of the insulating layer.

4. The display device according to claim 3, wherein the first connection pattern covers a portion of the insulating layer in which the second step is formed.

5. The display device according to claim 3, wherein the first step of the upper surface of the gate electrode is formed in the main portion of the gate electrode.

6. The display device according to claim 1, wherein the first connection pattern has a second side edge adjacent to the end portion of the protruding portion, and the second side edge is closer to the end portion of the protruding portion than the first side edge of the lower electrode.

7. The display device according to claim 6, wherein in the plan view, a shortest distance in the second direction from the end portion of the protruding portion to the first side edge of the lower electrode is greater than a shortest distance in the second direction from the end portion of the protruding portion to the second side edge of the first connection pattern.

8. The display device according to claim 6, wherein in the plan view, the second side edge of the first connection pattern is spaced apart from the first side edge of the lower electrode in the first direction.

9. The display device according to claim 1, wherein the lower electrode is spaced apart from the protruding portion in the plan view.

10. The display device according to any one of claims 1 to 9, further comprising: a first transistor and a second transistor electrically connected to each other; a second active pattern spaced apart from the first active pattern; and a gate line spaced apart from the gate electrode and provided over the second active pattern, wherein the first transistor includes at least a portion of the gate electrode and the first active pattern. ​ ​ The second transistor includes at least a part of the gate line and the second active pattern, and The protruding portion protrudes toward the second active pattern.

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