Acquisition circuit, chip, controller and vehicle

Abstract

The utility model discloses an acquisition circuit, chip, controller and vehicle relates to signal acquisition technical field, acquisition circuit includes acquisition module and a plurality of multiplexers, acquisition module includes analog-to-digital conversion interface, the output port of each multiplexer is connected with analog-to-digital conversion interface, and the analog-to-digital conversion interface is connected with the analog-to-digital conversion interface. And the input signal acquired by the multiplexer is sent to the acquisition module. As the output port of each multiplexer is connected with the analog-to-digital conversion interface of the acquisition module, the input signals acquired by the multiplexers are sent to the acquisition module, so that a plurality of input signals can be acquired, and other interfaces except the analog-to-digital conversion interface of the acquisition module do not need to be occupied too much; and the resource occupancy rate of the interface is reduced.

Description

Technical Field

[0001] This utility model belongs to the field of signal acquisition technology, specifically relating to an acquisition circuit, a chip, a controller, and a vehicle. Background Technology

[0002] In order to detect electronic and electrical faults in a vehicle in a timely manner, it is necessary to obtain the status of multiple circuits in the vehicle. This is usually done by obtaining the input signals of each circuit through the vehicle's controller and performing testing.

[0003] In related technologies, the controller includes a data acquisition chip. An input signal is obtained through an analog-to-digital conversion interface of the data acquisition chip. In order to obtain more input signals, other interfaces of the data acquisition chip, such as Inter-Integrated Circuit Interface (I2C), Universal Asynchronous Receiver / Transmitter (UART), and Serial Peripheral Interface (SPI), need to be used to acquire input signals, resulting in high resource utilization of the interfaces. Utility Model Content

[0004] This invention provides a data acquisition circuit, chip, controller, and vehicle, which at least solves the problem in related technologies that in order to obtain a greater number of input signals, it is necessary to occupy other interfaces such as I2C, UART, and SPI of the data acquisition chip to acquire input signals, resulting in high interface resource occupancy.

[0005] To solve the above-mentioned technical problems, this utility model is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a data acquisition circuit, comprising:

[0007] The acquisition module includes an analog-to-digital conversion interface;

[0008] Multiple multiplexers are provided, and the output port of each multiplexer is connected to the analog-to-digital converter interface to send the input signal acquired by the multiplexer to the acquisition module.

[0009] Optionally, the multiplexer includes a channel selection port and multiple input ports; the acquisition module further includes a first input / output port; the first input / output port is connected to the channel selection port of each multiplexer; used to select the input port connected to the output port of the multiplexer, so as to obtain the corresponding input signal through the analog-to-digital conversion interface.

[0010] Optionally, there are multiple first input / output ports; the channel selection port includes multiple acquisition selection terminals, and each acquisition selection terminal is connected to a corresponding first input / output port.

[0011] Optionally, the first input / output port is connected to the acquisition selection terminal corresponding to the first input / output port in each of the multiplexers.

[0012] Optionally, the multiplexer further includes multiple switching devices, one end of each switching device being connected to a corresponding input port, and the other end of each switching device being connected to the output port of the multiplexer.

[0013] Optionally, the acquisition module further includes a second input / output port; the second input / output port is connected to the enable terminal of the multiplexer.

[0014] Optionally, the multiplexer operates when the second input / output port is at a first level; the multiplexer stops operating when the second input / output port is at a second level; the second level is lower or higher than the first level.

[0015] Optionally, there are multiple second input / output ports, and each second input / output port is connected to the enable terminal of each multiplexer.

[0016] Optionally, at each moment, one of the second input / output ports is at a first level, and the other second input / output ports are at a second level; the second level is lower or higher than the first level.

[0017] Optionally, the acquisition module is used to acquire the input signals in turn according to the acquisition timing sequence.

[0018] Optionally, the acquisition module further includes a timer, which is used to increase the time according to a first preset time interval; when the time interval of the timer reaches a second preset time, the analog-to-digital conversion interface acquires one of the input signals.

[0019] Optionally, the acquisition module further includes a processor and a storage module; the storage module includes a volatile memory; the processor is connected to the timer, and the processor is used to cause the analog-to-digital conversion interface (11) to acquire an input signal and store it in the volatile memory when the time interval of the timer reaches the second preset time.

[0020] Optionally, the storage module further includes a non-volatile memory; the processor is also configured to, upon completion of acquisition of each of the input signals of the multiplexer, reset the timer to zero and transfer each input signal in the volatile memory to the non-volatile memory.

[0021] Optionally, the input signal is a voltage signal.

[0022] Optionally, the acquisition module further includes a storage module; the storage module is connected to the analog-to-digital conversion interface and is used to store the input signal.

[0023] Optionally, the storage module includes a volatile memory; the volatile memory is connected to the analog-to-digital conversion interface, and the volatile memory is used to store the input signal transmitted by the analog-to-digital conversion interface.

[0024] Optionally, the storage module includes a non-volatile memory; the non-volatile memory is connected to the volatile memory, and the non-volatile memory is used to store the input signal transmitted by the volatile memory.

[0025] Optionally, the volatile memory type includes random access memory; the non-volatile memory type includes read-only memory and / or flash memory.

[0026] Optionally, the acquisition module is adapted to be connected to the processing module so that the processing module can acquire the input signal through the acquisition module.

[0027] Optionally, the processing module is used to generate alarm information when the input signal is abnormal.

[0028] Optionally, the processing module is a system-on-a-chip, a microcontroller unit, and / or a field-programmable gate array.

[0029] Optionally, the acquisition module may include a microcontroller, a system-on-a-chip, and / or a single-chip microcomputer.

[0030] Secondly, this utility model embodiment also provides a chip, including the acquisition circuit as described in the first aspect.

[0031] Thirdly, embodiments of the present invention also provide a controller, including the acquisition circuit as described in the first aspect, or including the chip as described in the second aspect.

[0032] Optionally, the controller further includes a processing module; the analog-to-digital conversion interface of the acquisition module is used to acquire the input signal; the processing module is connected to the acquisition module, and the processing module is used to acquire the input signal through the acquisition module.

[0033] Optionally, the processing module is also configured to generate alarm information in the event of an abnormal input signal.

[0034] Optionally, the controller is a domain controller.

[0035] Fourthly, embodiments of the present invention also provide a vehicle, including the acquisition circuit as described in the first aspect, or the chip as described in the second aspect, or the controller as described in the third aspect.

[0036] In this embodiment of the invention, since the output port of each multiplexer is connected to the analog-to-digital conversion interface of the acquisition module, multiple input signals can be acquired by sending the input signals acquired by the multiplexer to the acquisition module, without occupying too many interfaces other than the analog-to-digital conversion interface of the acquisition module, thus reducing the resource occupancy rate of the interfaces. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a data acquisition circuit provided in an embodiment of this utility model;

[0039] Figure 2 This is a schematic diagram of another acquisition circuit provided in an embodiment of the present utility model;

[0040] Figure 3 This is a schematic diagram of the input signal acquisition process provided in an embodiment of the present utility model.

[0041] Figure label:

[0042] 10 - Acquisition module; 11 - Analog-to-digital converter interface; 12 - Processor; 13 - Storage module; 131 - Volatile memory; 132 - Non-volatile memory; 14 - Timer; 101a, 101b - Second input / output ports; 102a, 102b, 102c - First input / output ports; 20a, 20b - Multiplexers; 21a, 21b - Channel selection ports; 201a, 201b, 201c, 201d, 201e, 201f, 201h, 201i, 201j, 201k, 201n, 201p, 201q, 20 1x, 201y - Input ports; 202a, 202b - Output ports of the multiplexer; 203a, 203b - Enable terminals of the multiplexer; 204a, 204b, 204c, 204d, 204e, 204f - Acquisition selection terminals; 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316 - Loops; S1a, S1b, S1c, S1d, S1e, S1f, S1g, S1h - Switching devices; 40 - Processing module. Detailed Implementation

[0043] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Reference Figure 1 This utility model embodiment provides a data acquisition circuit, including: a data acquisition module 10, the data acquisition module 10 including an analog-to-digital conversion interface 11; and multiple multiplexers 20a and 20b, the output ports 202a and 202b of each multiplexer 20a and 20b being connected to the analog-to-digital conversion interface 11 to send the input signals acquired by the multiplexers 20a and 20b to the data acquisition module 10.

[0045] It should be noted that the acquisition module 10 includes a microcontroller unit (MCU), a single-chip microcomputer, a system-on-a-chip and / or other types of chips; multiplexers 20a and 20b are MUX (Multiplexer); and analog-to-digital converter interface 11 is ADC (Analog-to-digital converter) interface.

[0046] In some embodiments, the acquisition circuit includes: a plurality of multiplexers 20a and 20b, the multiplexers 20a and 20b being connected to at least one external circuit 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, and 316; and an acquisition module 10, the acquisition module 10 including an analog-to-digital conversion interface 11 and a plurality of second input / output ports 101a and 101b, the second input / output ports 101a and 101b being connected to the enable terminals 203a and 203b of the multiplexers 20a and 20b. One-to-one correspondence; the analog-to-digital conversion interface 11 is connected to the output ports 202a and 202b of each of the multiplexers 20a and 20b respectively, and the second input / output ports 101a and 101b are connected to the enable terminals 203a and 203b of the multiplexers corresponding to the second input / output ports 101a and 101b; wherein, the acquisition module 10 is used to select a target multiplexer from the multiple multiplexers 20a and 20b through the multiple second input / output ports 101a and 101b, and to acquire the input signal of the loop connected to the target multiplexer through the analog-to-digital conversion interface 11.

[0047] Each of the multiplexers 20a and 20b includes channel selection ports 21a and 21b and multiple input ports 201a, 201b, 201c, 201d, 201e, 201f, 201h, 201i, 201j, 201k, 201n, 201p, 201q, 201x, and 201y. The input ports 201a, 201b, 201c, 201d, 201e, 201f, 201h, 201i, 201j, 201k, 201n, 201p, 201q, 201x, and 201y are connected to external loops 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, and 302. 12, 313, 314, 315, and 316 correspond to each other; the input port is used to connect to the loop corresponding to the input port to obtain the input signal of the loop corresponding to the input port; the acquisition module 10 also includes first input / output ports 102a, 102b, and 102c; the first input / output ports 102a, 102b, and 102c are respectively connected to each of the channel selection ports 21a and 21b; the acquisition module 10 is also used to connect the target input port among the multiple input ports of the target multiplexer to the output port of the multiplexer through the first input / output ports, so as to obtain the input signal of the loop corresponding to the target input port through the analog-to-digital conversion interface 11.

[0048] In some embodiments, external circuits are circuits within the vehicle, such as power supply circuits for various domain controllers, communication chips, cameras, radars, antennas, etc., microcontrollers, and system-on-chips (SoCs).

[0049] In some embodiments, the second input / output port is a general-purpose input / output (GPIO) terminal of the acquisition module.

[0050] In some embodiments, the multiplexer operates when the second input / output port is at a first level; the multiplexer stops operating when the second input / output port is at a second level; the second level is lower or higher than the first level.

[0051] In some embodiments, the input signal may be a voltage signal.

[0052] In some embodiments, the acquisition module 10 is specifically used to acquire the input signals in turn according to the acquisition timing sequence.

[0053] In some embodiments, when the second input / output port outputs a low level, the multiplexer corresponding to the second input / output port is in the enabled state; when the second input / output port outputs a high level, the multiplexer corresponding to the second input / output port is in the disabled state.

[0054] In the event of a multiplexer failure, the second input / output port corresponding to the failed multiplexer will output a high level to shut down the failed multiplexer without affecting the operation of other multiplexers.

[0055] For example, the acquisition circuit includes an acquisition module 10 and two multiplexers 20a and 20b; each multiplexer includes a channel selection port and eight input ports, with the input ports corresponding to external loops; the acquisition module 10 includes an analog-to-digital conversion interface 11, a first input / output port, and two second input / output ports; the input ports are used to connect to the loops corresponding to the input ports; the analog-to-digital conversion interface 11 is connected to the output port of each multiplexer, the first input / output port is connected to each channel selection port, the first second input / output port 101a is connected to the enable terminal 203a of the first multiplexer 20a, and the second second input / output port 101b is connected to the enable terminal 203b of the second multiplexer 20b.

[0056] In some embodiments, when the second input / output port outputs a high level, the multiplexer corresponding to the second input / output port is in the enabled state; when the second input / output port outputs a low level, the multiplexer corresponding to the second input / output port is in the disabled state.

[0057] In the event of a multiplexer failure, the second input / output port corresponding to the failed multiplexer will output a low level to shut down the failed multiplexer without affecting the operation of other multiplexers.

[0058] In this embodiment of the invention, the acquisition module 10 selects a target multiplexer from multiple multiplexers through multiple second input / output ports, and connects the target input port among the multiple input ports of the target multiplexer to the output port of the multiplexer through the first input / output port, so as to obtain the input signal of the loop corresponding to the target input port through the analog-to-digital conversion interface 11. In this process, the analog-to-digital conversion interface 11 is expanded into multiple input ports through multiple multiplexers, which makes up for the insufficient number of analog-to-digital conversion interfaces 11. Each input signal is obtained by polling, so that the acquisition module 10 can support the acquisition of input signals of all loops.

[0059] In this embodiment of the invention, since the output port of each multiplexer is connected to the analog-to-digital conversion interface of the acquisition module 10, multiple input signals can be acquired by sending the input signals acquired by the multiplexer to the acquisition module 10, without occupying too many interfaces other than the analog-to-digital conversion interface of the acquisition module, thus reducing the resource occupancy rate of the interfaces.

[0060] Optionally, in some embodiments, there are multiple first input / output ports 102a, 102b, and 102c, and the channel selection port includes multiple acquisition selection terminals 204a, 204b, 204c, 204d, 204e, and 204f; in the channel selection port, each acquisition selection terminal is connected to a corresponding first input / output port. In the channel selection port, each acquisition selection terminal is connected to the first input / output port corresponding to that acquisition selection terminal; the first input / output port is connected to the acquisition selection terminal corresponding to the first input / output port in each multiplexer.

[0061] 101a, 101b - Second input / output ports; 102a, 102b, 102c - First input / output ports. For example, the acquisition circuit includes an acquisition module 10 and two multiplexers; each multiplexer includes a channel selection port and eight input ports, with the input ports corresponding to external loops; the acquisition module 10 includes an analog-to-digital converter interface 11, a first input / output port, and two second input / output ports; the number of first input / output ports is three, and the channel selection port includes three acquisition selection terminals; the input ports are used to connect to the loops corresponding to the input ports; the analog-to-digital converter interface 11 is connected to the output port of each multiplexer, and the first second input / output port 101a is connected to the enable terminal 203a of the first multiplexer 20a. The second second input / output port 101b is connected to the enable terminal 203b of the second multiplexer 20b; the first first input / output port 102a is connected to the first acquisition selection terminal 204a of the first channel selection port 21a and the first acquisition selection terminal 204d of the second channel selection port 21b, respectively; the second first input / output port 102b is connected to the second acquisition selection terminal 204b of the first channel selection port 21a and the second acquisition selection terminal 204e of the second channel selection port 21b, respectively; and the third first input / output port 102c is connected to the third acquisition selection terminal 204c of the first channel selection port 21a and the third acquisition selection terminal 204f of the second channel selection port 21b, respectively.

[0062] In some embodiments, the first input / output port is a general-purpose input / output port of the acquisition module.

[0063] In some embodiments, refer to Figure 1 The analog-to-digital conversion interface 11 is connected to the output port 202a of the first multiplexer 20a and the output port 202b of the second multiplexer 20b, respectively. In the first multiplexer 20a, input port 201a is connected to loop 301, input port 201b is connected to loop 302, input port 201c is connected to loop 303, input port 201d is connected to loop 304, input port 201e is connected to loop 305, input port 201f is connected to loop 306, and input port 201c is connected to loop 303. Input port 1g is connected to loop 307, and input port 201h is connected to loop 308; in the second multiplexer 20b, input port 201i is connected to loop 309, input port 201j is connected to loop 310, input port 201k is connected to loop 311, input port 201n is connected to loop 312, input port 201p is connected to loop 313, input port 201q is connected to loop 314, input port 201x is connected to loop 315, and input port 201y is connected to loop 316.

[0064] Reference Figure 2 In some embodiments, each multiplexer further includes multiple switching devices S1a, S1b, S1c, S1d, S1e, S1f, S1g, and S1h, with each switching device corresponding to an input port. In the multiplexer, one end of each switching device is connected to the corresponding input port, and the other end of each switching device is connected to the output port of the multiplexer.

[0065] It should be noted that when the switching device is on, one end of the switching device is connected to the other end; when the switching device is off, one end of the switching device is disconnected from the other end.

[0066] For example, the acquisition circuit includes an acquisition module 10 and two multiplexers; each multiplexer includes a channel selection port and eight input ports, with the input ports corresponding to external loops; the acquisition module 10 includes an analog-to-digital conversion interface 11, a first input / output port, and two second input / output ports; the number of first input / output ports is three, and the channel selection port includes three acquisition selection terminals;

[0067] The input ports are used for loop connections corresponding to the input ports; the analog-to-digital conversion interface 11 is connected to the output ports of each multiplexer respectively; the first second input / output port 101a is connected to the enable terminal 203a of the first multiplexer 20a; the second second input / output port 101b is connected to the enable terminal 203b of the second multiplexer 20b; the first first input / output port 102a is connected to the first acquisition selection terminal 204a of the first channel selection port 21a and the first acquisition selection terminal 204d of the second channel selection port 21b respectively; the second first input / output port 102b is connected to the second acquisition selection terminal 204b of the first channel selection port 21a and the second acquisition selection terminal 204e of the second channel selection port 21b respectively; the third first input / output port 102c is connected to the third acquisition selection terminal 204c of the first channel selection port 21a and the third acquisition selection terminal 204f of the second channel selection port 21b respectively.

[0068] Reference Figure 2One end of the first switching device S1a is connected to the first input port 201a; one end of the second switching device S1b is connected to the second input port 201b; one end of the third switching device S1c is connected to the third input port 201c; one end of the fourth switching device S1d is connected to the fourth input port 201d; one end of the fifth switching device S1e is connected to the fifth input port 201e; one end of the sixth switching device S1f is connected to the sixth input port 201f; one end of the seventh switching device S1g is connected to the seventh input port 201g; and one end of the eighth switching device S1h is connected to the eighth input port 201h. The other end of each switching device is connected to the output port 202a of the multiplexer.

[0069] By outputting a low level through the first second input / output port 101a and a high level through the second second input / output port 101b, the first multiplexer 20a is turned on and the second multiplexer 20b is turned off. At this time, the first multiplexer 20a is the target multiplexer. Then, by outputting a low level through the first first input / output port, the second first input / output port, and the third first input / output port, the first switch of the first multiplexer is turned on, and the other switches in the first multiplexer are turned off. This connects the first input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports in the first multiplexer from the output port. At this time, the first input port of the first multiplexer is the target input port. The input signal of the loop corresponding to the first input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11.

[0070] The first input / output port outputs a high level, while the second and third input / output ports both output a low level, causing the second switch of the first multiplexer to be turned on and the other switches in the first multiplexer to be turned off. This connects the second input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the second input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the second input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11.

[0071] The second first input / output port outputs a high level, while the first and third first input / output ports both output a low level, causing the third switch of the first multiplexer to be turned on and the other switches in the first multiplexer to be turned off. This connects the third input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the third input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the third input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11.

[0072] The third first input / output port outputs a low level, while the first and second first input / output ports both output a high level, causing the fourth switch of the first multiplexer to be turned on and all other switches in the first multiplexer to be turned off. This connects the fourth input port of the first multiplexer to the output port of the multiplexer and disconnects all other input ports from the output port of the multiplexer. At this time, the fourth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the fourth input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11.

[0073] The third first input / output port outputs a high level, while the first and second first input / output ports both output a low level, causing the fifth switch of the first multiplexer to be turned on and all other switches in the first multiplexer to be turned off. This connects the fifth input port of the first multiplexer to the output port of the multiplexer and disconnects all other input ports from the output port of the multiplexer. At this time, the fifth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the fifth input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11.

[0074] The third first input / output port outputs a low level, while both the first and third first input / output ports output a high level, causing the sixth switch of the first multiplexer to be turned on and all other switches in the first multiplexer to be turned off. This connects the sixth input port of the first multiplexer to the output port of the multiplexer and disconnects all other input ports from the output port of the multiplexer. At this time, the sixth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the sixth input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11.

[0075] The first input / output port outputs a low level, while the second and third input / output ports both output a high level, causing the seventh switch of the first multiplexer to be turned on and the other switches in the first multiplexer to be turned off. This connects the seventh input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the seventh input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the seventh input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11.

[0076] By outputting a high level through the first, second, and third input / output ports, the eighth switch of the first multiplexer is turned on, and all other switches in the first multiplexer are turned off. This connects the eighth input port of the first multiplexer to the output port of the multiplexer, and disconnects the other input ports from the output port of the multiplexer. At this time, the eighth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the eighth input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11.

[0077] The first multiplexer is turned off and the second multiplexer is turned on by outputting a high level through the first second input / output port and a low level through the second second input / output port. At this time, the second multiplexer is the target multiplexer. The selection process of the input port of the second multiplexer is similar to that of the first multiplexer, and will not be repeated here.

[0078] In this embodiment of the invention, the first input / output port is connected to the channel selection port by connecting the acquisition selection terminal to the first input / output port corresponding to the acquisition selection terminal.

[0079] Optionally, in some embodiments, the acquisition module 10 further includes a storage module 13; the analog-to-digital conversion interface 11 is used to convert the input signal into a digital signal; the storage module 13 is connected to the analog-to-digital conversion interface 11, and the storage module 13 is used to store the input signal.

[0080] It should be noted that the storage module 13 is specifically used to store data representing the input signal.

[0081] In this embodiment of the invention, the input signal is stored by the storage module 13 so that the processing module 40 can acquire the input signal through the acquisition module 10.

[0082] Optionally, in some embodiments, the storage module 13 includes a volatile memory 131 and a non-volatile memory 132; the volatile memory 131 is connected to the analog-to-digital conversion interface 11, and the volatile memory 131 is used to store the input signal transmitted by the analog-to-digital conversion interface 11; the non-volatile memory 132 is connected to the volatile memory 131, and the non-volatile memory 132 is used to store the input signal transmitted by the volatile memory 131.

[0083] It should be noted that the volatile memory 131 is specifically used to store data representing the input signal, and the non-volatile memory 132 is specifically used to store data representing the input signal.

[0084] In this embodiment of the invention, the input signal is temporarily stored in the volatile memory 131 and then stored in the non-volatile memory 132 so that the processing module 40 can acquire the input signal through the acquisition module 10.

[0085] Optionally, in some embodiments, the volatile memory 131 may be of the type of random access memory; the non-volatile memory 132 may be of the type of read-only memory and / or flash memory.

[0086] It should be noted that Random Access Memory (RAM), Read-Only Memory (ROM), and Flash Memory are all types of memory.

[0087] In this embodiment of the invention, since random access memory occupies less memory and computing resources, it can be used to temporarily store input signals, thereby reducing memory and computing resource consumption. In order to prevent data loss and errors, read-only memory and flash memory can be used to further store input signals, and the data in read-only memory and flash memory can be accessed externally in a timely manner.

[0088] Optionally, in some embodiments, the analog-to-digital conversion interface 11 is used to convert the input signal into a digital signal; the acquisition module 10 is used to connect to the processing module 40 so that the processing module 40 can acquire the input signal through the acquisition module 10 and generate alarm information when the input signal is abnormal.

[0089] In some embodiments, the processing module 40 is specifically used to compare the input signal with the standard input signal, and determine that the input signal is abnormal when the input signal and the standard input signal are inconsistent. For example, the input signal is abnormal when the level of the input signal is inconsistent with the level of the standard input signal.

[0090] In this embodiment of the utility model, the input signal is converted into a digital signal through the analog-to-digital conversion interface 11, and the input signal is acquired through the processing module 40. In the event of an abnormal input signal, an alarm message is generated so that the user can be notified of external circuit abnormalities and handle the fault in a timely manner.

[0091] Optionally, in some embodiments, the acquisition module 10 is a microcontroller unit; the processing module 40 is a system-on-a-chip, a microcontroller unit, and / or a field-programmable gate array (FPGA).

[0092] In this embodiment of the invention, the input signal can be converted into a digital signal by the microcontroller unit, and the alarm information can be generated when the input signal is abnormal by the system-on-a-chip.

[0093] Optionally, in some embodiments, the acquisition module 10 further includes a processor 12 and a timer 14; the timer 14 is connected to the processor 12; wherein the timer 14 is used to increment the time according to a first preset time interval; when the time interval of the timer 14 reaches a second preset time, the analog-to-digital conversion interface 11 acquires one of the input signals. The processor 12 is used to, when the time interval of the timer 14 reaches the second preset time, cause the acquisition module 10 to acquire one of the input signals and store it in the volatile memory 131, and when each of the input signals of one multiplexer has been acquired, reset the timer to zero and transfer each input signal in the volatile memory 131 to the non-volatile memory 132 for the acquisition of the next input signal of the multiplexer.

[0094] In some embodiments, the second preset time is 10 milliseconds. The processor 12 is configured to cause the acquisition module 10 to acquire the input signal of the loop corresponding to the target input port every 10 milliseconds recorded by the timer 14.

[0095] In this embodiment of the present invention, the processor 12 enables the acquisition module 10 to acquire the input signal of the circuit corresponding to the target input port when the timer 14 records one cycle, so as to acquire each input signal in a polling manner.

[0096] Reference Figure 3In some embodiments, the first preset time is 1 millisecond, and the second preset time is 10 milliseconds. The input signal acquisition process includes: X1, determining the number of input signals; X2, determining the number of multiplexers, i.e., adding multiplexers when the number of input signals is greater than the number of input ports of existing multiplexers; X3, connecting each multiplexer to the acquisition module 10; X4, starting timer 14, i.e., enabling the timer 14 timing function; X5, determining whether there is an acquisition request instruction, i.e., whether the acquisition module 10 has obtained an instruction to acquire input signals; X6, resetting timer 14 to zero; X7, polling each multiplexer; X8, checking if it is 0 milliseconds, i.e., determining if timer 14 is 0 milliseconds; X9, acquiring the input signal of the loop corresponding to the target input port; X10, checking if it is 10 milliseconds, i.e., determining if timer 14 is 1 millisecond. 0 milliseconds; X11, Obtain the input signal of the loop corresponding to the target input port; X12, Check if it is 20 milliseconds, i.e., determine if timer 14 is 20 milliseconds; X13, Obtain the input signal of the loop corresponding to the target input port; X14, Check if it is 70 milliseconds, i.e., determine if timer 14 is 70 milliseconds; X15, Obtain the input signal of the loop corresponding to the target input port; X16, Increment by 1 millisecond; X17, Store the input signal, i.e., when the analog-to-digital converter interface 11 converts the input signal into a digital signal and the volatile memory 131 stores the input signal, the input signal is stored through the non-volatile memory 132; X18, The processing module 40 obtains the input signal through the acquisition module 10, and generates alarm information when the input signal is abnormal.

[0097] Specifically, timer 14 is initialized to 0 milliseconds. A low level is output through the first second input / output port, and a high level is output through the second second input / output port, which turns on the first multiplexer and turns off the second multiplexer. At this time, the first multiplexer is the target multiplexer. Then, a low level is output through the first first input / output port, the second first input / output port, and the third first input / output port, which turns on the first switch of the first multiplexer and turns off the other switches in the first multiplexer. This connects the first input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports in the first multiplexer from the output port of the multiplexer. At this time, the first input port of the first multiplexer is the target input port. The input signal of the loop corresponding to the first input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11, and the input signal is converted into a first digital signal and stored in RAM.

[0098] Simultaneously, timer 14 starts counting. When timer 14 is 10 milliseconds, a high level is output through the first input / output port, and a low level is output through the second and third input / output ports. This turns on the second switch of the first multiplexer and turns off the other switches in the first multiplexer. This connects the second input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the second input port of the first multiplexer is the target input port. The input signal of the loop corresponding to the second input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11, and the input signal is converted into a second digital signal and stored in RAM.

[0099] When timer 14 is 20 milliseconds, a high level is output through the second first input / output port, and both the first and third first input / output ports output a low level, causing the third switch of the first multiplexer to be turned on, and the other switches in the first multiplexer to be turned off, so that the third input port of the first multiplexer is connected to the output port of the multiplexer, and the other input ports in the first multiplexer to be turned off from the output port of the multiplexer. At this time, the third input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the third input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11, and the input signal is converted into a third digital signal and stored in RAM.

[0100] When timer 14 is 30 milliseconds, a low level is output through the third first input / output port, and both the first and second first input / output ports output a high level, causing the fourth switch of the first multiplexer to be turned on, and the other switches in the first multiplexer to be turned off, so that the fourth input port of the first multiplexer is connected to the output port of the multiplexer, and the other input ports in the first multiplexer to be turned off from the output port of the multiplexer. At this time, the fourth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the fourth input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11, and the input signal is converted into a fourth digital signal and stored in RAM.

[0101] When timer 14 is 40 milliseconds, a high level is output through the third first input / output port, and both the first and second first input / output ports output a low level, causing the fifth switch of the first multiplexer to be turned on, and the other switches in the first multiplexer to be turned off, so that the fifth input port of the first multiplexer is connected to the output port of the multiplexer, and the other input ports in the first multiplexer to be turned off from the output port of the multiplexer. At this time, the fifth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the fifth input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11, and the input signal is converted into a fifth digital signal and stored in RAM.

[0102] When timer 14 is 50 milliseconds, a low level is output through the third first input / output port, and both the first and third first input / output ports output a high level, causing the sixth switch of the first multiplexer to be turned on, and the other switches in the first multiplexer to be turned off, so that the sixth input port of the first multiplexer is connected to the output port of the multiplexer, and the other input ports in the first multiplexer to be turned off from the output port of the multiplexer. At this time, the sixth input port of the first multiplexer is the target input port, and the input signal of the loop corresponding to the sixth input port of the first multiplexer can be obtained through the analog-to-digital conversion interface 11, and the input signal is converted into a sixth digital signal and stored in RAM.

[0103] When timer 14 is 60 milliseconds, the first input / output port outputs a low level, while the second and third input / output ports output a high level, causing the seventh switch of the first multiplexer to be turned on and the other switches in the first multiplexer to be turned off. This connects the seventh input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the seventh input port of the first multiplexer is the target input port. The input signal of the loop corresponding to the seventh input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11, and the input signal is converted into a seventh digital signal and stored in RAM.

[0104] When timer 14 is 70 milliseconds, the first, second, and third first input / output ports all output high levels, turning on the eighth switch of the first multiplexer and turning off the other switches in the first multiplexer. This connects the eighth input port of the first multiplexer to the output port of the multiplexer and disconnects the other input ports from the output port of the multiplexer. At this time, the eighth input port of the first multiplexer is the target input port. The input signal of the loop corresponding to the eighth input port of the first multiplexer can be obtained through the analog-to-digital converter interface 11, and the input signal is converted into the eighth digital signal and stored in RAM.

[0105] When timer 14 is 80 milliseconds, the acquisition module 10 stores the eight input signals in RAM into ROM or FLASH, and then outputs a high level through the first second input / output port and a low level through the second second input / output port, so that the first multiplexer is turned off and the second multiplexer is turned on. At this time, the second multiplexer is the target multiplexer. The selection process of the input port of the second multiplexer is similar to the selection process of the input port of the first multiplexer, and will not be repeated here. It takes 160 milliseconds to acquire each input signal once.

[0106] The processing module 40 acquires the input signal through the acquisition module 10 and generates an alarm message when the input signal is abnormal. Since the signal acquisition and processing are performed by different modules, the division of labor is clear and the processing efficiency is improved.

[0107] This utility model embodiment also provides a chip, including the acquisition circuit as described above.

[0108] The specific implementation process of the acquisition circuit in the chip is similar to that of the aforementioned acquisition circuit, and will not be repeated here.

[0109] This utility model embodiment also provides a controller, including the acquisition circuit as described above, or including the chip as described above.

[0110] In some embodiments, the controller further includes a processing module; the analog-to-digital conversion interface is used to convert the input signal into a digital signal; the processing module is connected to the acquisition module, and the processing module is used to acquire the input signal through the acquisition module 10, and generate alarm information when the input signal is abnormal.

[0111] In some embodiments, the controller is a domain controller.

[0112] The specific implementation process of the acquisition circuit in the controller is similar to that of the aforementioned acquisition circuit, and will not be repeated here.

[0113] In some embodiments, the controller is the intelligent driving domain controller of the vehicle. Through the embodiments of this utility model, an effective processing solution is provided for the full voltage acquisition of the intelligent driving domain controller, achieving efficient, low-cost, and stable system-level applications.

[0114] This utility model embodiment also provides a vehicle, including the acquisition circuit as described above, or including the chip as described above, or including the controller as described above.

[0115] The specific implementation process of the data acquisition circuit in the vehicle is similar to that of the aforementioned data acquisition circuit, and will not be repeated here.

[0116] In related technologies, the insufficient number of analog-to-digital conversion interfaces of the microcontroller unit is compensated by adding acquisition chips and relying on the acquisition chips to acquire and detect the input signals of multiple circuits. However, the acquisition chips occupy the integrated circuit interconnect (I2C) interface and have low processing efficiency.

[0117] In this embodiment of the invention, the analog-to-digital conversion interface 11 is expanded into multiple input ports by multiple multiplexers, which makes up for the insufficient number of analog-to-digital conversion interfaces 11. Each input signal is acquired by polling, so that the acquisition module 10 can support the acquisition of input signals from all loops without occupying the integrated circuit interconnection interface. Furthermore, the processing module 40 detects whether the digital signal converted from the input signal is abnormal. Compared with the related technology that uses an acquisition chip for signal acquisition and detection, the acquisition module 10 and the processing module 40 can process in parallel, which improves the processing efficiency.

[0118] Through the embodiments of this utility model, low-cost and high-efficiency ADC voltage acquisition and processing can be achieved, with less occupancy of the analog-to-digital conversion interface 11, and multi-threaded acquisition and diagnostic processing can be performed simultaneously; through the collaborative processing of RAM and FLASH, the acquisition and processing is efficient and stable.

[0119] In summary, in this embodiment of the present invention, since the output port of each multiplexer is connected to the analog-to-digital conversion interface of the acquisition module 10, multiple input signals can be acquired by sending the input signals acquired by the multiplexer to the acquisition module 10, without occupying too many interfaces other than the analog-to-digital conversion interface of the acquisition module, thus reducing the resource occupancy rate of the interfaces.

[0120] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device.

[0121] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0122] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

[0123] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A harvesting circuit, characterized by, The application relates to a data acquisition module. The data acquisition module comprises an analog-digital conversion interface (11); The data acquisition module comprises a plurality of multiplexers, and the output port of each multiplexer is connected with the analog-digital conversion interface (11) to send the input signal acquired by the multiplexer to the data acquisition module (10).

2. The harvesting circuit of claim 1, wherein, The multiplexer comprises a channel selection port and a plurality of input ports; The data acquisition module (10) further comprises a first input-output port, which is connected with the channel selection port of each multiplexer to select the input port in communication with the output port of the multiplexer to acquire the corresponding input signal through the analog-digital conversion interface (11).

3. The harvesting circuit of claim 2, wherein, The first input-output port is a plurality of input-output ports. The channel selection port comprises a plurality of acquisition selection ends, which are connected with the first input-output port one by one.

4. The harvesting circuit of claim 3, wherein, The first input-output port is connected with the acquisition selection end corresponding to the first input-output port in each multiplexer.

5. The harvesting circuit of claim 2, wherein, The multiplexer further comprises a plurality of switch devices, one end of the switch device is connected with the input port one by one, and the other end of the switch device is connected with the output port of the multiplexer.

6. The harvesting circuit of claim 1, wherein, The data acquisition module (10) further comprises a second input-output port; The second input-output port is connected with the enable end of the multiplexer.

7. The harvesting circuit of claim 6, wherein, In the case that the second input-output port is a first level, the multiplexer works; In the case that the second input-output port is a second level, the multiplexer stops working; The second level is lower than or higher than the first level.

8. The harvesting circuit of claim 6, wherein, The second input-output port is a plurality of input-output ports, and the second input-output ports are connected with the enable end of each multiplexer one by one.

9. The harvesting circuit of claim 8, wherein, At each moment, one second input-output port is a first level, and the other second input-output ports are a second level; The second level is lower than or higher than the first level.

10. The harvesting circuit according to any one of claims 1 to 9, characterized in that, The data acquisition module (10) is used to acquire the input signal according to the acquisition timing in turn.

11. The harvesting circuit according to any one of claims 1 to 9, characterized in that, The data acquisition module (10) further comprises a timer (14), which is used to increase the time according to a first preset time interval; in the case that the time interval of the timer (14) reaches a second preset time, the analog-digital conversion interface (11) acquires one input signal.

12. The harvesting circuit of claim 11, wherein, The data acquisition module (10) further comprises a processor (12) and a storage module (13); the storage module (13) comprises a volatile memory (131); The processor (12) is connected with the timer (14), and the processor (12) is used to make the analog-digital conversion interface (11) acquire one input signal and store the input signal to the volatile memory (131) in the case that the time interval of the timer (14) reaches the second preset time.

13. The harvesting circuit of claim 12, wherein, The storage module (13) further comprises a non-volatile memory (132); The processor (12) is further configured to reset the timer and transfer each of the input signals in the volatile memory (131) to the non-volatile memory (132) when the acquisition of each of the input signals of one of the multiplexers is completed.

14. The harvesting circuit according to any one of claims 1 to 9, characterized in that, The input signal is a voltage signal.

15. The harvesting circuit according to any one of claims 1 to 9, characterized in that, The acquisition module (10) further comprises a storage module (13). The storage module (13) is connected to the analog-digital conversion interface (11), and the storage module (13) is configured to store the input signal.

16. The harvesting circuit of claim 15, wherein, The storage module (13) comprises a volatile memory (131). The volatile memory (131) is connected to the analog-digital conversion interface (11), and the volatile memory (131) is configured to store the input signal transmitted by the analog-digital conversion interface (11).

17. The harvesting circuit of claim 16, wherein, The storage module (13) further comprises a non-volatile memory (132). The non-volatile memory (132) is connected to the volatile memory (131), and the non-volatile memory (132) is configured to store the input signal transmitted by the volatile memory (131).

18. The harvesting circuit of claim 17, wherein, The type of the volatile memory (131) comprises a random access memory, and the type of the non-volatile memory (132) comprises a read-only memory and / or a flash memory.

19. The acquisition circuit according to any one of claims 1 to 9, wherein The acquisition module (10) is adapted to be connected to a processing module (40) so that the processing module (40) acquires the input signal through the acquisition module (10).

20. The acquisition circuit according to claim 19, wherein The processing module (40) is configured to generate an alarm information when the input signal is abnormal.

21. The harvesting circuit of claim 19, wherein, The processing module (40) is a system on chip, a micro control unit and / or a field programmable gate array.

22. The harvesting circuit of any one of claims 1 to 9, wherein, The type of the acquisition module (10) comprises a micro control unit, a system on chip and / or a single chip microcomputer.

23. A chip, characterized by The acquisition circuit according to any one of claims 1 to 22.

24. A controller characterized by The acquisition circuit according to any one of claims 1 to 22, or the chip according to claim 23.

25. The controller of claim 24, wherein, The controller further comprises a processing module (40). The analog-digital conversion interface (11) of the acquisition module (10) is configured to acquire the input signal. The processing module (40) is connected to the acquisition module (10), and the processing module (40) is configured to acquire the input signal through the acquisition module (10).

26. The controller according to claim 25, wherein The processing module (40) is further configured to generate an alarm information when the input signal is abnormal.

27. The controller of claim 24, wherein, The controller is a domain controller.

28. A vehicle characterized by The acquisition circuit according to any one of claims 1 to 22, the chip according to claim 23, or the controller according to any one of claims 24 to 27.

Images