Decoding circuit and device and equipment using same

Abstract

The embodiment of the utility model provides a decoding circuit, a digital signal edge monitoring device using the decoding circuit, a frequency conversion equipment controller and frequency conversion equipment, and belongs to the technical field of electronic circuits. The decoding circuit comprises a hysteresis circuit and a monostable filtering time circuit and is used for detecting the edge of a digital signal and stably outputting a digital output pulse with a fixed width, and the pulse width of the digital output pulse depends on the filtering time of the monostable filtering time circuit.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a decoding circuit and a digital signal edge monitoring device, frequency converter controller, and frequency converter using the decoding circuit. Background Technology

[0002] Digital signal edges are easily interfered with during transmission. Therefore, digital signal edges that require fast and accurate transmission are usually encrypted. However, according to existing technology, when decoding at the receiving end, time errors occur in capturing the digital signal edges due to crystal oscillator offset and timing fluctuations. Furthermore, short-duration signals (less than microseconds) cannot be accurately captured. Applying such decoding circuits to control systems or equipment can easily lead to malfunctions or even accidents.

[0003] In the process of realizing this utility model, the inventors of this application discovered that the above-mentioned technical defects of the prior art have not been effectively resolved. Utility Model Content

[0004] The purpose of this utility model embodiment is to provide a decoding circuit for edge detection of digital signals and stable output of a digital output pulse of a fixed width.

[0005] To achieve the above objectives, this utility model provides a decoding circuit for decoding edge signals of digital input signals, comprising: a hysteresis circuit and a monostable filtering time circuit.

[0006] The hysteresis circuit includes a Schmitt trigger, and the monostable filtering time circuit includes a dual-channel single-trigger oscillator chip and a first RC filter circuit composed of a first resistor and a first capacitor.

[0007] The digital input signal is divided into two paths. One path is connected to the falling edge trigger input of the dual-channel single-trigger oscillator chip, and the other path is connected to the rising edge trigger input of the dual-channel single-trigger oscillator chip via a Schmitt trigger.

[0008] The first resistor and the first capacitor are connected in series and then bridged between the power supply and the ground terminal. The connection point of the first resistor and the first capacitor is also connected to the timer input of a dual-channel single-trigger oscillator chip.

[0009] The output of the dual-channel single-trigger oscillator chip is a pulse signal obtained after processing the digital input signal.

[0010] Preferably, the hysteresis circuit also includes a second RC filter circuit. The digital input signal is filtered out of high-frequency interference by the second RC filter circuit and then divided into two inputs, which are respectively input to the Schmitt trigger and the dual-channel single-trigger oscillator chip.

[0011] Preferably, the second RC filter circuit includes a second resistor and a second capacitor, wherein the second resistor also serves as a pull-up resistor, connected between the power supply and the falling edge trigger input terminal, so that the falling edge trigger input terminal always receives a high-level signal.

[0012] Preferably, the pulse signal is a pulse signal with a preset time width, which is equivalent to the filtering time of the first RC filter circuit.

[0013] Furthermore, the decoding circuit also includes a voltage divider circuit, which includes a third resistor and a fourth resistor. The third resistor and the fourth resistor are connected in series and then connected across the power supply and the ground terminal. The connection point of the third resistor and the fourth resistor is also connected to the output terminal of the dual-channel single-trigger oscillator chip.

[0014] Preferably, the resistance value of the third resistor is determined by the high level of the desired pulse signal, and the resistance value of the fourth resistor is determined by the low level of the desired pulse signal.

[0015] Preferably, the Schmitt trigger is an SN74HC14D chip, wherein the third pin of the SN74HC14D chip is connected to a digital input signal, which is processed and then output by the fourth pin.

[0016] Preferably, the dual-channel single-trigger oscillator chip is the MC74HC4538AD chip, wherein the third and fifth pins of the MC74HC4538AD chip are connected to digital input signals; the fourth pin of the MC74HC4538AD chip is connected to the signal output after processing by a Schmitt trigger; and the sixth pin of the MC74HC4538AD chip outputs the obtained pulse signal.

[0017] Preferably, the first resistor, the second resistor, the third resistor, and the fourth resistor are all integrated resistors.

[0018] Preferably, the power supply provides a 3.3V DC voltage, the first resistor has a resistance of 51kΩ, and the second, third, and fourth resistors have a resistance of 10kΩ.

[0019] On the other hand, this utility model embodiment also provides a digital signal edge monitoring device for monitoring the rising or falling edge of a digital signal, including the decoding circuit of this application. The digital signal to be monitored is used as the digital input signal of the decoding circuit. The rising or falling edge of the digital signal is determined according to the high or low level transition of the pulse signal output by the decoding circuit.

[0020] On the other hand, this utility model embodiment also provides a frequency converter controller, including the decoding circuit of this application, wherein the control signal for controlling the frequency converter is processed by the decoding circuit and then transmitted to the frequency converter.

[0021] Optionally, the frequency converter can be a motor, power equipment, electrical equipment, or appliance.

[0022] On the other hand, this utility model embodiment also provides a frequency converter, including the frequency converter controller of this application, which receives a control signal processed by a decoding circuit and controls the operating frequency of the frequency converter through the control signal.

[0023] The decoding circuit, as described above, includes a hysteresis circuit and a monostable filtering time circuit. The hysteresis circuit is used for hysteresis processing of the input signal, and the monostable filtering time circuit is used for edge detection of the digital signal and to stably output a digital output pulse of a fixed width. The pulse width of the digital output pulse depends on the filtering time of the monostable filtering time circuit.

[0024] Other features and advantages of this utility model embodiment will be described in detail in the following detailed description section. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a circuit diagram of one embodiment of the decoding circuit of this utility model. Detailed Implementation

[0027] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0028] It should be noted that the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0029] In the description of this specification, the terms "comprising," "including," "having," and "containing" are open-ended terms, meaning that they include but are not limited to. The terms "an embodiment," "a specific embodiment," "some embodiments," and "for example," etc., refer to specific features, structures, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. The order of steps involved in the various embodiments is used to illustrate the implementation of this application, and the order of steps is not limited and can be adjusted appropriately as needed.

[0030] Figure 1 This is a circuit diagram of a decoding circuit provided in an embodiment of the present invention. The decoding circuit is used to decode the edge signals of a digital input signal, which are generated by... Figure 1 The In terminal input shown, after being processed by the decoding circuit, converts the edge signal of the decoded digital input signal into a fixed-width digital output pulse. This digital output pulse is then processed by... Figure 1 The Out terminal is shown as the output.

[0031] In this embodiment, the decoding circuit mainly includes: a hysteresis circuit and a monostable filtering time circuit, wherein the hysteresis circuit includes: Figure 1 The Schmitt trigger SN74HC14D shown has a monostable filtering time circuit comprising a dual-channel single-trigger oscillator chip MC74HC4538AD and a first RC filter circuit composed of a first resistor R1 and a first capacitor C1. The digital input signal is divided into two paths, one of which is connected to the falling edge trigger input terminal 5 of the dual-channel single-trigger oscillator chip MC74HC4538AD, and the other is connected to the rising edge trigger input terminal 4 of the dual-channel single-trigger oscillator chip MC74HC4538AD via the Schmitt trigger SN74HC14D. The first resistor R1 and the first capacitor C1 are connected in series between the power supply and the ground terminal, and the connection point of the first resistor R1 and the first capacitor C1 is also connected to the timer input terminal 2 of the dual-channel single-trigger oscillator chip MC74HC4538AD. The output terminal 6 of the dual-channel single-trigger oscillator chip MC74HC4538AD outputs the pulse signal obtained after processing the digital input signal.

[0032] It should be noted that in this embodiment, the Schmitt trigger is an SN74HC14D chip, where the third pin of the SN74HC14D chip is connected to the digital input signal, processed, and output from the fourth pin. The dual-channel single-trigger oscillator chip is an MC74HC4538AD chip, where the third and fifth pins of the MC74HC4538AD chip are connected to the digital input signal; the fourth pin of the MC74HC4538AD chip is connected to the signal output after processing by the Schmitt trigger; and the sixth pin of the MC74HC4538AD chip outputs the obtained pulse signal. However, this invention is not limited to this. Those skilled in the art can select the Schmitt trigger and the dual-channel single-trigger oscillator according to the actual parameters to be obtained, ensuring that the Schmitt trigger meets the hysteresis characteristics required by the design, and that the dual-channel single-trigger oscillator provides the digital output pulse that meets the design requirements.

[0033] In this embodiment, to filter high-frequency interference signals, the hysteresis circuit also includes a second RC filter circuit. The digital input signal is filtered by the second RC filter circuit to remove high-frequency interference before being split into two inputs, which are respectively input to the third pin of the SN74HC14D chip and the fourth pin of the MC74HC4538AD. For example... Figure 1 As shown, the second RC filter circuit includes a second resistor R2 and a second capacitor C2. The second resistor R2 also acts as a pull-up resistor, connected between the 3.3V power supply and the fifth pin of the MC74HC4538AD, i.e. the falling edge trigger input 5, so that the falling edge trigger input 5 always inputs a high-level signal.

[0034] In this embodiment, the sixth pin of the MC74HC4538AD is the final pulse signal, which is a pulse signal with a preset time width. The preset time width is equivalent to the filtering time of the first RC filter circuit, and the filtering time t is equal to 0.7*R1*C1.

[0035] In this embodiment, the decoding circuit also includes a voltage divider circuit, which includes a third resistor R3 and a fourth resistor R4. The third resistor R3 and the fourth resistor R4 are connected in series and then connected across the power supply and the ground terminal. The connection point of the third resistor R3 and the fourth resistor R4 is also connected to the output terminal 6 of the dual-channel single-trigger oscillator chip MC74HC4538AD, i.e., the sixth pin.

[0036] In this embodiment, pin 6 of the MC74HC4538AD is the decoded output signal Out. It is connected to the power supply via pull-up resistor R3 to provide a pull-up level, and connected to the reference ground via pull-down resistor R4 to provide a low level. That is, the resistance value of the third resistor R3 is determined by the high level of the desired pulse signal, and the resistance value of the fourth resistor R4 is determined by the low level of the desired pulse signal.

[0037] In this embodiment, the power supply provides a 3.3V DC voltage, but the invention is not limited to this; those skilled in the art can determine the voltage value of the power supply based on the design parameters. Furthermore, to reduce resistance drift caused by temperature and ensure output stability and low variation, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are all integrated resistors.

[0038] When the rising edge of the digital input signal In passes through the above circuit, a pulse signal will be generated at the output terminal Out, for example, a pulse of 35.7ms. During the 35.7ms pulse period, if the input signal In generates another falling edge, it will no longer respond until the 35.7ms signal output is completed and a new pulse signal is generated again.

[0039] Compared with the prior art, the technical advantages of this embodiment are as follows:

[0040] 1. Edge detection and stable output of digital signals are achieved by using a Schmitt trigger and a dual-channel single-trigger oscillator, generating digital output pulses of fixed width;

[0041] 2. The pulse width of the output pulse is determined by resistor R1 and capacitor C1, and is not affected by the external crystal oscillator;

[0042] 3. During the output pulse period, even if interference signals are generated, the above-mentioned fixed-width output pulse will continue to be completed, thus eliminating the influence of interference signals during transmission.

[0043] This utility model embodiment also provides a digital signal edge monitoring device for monitoring the rising or falling edge of a digital signal, including the decoding circuit of this application. The digital signal to be monitored is used as the digital input signal of the decoding circuit. The rising or falling edge of the digital signal is determined according to the high-low level transition of the pulse signal output by the decoding circuit.

[0044] This utility model embodiment also provides a frequency converter controller, including the decoding circuit of this application. The control signal for controlling the frequency converter is processed by the decoding circuit and then transmitted to the frequency converter. The frequency converter can be a motor, power equipment, electrical equipment, or appliance, such as a frequency converter motor with a common load like a fan or pump.

[0045] This utility model embodiment also provides a frequency converter, including the frequency converter controller of this application, which receives a control signal processed by a decoding circuit and controls the operating frequency of the frequency converter through the control signal.

[0046] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0047] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A decoding circuit for decoding an edge signal of a digital input signal, characterized in that, The application relates to a delay circuit and a monostable filter time circuit. The delay circuit comprises a Schmitt trigger, and the monostable filter time circuit comprises a double-channel monostable oscillator chip and a first RC filter circuit composed of a first resistor and a first capacitor. The digital input signal is divided into two paths, one of which is connected to the falling edge trigger input end of the double-channel monostable oscillator chip, and the other is connected to the rising edge trigger input end of the double-channel monostable oscillator chip through the Schmitt trigger. The first resistor and the first capacitor are connected in series and are connected between a power supply and a ground end, and the connection point of the first resistor and the first capacitor is also connected to the timer input end of the double-channel monostable oscillator chip. The output end of the double-channel monostable oscillator chip outputs a pulse signal obtained by processing the digital input signal. The delay circuit further comprises a second RC filter circuit, and the digital input signal is filtered by the second RC filter circuit to remove high-frequency interference and then divided into two paths for inputting into the Schmitt trigger and the double-channel monostable oscillator chip respectively.

2. The decoding circuit of claim 1, wherein, The second RC filter circuit comprises a second resistor and a second capacitor.

3. The decoding circuit of claim 2, wherein, The second resistor also serves as a pull-up resistor and is connected between a power supply and the falling edge trigger input end, so that the falling edge trigger input end always inputs a high-level signal. The pulse signal is a pulse signal with a preset time width, and the preset time width is equivalent to the filtering time of the first RC filter circuit.

4. The decoding circuit of claim 3, wherein, The application further comprises a voltage dividing circuit.

5. The decoding circuit of claim 4, wherein, The voltage dividing circuit comprises a third resistor and a fourth resistor, and the third resistor and the fourth resistor are connected in series and are connected between the power supply and the ground end. The connection point of the third resistor and the fourth resistor is also connected to the output end of the double-channel monostable oscillator chip. The resistance value of the third resistor is determined by the high level of the pulse signal to be obtained, and the resistance value of the fourth resistor is determined by the low level of the pulse signal to be obtained.

6. The decoding circuit of claim 5, wherein, The Schmitt trigger is an SN74HC14D chip.

7. The decoding circuit according to any one of claims 1 to 6, characterized by, The third pin of the SN74HC14D chip is connected to the digital input signal and outputs the signal through the fourth pin after processing. The double-channel monostable oscillator chip is an MC74HC4538AD chip.

8. The decoding circuit of claim 7, wherein, The third pin and the fifth pin of the MC74HC4538AD chip are connected to the digital input signal. The fourth pin of the MC74HC4538AD chip is connected to the signal output after processing by the Schmitt trigger. The sixth pin of the MC74HC4538AD chip outputs the obtained pulse signal. The first resistor, the second resistor, the third resistor and the fourth resistor are all integrated resistors.

9. The decoding circuit of claim 6, wherein, The power supply provides a 3.3V direct current voltage, the resistance value of the first resistor is 51kOmega, and the resistance values of the second resistor, the third resistor and the fourth resistor are 10kOmega.

10. The decoding circuit of claim 9, wherein, ​ 11. An edge monitoring apparatus of a digital signal for monitoring a rising edge or a falling edge of the digital signal, characterized by, The decoding circuit according to any one of claims 1-10, wherein a digital signal to be monitored is taken as a digital input signal of the decoding circuit, and a rising edge or a falling edge of the digital signal is determined according to a transition of a high level or a low level of a pulse signal output by the decoding circuit.

12. A variable frequency equipment controller characterized by, The decoding circuit according to any one of claims 1-10, wherein a control signal for controlling a variable frequency device is transmitted to the variable frequency device after being processed by the decoding circuit.

13. The variable frequency equipment controller of claim 12, wherein, The variable frequency device is a motor device, a power device, an electrical device or an electric appliance.

14. A frequency conversion device, comprising: The variable frequency device controller according to claim 12 or 13, wherein a control signal processed by the decoding circuit is received, and a working frequency of the variable frequency device is controlled by the control signal.

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