Memory device

Abstract

An embodiment of the utility model discloses a memory device. The memory device includes a compound semiconductor feature. The compound semiconductor feature includes a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature. The first portion is over the second portion, the second portion is over the third portion, and the second portion extends vertically from the first portion to the third portion. The memory device includes a gate structure horizontally surrounding and covering the second portion, and a capacitor structure directly contacting and surrounding and covering the compound semiconductor feature.

Description

Technical Field

[0001] This disclosure concerns a memory device. Background Technology

[0002] The electronics industry is experiencing a surge in demand for smaller, faster electronic devices capable of supporting a significant increase in complexity. To meet this demand, the current trend in the integrated circuit (IC) industry continues to focus on manufacturing low-cost, high-performance, and low-power integrated circuits. To date, reducing the dimensions of integrated circuits has achieved most of these goals (e.g., minimizing the size of IC features), thereby improving production efficiency and reducing associated costs. However, such a scale increases the complexity of the integrated circuit manufacturing process. Therefore, achieving continuously evolving integrated circuit devices and performance requires similarly advanced integrated circuit processes and technologies.

[0003] Many advanced technologies are now applied in the field of memory devices, including single-transistor-single-capacitor (1T1C) memory devices for Dynamic Random Access Memory (DRAM), Ferroelectric RAM (FeRAM), and other memory types. However, integrating more devices into smaller areas necessitates improvements in device density. For example, many existing single-transistor-single-capacitor devices each consist of a planar transistor and a planar capacitor mounted on two separate metal layers. These single-transistor-single-capacitor devices occupy significant amounts of space both horizontally and vertically. Therefore, device density cannot be further reduced.

[0004] Therefore, while existing methods and devices related to single-transistor-single-capacitor memory devices are generally sufficient to achieve the intended purpose, they are not entirely satisfactory in all aspects. Utility Model Content

[0005] This disclosure discloses a memory device. The memory device includes compound semiconductor features. The compound semiconductor features include a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, and the second portion extends vertically from the first portion to the third portion. The memory device includes a gate structure horizontally surrounding and enclosing the second portion, and a capacitor structure directly contacting and surrounding the compound semiconductor features.

[0006] Another embodiment disclosed herein is a memory device. The memory device includes a conductive layer above a dielectric layer. The memory device includes a compound semiconductor feature above the conductive layer, the compound semiconductor feature including a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, with the second portion extending vertically from the first portion to the third portion. The memory device includes a gate structure horizontally surrounding the second portion of the compound semiconductor feature, a metal-insulator-metal capacitor structure located above the first portion of the compound semiconductor feature, wherein the coplanar metal-insulator-metal capacitor structure directly contacts multiple upper and side surfaces of the first portion of the compound semiconductor feature, and an insulating layer is located between the gate structure and the metal-insulator-metal capacitor structure.

[0007] This disclosure discloses a memory device. The memory device includes a compound semiconductor feature. The compound semiconductor feature includes a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, and the second portion extends vertically from the first portion to the third portion. The compound semiconductor feature has an amorphous or polycrystalline silicon structure. The memory device includes a gate structure horizontally surrounding and enclosing the second portion, and a capacitor structure directly contacting and surrounding the compound semiconductor feature. Attached Figure Description

[0008] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1A To illustrate the circuit diagram of a memory device having transistors and capacitors according to the embodiments herein;

[0010] Figure 1B To illustrate according to the embodiments herein Figure 1A Cross-sectional view of the memory device;

[0011] Figures 2A to 2B A flowchart illustrating a method for forming a memory device having transistors and capacitors, according to embodiments herein;

[0012] Figures 3 to 14 and Figures 16 to 17 To illustrate a memory device having transistors and capacitors according to the embodiments herein. Figure 2A and Figure 2B The method described is illustrated in the diagram of the formation process in the intermediate stage.

[0013] Figure 15A-1 , Figure 15A-2 and Figure 15A-3 To illustrate according to the embodiments herein Figure 14 A top view of the memory device in the image, taken along a section of line A-A'.

[0014] Figure 15B-1 , Figure 15B-2 and Figure 15B-3 To illustrate according to the embodiments herein Figure 14 A top view of the memory device along the B-B' line;

[0015] Figure 18A To illustrate the formation of a system comprising, according to the embodiments herein. Figure 1B Flowchart of a method for integrating memory devices; Figure 18B For Figure 18A Integrated circuits formed using the methods described above;

[0016] Figure 19A To illustrate the formation of a system comprising, according to the embodiments herein. Figure 1B A flowchart of a method for integrating memory devices in a computer. Figure 19B For Figure 19A Integrated circuits formed using the methods described above;

[0017] Figure 20A To illustrate the circuit diagram of a memory device having transistors and capacitors according to the embodiments herein;

[0018] Figure 20B To illustrate according to the embodiments herein Figure 20A Cross-sectional view of the memory device;

[0019] Figure 21A and Figure 21B A flowchart illustrating a method for forming a memory device having transistors and capacitors, according to embodiments herein;

[0020] Figures 22 to 41 and Figures 43 to 44 According to the embodiments herein, a memory device having transistors and capacitors is described as follows: Figure 21A and Figure 21B The method described is illustrated in the diagram of the formation process in the intermediate stage.

[0021] Figure 42A-1 , Figure 42A-2 and Figure 42A-3 To illustrate according to the embodiments herein Figure 41 A top view of the memory device in the image, taken along a section of line A-A'.

[0022] Figure 42B-1 , Figure 42B-2 and Figure 42B-3To illustrate according to the embodiments herein Figure 41 A top view of the memory device along the B-B' line;

[0023] Figure 45A To illustrate the formation of a system comprising, according to the embodiments herein. Figure 20B Flowchart of a method for integrating memory devices; Figure 45B For Figure 45A Integrated circuits formed using the methods described above;

[0024] Figure 46A To illustrate the formation of a system comprising, according to the embodiments herein. Figure 20B A flowchart of a method for integrating memory devices in a computer. Figure 46B For Figure 46A Integrated circuits formed using the methods described in the article.

[0025] [Symbol Explanation]

[0026] 100: Memory device

[0027] 101: Bonding substrate

[0028] 102:Substrate

[0029] 104: Transistor device

[0030] 104a: Channel Area

[0031] 104b: Source / Drain Region

[0032] 106a: Gate dielectric layer

[0033] 106b: Gate electrode

[0034] 107: Straight-through conductive post

[0035] 108: Metal wire

[0036] 109: Spacers

[0037] 110: Dielectric layer / First dielectric layer

[0038] 112: Conductive layer

[0039] 114: Semiconductor layer

[0040] 115: Insulation layer / First insulation layer

[0041] 117: Second Insulation Layer

[0042] 120: Second dielectric layer

[0043] 121: Trench

[0044] 130: Third dielectric layer

[0045] 131: First conductive post trench

[0046] 132: First conductive post

[0047] 140: Fourth dielectric layer

[0048] 141: Second conductive post trench

[0049] 142: Second conductive post

[0050] 151: Third conductive post trench

[0051] 152: Third conductive post

[0052] 200: Method

[0053] 202: Operation

[0054] 204: Operation

[0055] 206: Operation

[0056] 208: Operation

[0057] 210: Operation

[0058] 212: Operation

[0059] 214: Operation

[0060] 216: Operation

[0061] 218: Operation

[0062] 220: Operation

[0063] 221: Trench

[0064] 222: Operation

[0065] 223: Opening

[0066] 224: Operation

[0067] 225: Semiconductor trench

[0068] 226: Operation

[0069] 228: Operation

[0070] 230: Operation

[0071] 232: Operation

[0072] 300: Method

[0073] 302: Operation

[0074] 304: Operation

[0075] 306: Operation

[0076] 308: Operation

[0077] 310: Operation

[0078] 312: Operation

[0079] 314: Operation

[0080] 316: Operation

[0081] 318: Operation

[0082] 320: Operation

[0083] 322: Operation

[0084] 324: Operation

[0085] 326: Operation

[0086] 328: Operation

[0087] 330: Operation

[0088] 332: Operation

[0089] 334: Operation

[0090] 336: Operation

[0091] 338: Operation

[0092] 340: Operation

[0093] 342: Operation

[0094] 406: Gate Stack

[0095] 501: Transistor

[0096] 501a: Part 1

[0097] 501b: Part Two

[0098] 502: First source / drain characteristics

[0099] 504: Second source / drain characteristics

[0100] 505: Channel

[0101] 506: Gate

[0102] 508: Capacitor

[0103] 508a: Electrode

[0104] 508b: Insulation layer

[0105] 508c: Electrode

[0106] 606: Gate

[0107] 1000: Integrated Circuits

[0108] 1100: First inner connection structure

[0109] 1200: Second inner connection structure

[0110] 1300: Third Inner Connection Structure

[0111] 2000: Method

[0112] 2002: Operation

[0113] 2004: Operation

[0114] 2006: Operation

[0115] 2008: Operation

[0116] 3000: Method

[0117] 3002: Operation

[0118] 3004: Operation

[0119] 3006: Operation

[0120] 3008: Operation

[0121] 4000: Method

[0122] 4002: Operation

[0123] 4004: Operation

[0124] 4006: Operation

[0125] 4008: Operation

[0126] 4010: Operation

[0127] 4012: Operation

[0128] 5000: Method

[0129] 5002: Operation

[0130] 5004: Operation

[0131] 5006: Operation

[0132] 5008: Operation

[0133] 5010: Operation

[0134] 5012: Operation

[0135] X1: Width

[0136] X2: Width Detailed Implementation

[0137] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0138] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0139] Additionally, when numbers or numerical ranges are described using the word "about," it indicates, to a person skilled in the art, an exact interval within which the relevant numerical range described in the specification and claims is defined. Generally, such an exact interval is ±10%. For example, "about 5 nanometers" might cover a dimensional range from 4.5 nanometers to 5.5 nanometers. Furthermore, when comparing the dimension or scale of one feature with another, terms such as "substantially the same," "essentially the same," "of similar size," and other similar expressions can be interpreted to a person skilled in the art as falling within ±10% of the compared features. Moreover, the dimension of different features may imply a dimensional ratio between the different features.

[0140] This document discloses a method and structure for forming a memory device with a vertically stacked transistor and capacitor structure. The transistor is a vertical gate all-around (GAA) transistor with a gate horizontally covering a channel, which is vertically located between the source and drain. The capacitor structure is vertically stacked directly above the source or drain of the transistor, thereby reducing the passive element area of ​​the device and increasing the device density. In one embodiment, the capacitor structure is vertically stacked above the transistor. In another embodiment, the capacitor structure is vertically stacked below the transistor. In either example, the memory device may be bonded to the front or back side of a larger semiconductor structure. For example, the memory device may be bonded between metal lines within a front-side interconnect structure located above a logic element. As another example, the memory device may be bonded to the back side of the logic element and connected to a back-side interconnect structure.

[0141] Figure 1A This diagram illustrates a memory device 100 having a transistor 501 and a capacitor 508. The transistor 501 has a first terminal corresponding to a first source / drain feature 502, a second terminal corresponding to a second source / drain feature 504, and a third terminal corresponding to a gate 506. The gate 506 controls a channel located between the first source / drain feature 502 and the second source / drain feature 504. The gate 506 is electrically connected to a word line of the memory device 100. The first source / drain feature 502 (e.g., the first terminal of the transistor 501) is electrically connected to a bit line of the memory device 100, and the second source / drain feature 504 (e.g., the second terminal of the transistor 501) is first electrically connected to the capacitor 508 and then electrically connected to ground. In one embodiment, the first source / drain feature 502 may be a drain, and the second source / drain feature 504 may be a source. In this example, the drain of transistor 501 is connected to a bit line, the source of transistor 501 is connected to a first terminal (or electrode) of capacitor 508, and the second terminal (or electrode) of capacitor 508 is connected to a ground line. In other embodiments, the first source / drain feature 502 may be a source, and the second source / drain feature 504 may be a drain. In this example, the source of transistor 501 is connected to a bit line, the drain of transistor 501 is connected to a first terminal (or electrode) of capacitor 508, and the second terminal (or electrode) of capacitor 508 is connected to a ground line. The bit line, word line, and ground line may be different conductive layers, and these conductive layers may be connected to other transistors 501 and other capacitors 508 in other memory devices 100. In one embodiment, the bit line, word line, and ground line are metal lines in a metal interconnect structure, and these lines are connected to different memory devices 100 in a memory array.

[0142] According to one embodiment disclosed herein, Figure 1B for Figure 1ACross-sectional view of the memory device 100. Figure 1A The features described in the text are similar to those marked in the text. Figure 1B In the middle. It should be noted that... Figure 1B More details on the additional features will be available later. Figure 2A and Figure 2B Method 200 is presented, and the formation of memory device 100 will be... Figures 3 to 14 and Figures 16 to 17 Presented in the middle.

[0143] Figure 1B The transistor 501 shown (also referred to as semiconductor feature 501) has different portions, which may be a source, a drain, and a channel. Semiconductor feature 501 may be made of a compound semiconductor material. In one embodiment, the compound semiconductor material comprises indium gallium zinc oxide (IGZO). In other embodiments, the compound semiconductor material comprises oxygen and at least two of the following three materials: indium, gallium, and zinc. In yet another embodiment, semiconductor feature 501 may comprise hafnium oxide (HfO2). In one embodiment, semiconductor feature 501 is selected to have high mobility in polycrystalline silicon or amorphous materials. In other words, semiconductor feature 501 does not have a crystalline structure but has an amorphous or polycrystalline silicon structure. As described above, semiconductor feature 501 does not need to be formed on a semiconductor layer, such as silicon, but may be formed on a conductive layer, such as titanium nitride.

[0144] Please refer to the following: Figure 1B A gate 506 is horizontally positioned around a vertical channel 505 that covers the semiconductor feature 501. In this cross-sectional view, the gate 506 is deposited on the sidewall of the channel 505. Source / drain features 502 and 504 of the semiconductor feature 501 are vertically positioned above and below the channel 505. In other words, the semiconductor feature 501 includes a first portion (such as a second source / drain feature 504) above a second portion (such as the channel 505), and a second portion (such as the channel 505) above a third portion (such as a first source / drain feature 502). The second portion (such as the channel 505) extends vertically and lies between the first portion (such as the second source / drain feature 504) and the third portion (such as the first source / drain feature 502). As described above, a capacitor 508 directly contacts and horizontally surrounds the first portion (such as the second source / drain feature 504) that covers the semiconductor feature 501. In this example, the capacitor 508 is vertically stacked above the semiconductor feature 501. Further details are as follows: the first source / drain feature 502 may be electrically connected to the bit line through the bit line conductive post, the capacitor 508 may be electrically connected to the ground line through the ground line conductive post, and the gate 506 may be electrically connected to the word line through the word line conductive post.

[0145] According to one embodiment disclosed herein, Figure 2A and Figure 2B A flowchart of a method 200 for forming a memory device 100 having a transistor 501 and a capacitor 508. According to an embodiment disclosed herein, Figures 3 to 14 and Figures 16 to 17 This is a schematic diagram illustrating the formation of memory device 100 at an intermediate stage of the manufacturing process, and the formation process is as follows: Figure 2A and Figure 2B As shown in Method 200. For a detailed description of Method 200, please refer to [link to Method 200]. Figures 3 to 14 and Figures 16 to 17 .

[0146] Please see Figure 3 In method 200, operation 202 involves forming a conductive layer 112 over the dielectric layer 110 (or the first dielectric layer 110). The dielectric layer 110 may be an interlayer dielectric (ILD), and a memory device 100 is formed thereon. The dielectric layer 110 comprises a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, an oxide formed of tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), a low dielectric constant material, other suitable dielectric materials, or any combination thereof. In one embodiment, the dielectric layer 110 comprises silicon dioxide or a low dielectric constant material. The conductive layer 112 may comprise a suitable conductive material, such as titanium nitride. The conductive layer 112 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes.

[0147] Please see Figure 3 In method 200, operation 204 involves forming a semiconductor layer 114 over the conductive layer 112. The semiconductor layer 114 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD). The semiconductor layer 114 may be made of a compound semiconductor material. In one embodiment, the compound semiconductor material comprises indium gallium zinc oxide (IGGaZ). In other embodiments, the compound semiconductor material comprises oxygen and at least two of three materials: indium, gallium, and zinc. In one embodiment, the semiconductor layer 114 is selected to have high mobility in polycrystalline silicon or amorphous materials. As described above, the semiconductor layer 114 may be formed over the conductive layer 112 without necessarily being formed over the semiconductor layer, such as silicon. This is because with the selected material (such as IGGaZ), the semiconductor layer 114 does not need to form a single-crystal silicon structure but requires crystal growth on the semiconductor layer, such as silicon. Although not mandatory, selective doping may be performed in the semiconductor layer 114 to reduce oxygen deficiency and improve channel effects. For example, a high doping concentration (such as gallium) is introduced into the top and bottom portions of semiconductor layer 114. These top and bottom portions then form source / drain features embedded in the channels of the transistor device.

[0148] Please see Figure 4 In method 200, operation 206 involves patterning the semiconductor layer 114 to form a semiconductor feature 501. The semiconductor feature 501 may be formed using a patterning process including lithography and etching processes. In one embodiment, a lithography process is performed to form a patterned mask layer to cover a portion of the semiconductor layer 114, and an etching process is performed using the patterned mask layer as an etching mask. The semiconductor feature 501 includes a first portion 501a over a second portion 501b. The second portion 501b is wider than the first portion 501a. In one embodiment, the semiconductor feature 501 is inverted T-shaped, wherein the narrower first portion 501a extends upwardly from the wider second portion 501b.

[0149] Please see Figure 5 In method 200, operation 208 forms a gate stack 406 over semiconductor feature 501 using a suitable deposition process. The gate stack 406 includes a gate dielectric layer 106a and a gate electrode 106b located above the gate dielectric layer 106a. The gate dielectric layer 106a may contain a high-dielectric-coefficient material, and the gate electrode 106b may contain a suitable conductive material such as titanium nitride. The high-dielectric-coefficient material may contain hafnium oxide, zirconium oxide, titanium oxide, silicon oxynitride, or other suitable dielectric materials. In some embodiments (not shown), each of the gate dielectric layer 106a and the gate electrode 106b may contain multiple sublayers. See also... Figure 5 The gate stack 406 may be conformally deposited over the semiconductor feature 501. As shown, the gate dielectric layer 106a is located on the upper and side surfaces of the semiconductor feature 501. Subsequently, the gate electrode 106b is located on the upper and side surfaces of the gate dielectric layer 106a.

[0150] Please see Figure 6 In method 200, operation 210 forms a second dielectric layer 120 over the gate stack 406 using a suitable deposition process. The second dielectric layer 120 may contain a material similar to that of dielectric layer 110.

[0151] Please see Figure 7 In method 200, operation 212 etches through the second dielectric layer 120, the gate electrode 106b, and the second portion 501b of the semiconductor feature 501 to form a trench 121 exposing the location portion of the conductive layer 112. The trench 121 may be formed using a patterning process including lithography and etching processes. In one embodiment, a lithography process is performed to form a patterned mask layer covering the second dielectric layer 120, and an etching process is performed using the patterned mask layer as an etching mask.

[0152] Please see Figure 8In method 200, operation 214 reshapes the second dielectric layer 120 by filling trench 121 with a dielectric material. In embodiments herein, the dielectric material comprises a material similar to that of the second dielectric layer 120. The dielectric material may be deposited in the trench 121 using any suitable process. In one embodiment, operation 214 further includes a planarization process, such as chemical mechanical planarization (CMP), to planarize the upper surface of the reshaped second dielectric layer 120.

[0153] Please see Figure 9 In method 200, operation 216 performs a pullback etch on the second dielectric layer 120. The pullback etch exposes the top layer portion of the gate stack 406. At this point, the second dielectric layer 120 surrounds and embeds the lower portion of the gate stack 406 (which subsequently becomes the gate 506), and the second dielectric layer 120 directly contacts the lower portion of the gate stack 406 and the semiconductor feature 501 (or specifically, the second portion 501b of the semiconductor feature 501).

[0154] Please see Figure 10 In method 200, operation 218 etches the top layer portion of the gate stack 406 to expose the top layer portion of the semiconductor feature 501. Specifically, regarding semiconductor feature 501, the top layer portion of the first portion 501a is exposed, while the bottom layer portion of the first portion 501a and the second portion 501b remain covered. When etching the top layer portion of the gate stack 406, the second dielectric layer 120 may serve as an etch stop layer and an etch mask. The remaining portion of the gate stack 406 forms the gate 506. Figure 1A and Figure 1B The semiconductor feature 501 can function as a transistor 501 and includes portions such as a source, a drain, and a channel. After forming the gate 506, the source, drain, and channel portions of the semiconductor feature 501 are defined. For example, the semiconductor feature 501 includes a first source / drain feature 502, which can be the drain (or source) of the semiconductor feature 501. The semiconductor feature 501 includes a second source / drain feature 504, which can be the source (or drain) of the semiconductor feature 501. The semiconductor feature 501 also includes a channel 505 vertically located between the first source / drain feature 502 and the second source / drain feature 504, which can be a channel of the semiconductor feature 501. Figure 10As shown, the gate 506 horizontally surrounds and covers the channel 505. The channel 505 is a vertical channel with source and drain portions located above and / or below it. The first source / drain feature 502 may be the second portion 501b of the semiconductor feature 501, the channel 505 may be the bottom portion of the first portion 501a of the semiconductor feature 501, and the second source / drain feature 504 may be the top portion of the first portion 501a of the semiconductor feature 501. The first source / drain feature 502 is directly situated on the conductive layer 112, and the gate 506 not only surrounds and covers the channel 505 but is also situated on the upper surface of the first source / drain feature 502. The channel 505 is located above the first source / drain feature 502 and below the second source / drain feature 504. In one embodiment, channel 505 and the second source / drain feature 504 have substantially the same width along the X direction because channel 505 and the second source / drain feature 504 are formed in the same patterning step. The first source / drain feature 502 may have a larger width along the X direction than channel 505 and the second source / drain feature 504.

[0155] Please see Figure 11 In method 200, operation 220 forms an insulating layer 115 (or a first insulating layer 115) over the gate 506 and the second dielectric layer 120. The insulating layer 115 may be formed using a directional deposition process such that it is formed only (or substantially) on the upper surfaces of the gate 506, the second dielectric layer 120, and the second source / drain feature 504. A subsequent etch process may be performed on the portion of the insulating layer 115 located on the upper surface of the second source / drain feature 504, and on the top layer portion of the second source / drain feature 504. Thus, the insulating layer 115 is formed as shown, located on the upper surfaces of the gate 506 and the second dielectric layer 120, and on a portion of the side surfaces of the second source / drain feature 504. After the insulating layer 115 is formed, the top layer portion of the second source / drain feature 504 remains exposed. The insulating layer 115 may serve as an etch stop layer comprising silicon nitride. In one embodiment, the insulating layer 115 comprises a dielectric material different from that of the dielectric layer 110 and the second dielectric layer 120 to correspond to the selectivity of the etchant.

[0156] Please see Figures 12 to 13In method 200, operation 222 forms a capacitor 508 above the insulating layer 115 and above the upper and side surfaces of the exposed portion of the top layer of the second source / drain feature 504. The capacitor 508 may be a metal-insulator-metal (MIM) capacitor structure having electrodes 508a and 508c separated by an insulating layer 508b. Electrodes 508a and 508c may contain any suitable conductive material, such as titanium nitride. The insulating layer 508b may contain a high dielectric constant material as mentioned above. Electrode 508a is in direct contact with and located above the second source / drain feature 504 of the semiconductor feature 501, and is located above the insulating layer 115. The capacitor 508 may first be formed with a conformal deposition layer, including electrode 508a, insulating layer 508b, and electrode 508c (e.g., Figure 12 As shown), the subsequent patterning process performs etching on the portion of the deposited layer located above the insulating layer 115 (as shown). Figure 13 (As shown). Capacitor 508 may be located directly on the upper surface of insulating layer 115, and therefore insulating layer 115 is located vertically between capacitor 508 and gate 506, and may be in direct contact with both. Figure 13 As shown, a portion of the insulating layer 115 is exposed. In this embodiment, the capacitor 508 directly contacts and horizontally surrounds the second source / drain feature 504.

[0157] Please see Figure 14 In method 200, operation 224 forms a third dielectric layer 130 over capacitor 508 using a suitable deposition process. The third dielectric layer 130 may contain a material similar to dielectric layer 110 and the second dielectric layer 120. The third dielectric layer 130 covers and embeds capacitor 508. The third dielectric layer 130 directly contacts capacitor 508 (including electrode 508a, insulating layer 508b, and electrode 508c) and directly contacts the upper surface of insulating layer 115. As shown, insulating layer 115 separates the second dielectric layer 120 (first horizontal interlayer dielectric layer) from the third dielectric layer 130 (second horizontal interlayer dielectric layer), and separates gate 506 from capacitor 508. Method 200 forms a memory device 100 having transistor 501 and capacitor 508 located above the transistor. To adjust to a lower capacitance, such as... Figure 14 As shown, the height of the second source / drain feature 504 along the Z-direction may be less than the height of the channel 505 along the Z-direction. In a different embodiment, to achieve a higher capacitance, the height of the second source / drain feature 504 along the Z-direction may be greater than the height of the channel 505 along the Z-direction. In other words, the dimensional height and ratio between the second source / drain feature 504 and the channel 505 may be adjusted to meet the goal of low leakage current and high capacitance density.

[0158] Based on the different embodiments disclosed herein, Figure 14It includes an A-A' line crossing channel 505 and a B-B' line crossing the second source / drain feature 504. Figure 15A-1 , Figure 15A-2 and Figure 15A-3 for Figure 14 A top view of the memory device 100 along the A-A' line. Figure 15B-1 , Figure 15B-2 and Figure 15B-3 for Figure 14 A top view of the memory device 100 along the B-B' line.

[0159] Please see Figure 15A-1 , Figure 15A-2 and Figure 15A-3 In the XY plane, channel 505 may be completely surrounded by gate 506. Gate 506 includes a gate dielectric layer 106a that directly contacts and completely surrounds the channel 505. Gate 506 also includes a gate electrode 106b that directly contacts and completely surrounds the gate dielectric layer 106a. In one embodiment, in the XY plane, channel 505 is circular (see...). Figure 15A-1 In another embodiment, in the XY plane, channel 505 is square (see...). Figure 15A-2 In another embodiment, in the XY plane, channel 505 is rectangular (see...). Figure 15A-3 ).

[0160] Please see Figure 15B-1 , Figure 15B-2 and Figure 15B-3 In the XY plane, the second source / drain feature 504 may be completely surrounded by a capacitor 508. The capacitor 508 includes an electrode 508a that directly contacts and completely surrounds the second source / drain feature 504. The capacitor 508 includes an insulating layer 508b that directly contacts and completely surrounds the electrode 508a. The capacitor 508 also includes an electrode 508c that directly contacts and completely surrounds the insulating layer 508b. Although not shown, the capacitor 508 may include additional interlayer interleaved metal and insulating layers in the electrodes 508a and 508c. In one embodiment, in the XY plane, the second source / drain feature 504 is circular (see...). Figure 15B-1 In another embodiment, in the XY plane, the second source / drain feature 504 is square (see...). Figure 15B-2 In another embodiment, in the XY plane, the second source / drain feature 504 is rectangular. Figure 15B-3 ).

[0161] Figure 15A-1 , Figure 15A-2 and Figure 15A-3 Each one displays the width of channel 505 x 1. Figure 15B-1 , Figure 15B-2 and Figure 15B-3 Each of them displays the width X2 of the second source / drain feature 504. In this embodiment, the widths X1 and X2 of each pair of channels 505 and the second source / drain feature 504 are the same or substantially the same (e.g., Figure 15A-1 X1 and Figure 15B-1 (X2 in the original text is the same or substantially the same). This is because channel 505 and the second source / drain feature 504 are formed in the same patterning step; see the relevant description. Figure 4 (If both are part of Part 1, 501a).

[0162] See Figure 16 In method 200, operation 226 forms a first conductive post trench 131 that penetrates the third dielectric layer 130, the insulating layer 115, and the second dielectric layer 120. The first conductive post trench 131 exposes a portion of the conductive layer 112. The exposed portion of the conductive layer 112 may be... Figure 7 The portion where the intermediate conductive layer 112 is located. The third dielectric layer 130, the insulating layer 115, and the second dielectric layer 120 may be etched in the same or respective etching processes that form the first conductive post trench 131. In one embodiment, the first conductive post trench 131 is etched using different etching parameters when the third dielectric layer 130, the second dielectric layer 125, and the insulating layer 115 are etched.

[0163] See also Figure 16 In method 200, operation 228 forms a second conductive post trench 141 that penetrates the third dielectric layer 130, the insulating layer 115, and the second dielectric layer 120. The second conductive post trench 141 exposes the gate 506. The exposed portion of the gate 506 is the horizontal portion of the gate 506 directly above the first source / drain feature 502. Specifically, the second conductive post trench 141 exposes the horizontal surface of the gate electrode 106b. The trench depth of the second conductive post trench 141 is not the same as that of the first conductive post trench 131. The third dielectric layer 130, the insulating layer 115, and the second dielectric layer 120 may be etched in the same or separate etching processes that form the second conductive post trench 141. In one embodiment, the second conductive post trench 141 is etched using different etching parameters when the third dielectric layer 130, the second dielectric layer 125, and the insulating layer 115 are etched.

[0164] See also Figure 16In method 200, operation 230 forms a third conductive post trench 151 that penetrates the third dielectric layer 130. The third conductive post trench 151 exposes a capacitor 508. The exposed portion of the capacitor 508 is likely the horizontal upper surface of the capacitor 508. Specifically, the third conductive post trench 151 exposes the electrode 508c of the capacitor 508. As shown, the depth of the third conductive post trench 151 may be shallower than that of the first conductive post trench 131 and the second conductive post trench 141. This is because the third conductive post trench 151 does not penetrate the insulating layer 115. To avoid over-etching and damage to the electrode 508c, the third conductive post trench 151 may be formed separately from the first conductive post trench 131 and the second conductive post trench 141. For example, the first conductive post trench 131 and the second conductive post trench 141 may be formed together in a first patterning process including lithography and etching processes, followed by the formation of the third conductive post trench 151 in a second patterning process including lithography and etching processes. In another embodiment, the first conductive post trench 131 and the second conductive post trench 141 may be partially formed in the first patterning process and etched to a first depth. Following the second patterning process, the first conductive post trench 131, the second conductive post trench 141, and the third conductive post trench 151 are formed together in a further etching process, wherein the first conductive post trench 131 and the second conductive post trench 141 are etched to a second depth, exposing the conductive layer 112 and the gate 506, and the third conductive post trench 151 is etched to expose the capacitor 508. In another embodiment, the first conductive post trench 131, the second conductive post trench 141, and the third conductive post trench 151 may all be formed in their respective patterning processes.

[0165] See Figure 17 In method 200, operation 232 forms first conductive pillars 132, second conductive pillars 142, and third conductive pillars 152 in the first conductive pillar trench 131, the second conductive pillar trench 141, and the third conductive pillar trench 151, respectively. These conductive pillars may be formed using any suitable deposition method, such as physical vapor deposition or chemical vapor deposition, to deposit metallic material in the first conductive pillar trench 131, the second conductive pillar trench 141, and the third conductive pillar trench 151. Next, a chemical mechanical planarization process may be performed to remove any overfilled portions of metallic material and planarize the memory device 100 to facilitate the formation of the first conductive pillars 132, the second conductive pillars 142, and the third conductive pillars 152. The metallic material of the first conductive pillars 132, the second conductive pillars 142, and the third conductive pillars 152 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo), or any combination thereof.

[0166] See also Figure 17The first conductive post 132 is directly situated on the conductive layer 112 and is electrically connected to the first source / drain feature 502 of the semiconductor feature 501. The first conductive post 132 may be a bit line conductive post, conducting the circuit to the bit line of the memory device 100. The second conductive post 142 is directly situated on the gate 506, wherein the gate 506 surrounds the channel 505 covering the semiconductor feature 501. The second conductive post 142 may be a word line conductive post, conducting the circuit to the word line of the memory device 100. The third conductive post 152 is directly situated on the capacitor 508 and is electrically connected to the second source / drain feature 504 of the semiconductor feature 501. Specifically, electrode 508c directly contacts the third conductive post 152, and electrode 508a directly contacts the second source / drain feature 504. The third conductive post 152 may be a ground wire conductive post, conducting the circuit to the ground wire of the memory device 100.

[0167] According to the embodiments described herein, Figure 18A Method 2000 forms a system containing Figure 1B (or Figure 17 The flowchart of the integrated circuit 1000 of the memory device 100 in the ) is shown. Figure 18B For Figure 18A The integrated circuit 1000 formed by method 2000 in the example is described. (See also...) Figure 18A and Figure 18B Method 2000, operation 2002, forms a transistor device 104 over a substrate 102. The transistor device 104 may differ from the aforementioned memory device 100. In one embodiment, the transistor device 104 is a logic element. Each of the transistor devices 104 includes a channel region 104a between a source / drain region 104b. The channel region 104a and the source / drain region 104b may be portions of an active element region over the substrate 102. Each of the transistor devices 104 includes a gate 606 over the channel region 104a. The transistor device 104 may be a planar device (as shown) or may be a FinFET or a Gate All-Around (GAA) field-effect transistor.

[0168] Referring to operation 2004, method 2000 forms a first interconnect structure 1100 above the transistor device. The first interconnect structure 1100 includes metal contacts such as source / drain contacts, gate contacts (not shown), wherein the source / drain contacts and gate contacts are located in the source / drain region 104b and the gate 606, respectively; conductive pillars such as source / drain conductive pillars, gate conductive pillars located on the metal contacts (not shown); and metal lines 108 situated and electrically connected to the plurality of metal contacts and conductive pillars. The plurality of metal contacts, conductive pillars, and metal lines of the first interconnect structure 1100 may be covered or embedded in an interlayer dielectric layer. Referring to operation 2006, method 2000 forms a vertical gate all-around memory device 100 above the first interconnect structure 1100. The vertical gate all-around memory device 100 may be formed using the aforementioned method 200. In one embodiment, memory device 100 is formed above dielectric layer 110 and above first interconnect structure 1100. Dielectric layer 110 may cover memory device 100 and embed other features such as through conductive pillars 107. Referring to operation 2008, method 2000 forms second interconnect structure 1200 over memory device 100 with vertical gates fully surrounding it. Second interconnect structure 1200 includes different metal lines 108 electrically connected to memory device 100. For example, multiple metal lines 108 may be located on first conductive pillar 132, second conductive pillar 142, and third conductive pillar 152. Metal lines 108 are subsequently connected to metal lines 108 on higher layers as additional lines. Multiple metal lines 108 in second interconnect structure 1200 may be located on through conductive pillars 107 that bypass memory device 100 to be located on metal lines 108 in first interconnect structure 1100.

[0169] like Figure 18A and Figure 18B As stated and displayed, Figure 1B (or Figure 17The memory device 100 in the memory device 100 may be embedded and sandwiched between a plurality of metal lines 108. These metal lines 108, whether in the first interconnect structure 1100 or the second interconnect structure 1200, are front-side metal lines formed above the transistor device 104. In some embodiments, due to the increased density efficiency of the memory device 100, the vertical distance between each of the metal lines 108 sandwiched within the memory device 100 is approximately the same as the vertical distance between each of the metal lines 108 not sandwiched within any memory device 100. In other embodiments, the distance between each of the metal lines 108 sandwiched within the memory device 100 is greater than the distance between each of the metal lines 108 not sandwiched within any memory device 100. It should be noted that different memory devices 100 may be configured between different metal lines 108. In one embodiment, the formed integrated circuit 1000 may include a plurality of vertical gate all-around transistors for the memory device 100 and a plurality of horizontal gate all-around transistors for logic elements (such as the transistor device 104). That is, the memory device 100 has a vertical channel with a gate electrode horizontally covered, and a logic element (such as a transistor device 104) with a horizontal channel with a gate electrode vertically covered.

[0170] According to other embodiments disclosed herein, Figure 19A Method 4000 forms an integrated circuit 1000 comprising Figure 1B (or Figure 17 The flowchart of the memory device 100 in ) . Figure 19B for Figure 19A Integrated circuit 1000 formed by Chinese method 4000. (See also...) Figure 19A and Figure 19B Method 4000, operation 4002, forms a transistor device 104 over a substrate (not shown in the figure). The transistor device 104 may differ from the aforementioned memory device 100. In one embodiment, the transistor device 104 is a logic element. Each of the transistor devices 104 includes a channel region 104a between source / drain regions 104b. In one illustrated embodiment, the channel region 104a may include a stack of multiple channel layers connecting the source / drain regions 104b. Each of the transistor devices 104 includes a gate 606 over the channel region 104a. However, as... Figure 19BAs shown, after the circuit structure is flipped in operation 4006, gate 606 is positioned below channel region 104a. Gate 606 may include a gate dielectric and a gate electrode, and gate 606 may have portions that vertically surround and cover multiple channel layers. Each of transistor devices 104 may include spacers 109, such as gate spacers, inner spacers, or insulating layers that insulate other channel layers, gate structures, and other associated surrounding features. In some embodiments, spacers 109 comprise a dielectric material, wherein the dielectric material comprises silicon, oxygen, carbon, nitrogen, other suitable materials, or any combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the spacer layer comprises a low dielectric constant material. Transistor device 104 may be a gate-all-around field-effect transistor as shown, or may be a planar device or a fin field-effect transistor (FinFET).

[0171] Referring to operation 4004, method 4000 forms a first internal connection structure 1100 above the transistor device 104, thereby forming a circuit structure having the first internal connection structure 1100 and the transistor device 104. It should be noted that... Figure 19BThe first interconnect structure 1100 is shown below the transistor device 104. This is because the circuit structure is flipped downwards in a subsequent manufacturing stage. The first interconnect structure 1100 includes metal contacts, such as source / drain contacts and gate contacts (not shown), located in the source / drain region 104b and gate 606, respectively. Conductive pillars, such as source / drain conductive pillars and gate conductive pillars (not shown), are located on the metal contacts, and metal lines 108 are situated and electrically connected to multiple metal contacts and conductive pillars. The multiple metal contacts, conductive pillars, and metal lines of the first interconnect structure 1100 may be covered or embedded in an interlayer dielectric layer. Referring to operation 4006, method 4000 flips the circuit structure and transistor device 104 having the first interconnect structure 1100 and performs a thinning process on the back side of the circuit structure. Operation 4006 may include forming a bonding substrate 101 for structural strength over the first interconnect structure 1100, then flipping the entire working element, and performing a thinning process to remove the portion of the transistor device 104 previously formed over the circuit structure. Referring to operation 4008, method 4000 forms a second interconnect structure 1200 over the back side of the circuit structure (from this point onwards, the flipped structure). The second interconnect structure 1200 includes various metal lines 108 electrically connected to the transistor device 104. For example, the plurality of metal lines 108 may include back-side conductive pillars located from the back side of the source / drain regions 104b of the transistor device 104, and back-side conductive lines located on the back-side conductive pillars. These back-side conductive lines may also be referred to as back-side power rails for power routing from the back side of the transistor device 104. These metal lines 108 then further connect the circuit to metal lines 108 in a third interconnect structure. Referring to operation 4010, method 4000 forms a vertical gate all-around memory device 100 over a second interconnect structure 1200. The vertical gate all-around memory device 100 may be formed using the aforementioned method 200. In some embodiments, the memory device 100 is formed over a dielectric layer 110 over the second interconnect structure 1200. The dielectric layer 110 may cover the memory device 100 and embed other features such as through-conductive pillars 107. Referring to operation 4012, method 4000 forms a third interconnect structure 1300 over the vertical gate all-around memory device 100. As described above, the vertical gate all-around memory device 100 is formed between the back-side power rail in the second interconnect structure 1200 and the metal circuit lines in the third interconnect structure 1300. The third interconnect structure 1300 includes a plurality of metal lines 108 electrically connected to the memory device 100. For example, multiple metal wires 108 may be located on the first conductive post 132, the second conductive post 142, and the third conductive post 152. These metal wires 108 are subsequently connected to metal wires 108 at higher levels as additional lines.In the third internal connection structure 1300, multiple metal lines 108 may be located on the through conductive post 107, which bypasses the memory device 100 to be located in the metal lines 108 in the second internal connection structure 1200.

[0172] like Figure 19A and Figure 19B As stated and displayed, Figure 1B (or Figure 17 The memory device 100 may be embedded and sandwiched between a plurality of metal lines 108. These metal lines 108 are back-side metal lines formed on the back side of the transistor device 104. In some embodiments, due to the increased density efficiency of the memory device 100, the vertical distance between each of the metal lines 108 sandwiched therein by the memory device 100 is approximately the same as the vertical distance between each of the metal lines 108 in which no memory device 100 is sandwiched. In other embodiments, the distance between each of the metal lines 108 sandwiched therein by the memory device 100 is greater than the distance between each of the metal lines 108 in which no memory device 100 is sandwiched. It should be noted that different memory devices 100 may be configured between different metal lines 108. In one embodiment, the formed integrated circuit 1000 may include a plurality of vertical gate all-around transistors for the memory device 100 and a plurality of horizontal gate all-around transistors for logic elements (such as the transistor device 104). That is, the memory device 100 has a vertical channel with the gate electrode horizontally covered, and the logic element (such as the transistor device 104) has a vertical channel with the gate electrode vertically covered.

[0173] Figure 20A This is a circuit diagram of a memory device 100 having a transistor 501 and a capacitor 508. Figure 20A The circuit diagram and Figure 1AThe circuit diagram is similar to that in the figure. As shown, transistor 501 has a first terminal corresponding to a first source / drain feature 502, a second terminal corresponding to a second source / drain feature 504, and a third terminal corresponding to a gate 506. Gate 506 controls a channel located between the first source / drain feature 502 and the second source / drain feature 504. Gate 506 is electrically connected to a word line of memory device 100. The first source / drain feature 502 (such as the first terminal of transistor 501) is electrically connected to a bit line of memory device 100, and the second source / drain feature 504 (such as the second terminal of transistor 501) is electrically connected to a capacitor 508, and then electrically connected to a ground line. In one embodiment, the first source / drain feature 502 may be a drain, and the second source / drain feature 504 may be a source. In this example, the drain of transistor 501 is connected to a bit line, the source of transistor 501 is connected to a first terminal (or electrode) of capacitor 508, and the second terminal (or electrode) of capacitor 508 is connected to a ground line. In other embodiments, the first source / drain feature 502 may be a source, and the second source / drain feature 504 may be a drain. In this example, the source of transistor 501 is connected to a bit line, the drain of transistor 501 is connected to a first terminal (or electrode) of capacitor 508, and the second terminal (or electrode) of capacitor 508 is connected to a ground line. The bit line, word line, and ground line may be different conductive layers, and these conductive layers may be connected to other transistors 501 and other capacitors 508 in other memory devices 100. In one embodiment, the bit line, word line, and ground line are metal lines in a metal interconnect structure, and these lines are connected to different memory devices 100 in a memory array.

[0174] According to one embodiment disclosed herein, Figure 20B for Figure 20A Cross-sectional view of the memory device 100. Figure 20A The features described in the text are similar to those marked in the text. Figure 20B In the middle. It should be noted that... Figure 20B More details on the additional features will be available later. Figure 21A and Figure 21B Method 300 is presented, and the formation of memory device 100 will be... Figures 22 to 43 and Figures 45A to 46B Presented in the middle. It should be noted that... Figure 20B The memory device 100 in the middle has a similar Figure 1B The memory devices in the memory have 100 different structures. Figure 1B In the middle, capacitor 508 is vertically deposited above channel 505 of transistor 501, while Figure 20B In the middle, capacitor 508 is vertically deposited below channel 505 of transistor 501.

[0175] Figure 20BThe transistor 501 shown (also referred to as semiconductor feature 501) has different portions, which may be a source, a drain, and a channel. Semiconductor feature 501 may be made of a compound semiconductor material. In one embodiment, the compound semiconductor material comprises indium gallium zinc oxide (IGZO). In other embodiments, the compound semiconductor material comprises oxygen and at least two of the following three materials: indium, gallium, and zinc. In yet another embodiment, semiconductor feature 501 may comprise hafnium oxide (HfO2). In one embodiment, semiconductor feature 501 is selected to have high mobility in polycrystalline silicon or amorphous materials. In other words, semiconductor feature 501 does not have a crystalline structure but has an amorphous or polycrystalline silicon structure. As described above, semiconductor feature 501 does not need to be formed on a semiconductor layer, such as silicon, but may be formed on a conductive layer, such as titanium nitride.

[0176] Please refer to the following: Figure 20B A gate 506 is horizontally positioned around a channel 505 that covers the semiconductor feature 501. In this cross-sectional view, the gate 506 is deposited on the sidewall of the channel 505. Source / drain features 502 and 504 of the semiconductor feature 501 are vertically positioned above and below the channel 505. In other words, the semiconductor feature 501 includes a first portion (such as the first source / drain feature 502) above a second portion (such as the channel 505), and a second portion (such as the channel 505) above a third portion (such as the second source / drain feature 504). The second portion (such as the channel 505) extends vertically and lies between the first portion (such as the first source / drain feature 502) and the third portion (such as the second source / drain feature 504). As described above, a capacitor 508 directly contacts and horizontally surrounds the third portion (such as the second source / drain feature 504) that covers the semiconductor feature 501. In this example, the capacitor 508 is vertically stacked below the semiconductor feature 501. Further details are as follows: the first source / drain feature 502 may be electrically connected to the bit line through the bit line conductive post, the capacitor 508 may be electrically connected to the ground line through the ground line conductive post, and the gate 506 may be electrically connected to the word line through the word line conductive post.

[0177] According to one embodiment disclosed herein, Figure 21A and Figure 21B A flowchart of a method 300 for forming a memory device 100 having a transistor 501 and a capacitor 508. According to an embodiment disclosed herein, Figures 22 to 41 and Figures 43 to 44 This is a schematic diagram illustrating the formation of memory device 100 at an intermediate stage of the manufacturing process, and the formation process is as follows: Figure 21A and Figure 21B As shown in Method 300. For a detailed description of Method 300, please refer to [link to Method 300]. Figures 22 to 41 and Figures 43 to 44 .

[0178] Please see Figure 22 In method 300, operation 302 involves forming trenches 221 over dielectric layer 110 (or the first dielectric layer 110) using a suitable patterning process. Dielectric layer 110 may be an interlayer dielectric (ILD), and a memory device 100 will be formed thereon. Dielectric layer 110 comprises a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, an oxide formed of tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), a low dielectric constant material, other suitable dielectric materials, or any combination thereof. In one embodiment, dielectric layer 110 comprises silicon dioxide or a low dielectric constant material.

[0179] Please see Figure 23 In method 300, operation 304 forms a capacitor 508 in trench 221, and the capacitor 508 partially fills the trench 221. The capacitor 508 may be a metal-insulator-metal (MIM) capacitor structure having electrodes 508a and 508c separated by an insulating layer 508b. Electrodes 508a and 508c may contain any suitable conductive material, such as titanium nitride. The insulating layer 508b may contain a high dielectric constant material as mentioned above. Electrode 508a directly contacts and is located on the surface of dielectric layer 110 along trench 221 and on the upper surface of dielectric layer 110. The capacitor 508 may be formed as a conformal deposition layer, including electrode 508a, insulating layer 508b, and electrode 508c. In a subsequent stage, a patterning process may perform etching (e.g., on the portion of the electrode 508c and insulating layer 508b deposition layer) on the electrode 508c and insulating layer 508b deposition layer. Figure 26 (As shown).

[0180] Please see Figures 24 to 25 In method 300, operation 306 forms a second dielectric layer 120 above the remaining portion of the capacitor 508 in the filled trench 221. Operation 306 may involve depositing dielectric material into the trench 221 using a suitable deposition process. It should be noted that the dielectric material fills beyond the trench (e.g., ...). Figure 24 (As shown). Next, a planarization process, such as chemical mechanical planarization, is performed to planarize the upper surface of capacitor 508 and the deposited dielectric material (e.g., Figure 25 (As shown). The deposited dielectric material forms a second dielectric layer 120, and the second dielectric layer 120 may contain a material similar to that of dielectric layer 110.

[0181] See Figure 26 In method 300, operation 308 partially etches through capacitor 508 to form opening 223 to expose the metal layer of capacitor 508 (such as electrode 508a). For example, a suitable patterning process is performed to etch portions of electrode 508c and insulating layer 508b deposition layer to expose portions of electrode 508a.

[0182] Please see Figures 27 to 28 In method 300, operation 310 reshapes the second dielectric layer 120. Operation 306 may involve depositing dielectric material of the second dielectric layer 120 on the opening 223, capacitor 508, and above the upper surface of the second dielectric layer 120 (e.g., Figure 27 (As shown). Next, a planarization process, such as chemical mechanical planarization, is performed to planarize the capacitor 508 and the upper surface of the deposited dielectric material (e.g., Figure 28 As shown, the second dielectric layer 120 includes a portion located within the opening 223 and a portion located within the trench 221. The second dielectric layer 120 is substantially on the same plane as the top surface of the capacitor 508 (such as electrode 508c).

[0183] Please see Figure 29 In method 300, operation 312 forms an insulating layer 115 (or a first insulating layer 115) over capacitor 508 and second dielectric layer 120. The insulating layer 115 may be formed using any suitable deposition process. The insulating layer 115 may serve as an etch stop layer comprising silicon nitride. In one embodiment, the insulating layer 115 comprises a dielectric material different from that of dielectric layer 110 and second dielectric layer 120 to correspond to the selectivity of the etchant.

[0184] See Figure 30 In method 300, operation 314 forms a semiconductor trench 225 penetrating the insulating layer 115 and the second dielectric layer 120 to expose the capacitor 508. The semiconductor trench 225 may be formed using a suitable patterning process including lithography and etching processes. For example, a lithography process is performed to form a patterned mask layer to cover a portion of the insulating layer 115, and an etching process is performed using the patterned mask layer as an etching mask. The etching process may include a first etching process etching the insulating layer 115 and a second etching process etching the second dielectric layer 120. In one embodiment, the etching process etches both the insulating layer 115 and the second dielectric layer 120 in the same etching process. The etching process etches the second dielectric layer 120 in the trench 221, thereby exposing the electrode 508c of the capacitor 508.

[0185] See Figure 31In method 300, operation 316 involves forming a semiconductor layer 114 in a semiconductor trench 225 and over a first insulating layer 115. A portion of the semiconductor layer 114 in the semiconductor trench 225 is in direct contact with and horizontally covered by a capacitor 508. The semiconductor layer 114 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD). The semiconductor layer 114 may be made of a compound semiconductor material. In one embodiment, the compound semiconductor material comprises indium gallium zinc oxide (IGNOW). In other embodiments, the compound semiconductor material comprises oxygen and at least two of the following three materials: indium, gallium, and zinc. In one embodiment, the semiconductor layer 114 is selected to have high mobility in polycrystalline silicon or amorphous materials. In another embodiment, the semiconductor layer 114 may comprise hafnium oxide (HfO2). In one embodiment, the semiconductor layer 114 is selected to have high mobility in polycrystalline silicon or amorphous materials. That is, the semiconductor layer 114 can be formed on top of the capacitor 508 (such as electrode 508c) instead of on a semiconductor layer such as silicon. This is because, with the chosen material (such as indium gallium zinc oxide), the semiconductor layer 114 does not need to form a single-crystal silicon structure, but rather requires crystal growth on a semiconductor layer, such as silicon. While not mandatory, selective doping may be performed in the semiconductor layer 114 to reduce oxygen deficiency and enhance channel effects. For example, high doping concentrations (such as gallium) can be introduced into the top and bottom portions of the semiconductor layer 114. These top and bottom portions then form source / drain features embedded in the vertical channels of the transistor device.

[0186] See Figure 32 In method 300, operation 318 is to pattern the semiconductor layer 114 to form a semiconductor feature 501. The semiconductor feature 501 may be formed using a patterning process including lithography and etching processes. In one embodiment, a lithography process is performed to form a patterned mask layer to cover a portion of the semiconductor layer 114, and an etching process is performed using the patterned mask layer as an etching mask. The semiconductor feature 501 includes a first portion 501a located above a second portion 501b. In one embodiment, the first portion 501a is wider than the second portion 501b, but in other embodiments, the first portion 501a may be narrower than the second portion 501b. In the illustrated embodiment, the first portion 501a is wider and sits on the upper surface of the first insulating layer 115.

[0187] Please see Figure 33In method 300, operation 320 forms a gate stack 406 over semiconductor feature 501 using a suitable deposition process. The gate stack 406 includes a gate dielectric layer 106a and a gate electrode 106b located above the gate dielectric layer 106a. The gate dielectric layer 106a may contain a high-dielectric-coefficient material, and the gate electrode 106b may contain a suitable conductive material such as titanium nitride. The high-dielectric-coefficient material may contain hafnium oxide, zirconium oxide, titanium oxide, silicon oxynitride, or other suitable dielectric materials. In some embodiments (not shown), each of the gate dielectric layer 106a and the gate electrode 106b may contain multiple sublayers. See also... Figure 33 The gate stack 406 may be conformally deposited over the semiconductor feature 501. As shown, the gate dielectric layer 106a is located on the upper and side surfaces of the semiconductor feature 501. The gate dielectric layer 106a is also located on the upper surface of the first insulating layer 115. Next, the gate electrode 106b is located on the upper and side surfaces of the gate dielectric layer 106a. It should be noted that the first insulating layer 115 separates the gate stack 406 from the capacitor 508.

[0188] Please see Figure 34 In method 300, operation 322 etches through the gate stack 406 to expose a portion of the first insulating layer 115. It should be noted that the exposed portion of the first insulating layer 115 is directly above the remaining portion of the second dielectric layer 120 above the electrode 508a of the capacitor 508.

[0189] Please see Figure 35 In method 300, operation 324 forms a third dielectric layer 130 over the exposed portion of the first insulating layer 115 and over the gate stack 406 using a suitable deposition process. The third dielectric layer 130 may contain a material similar to dielectric layer 110 and the second dielectric layer 120. The third dielectric layer 130 directly contacts the gate stack 406 (including gate dielectric layer 106a and gate electrode 106b) and directly contacts the upper surface of the insulating layer 115. As shown, the third dielectric layer 130 covers and embeds a first portion 501a of the gate stack 406 and the semiconductor feature 501.

[0190] Please see Figure 36 In method 300, operation 326 performs a pullback etch on the third dielectric layer 130. The pullback etch exposes the top portion of the gate stack 406. At this point, the third dielectric layer 130 surrounds and embeds the lower portion of the gate stack 406 (which subsequently becomes gate 506).

[0191] Please see Figure 37In method 300, operation 328 etches the top layer of the gate stack 406 to expose the top layer of the first portion 501a of the semiconductor feature 501. Specifically, regarding the semiconductor feature 501, the top layer of the first portion 501a is exposed; however, the bottom layer of the first portion 501a and the second portion 501b remain covered. When etching the top layer of the gate stack 406, the third dielectric layer 130 may serve as an etch stop layer and an etch mask. The remaining portion of the gate stack 406 forms the gate 506. Figure 20A and Figure 20B The semiconductor feature 501 can function as a transistor 501 and includes portions such as a source, a drain, and a channel. After forming the gate 506, the source, drain, and channel portions of the semiconductor feature 501 are defined. For example, the semiconductor feature 501 includes a first source / drain feature 502, which can be the drain (or source) of the semiconductor feature 501. The semiconductor feature 501 includes a second source / drain feature 504, which can be the source (or drain) of the semiconductor feature 501. The semiconductor feature 501 also includes a channel 505 vertically located between the first source / drain feature 502 and the second source / drain feature 504, which can be a channel of the semiconductor feature 501. Figure 37 As shown, gate 506 horizontally surrounds and covers channel 505. Channel 505 is a vertical channel with source and drain portions located above and / or below channel 505. First source / drain feature 502 may be a first portion 501a of semiconductor feature 501, channel 505 may be a bottom portion of the first portion 501a of semiconductor feature 501, and second source / drain feature 504 may be a second portion 501b of semiconductor feature 501. In one illustrated embodiment, channel 505 and first source / drain feature 502 have substantially the same width along the X direction because channel 505 and first source / drain feature 502 are formed in the same patterning step, and channel 505 and first source / drain feature 502 may have a larger width along the X direction than second source / drain feature 504.

[0192] Please see Figure 38In method 300, operation 330 forms a second insulating layer 117 over the gate 506 and over the third dielectric layer 130. The second insulating layer 117 may be made of the same material as the first insulating layer 115. The second insulating layer 117 may be formed using a directional deposition process such that the second insulating layer 117 is formed only (or substantially) on the upper surfaces of the gate 506, the third dielectric layer 130, and the first source / drain feature 502. A subsequent etch process may be performed to etch the portion of the second insulating layer 117 located above the upper surface of the first source / drain feature 502. Thus, the second insulating layer 117 is formed as shown, located on the upper surfaces of the gate 506 and the third dielectric layer 130, and on the side surfaces of a portion of the first source / drain feature 502. After the second insulating layer 117 is formed, the top layer portion of the first source / drain feature 502 remains exposed. The second insulating layer 117 may serve as an etch stop layer comprising silicon nitride. In one embodiment, the second insulating layer 117 comprises a dielectric material different from that of the dielectric layer 110 and the second dielectric layer 120 to correspond to the selectivity of the etchant.

[0193] Please see Figures 39 to 40 In method 300, operation 332 forms a conductive layer 112 over the second insulating layer 117 and over the exposed side and top surfaces of the first source / drain feature 502 (e.g., the exposed side and top surfaces of the top layer portion of the first portion 501a of semiconductor feature 501). The conductive layer 112 may contain a suitable conductive material, such as titanium nitride. The conductive layer 112 may be formed using a suitable deposition process (see...). Figure 39 ) and subsequent patterning processes (see Figure 40 The patterning process includes etching a side portion of the conductive layer 112 situated above the second insulating layer 117. As shown, the conductive layer 112 may be located directly above the gate 506 and the first source / drain feature 502; however, the conductive layer 112 may be located not directly above the third dielectric layer 130 due to the patterning process.

[0194] Please see Figure 41In method 300, operation 334 forms a fourth dielectric layer 140 over the conductive layer 112 and over the second insulating layer 117 using a suitable deposition process. The fourth dielectric layer 140 may contain a material similar to that of dielectric layer 110, second dielectric layer 120, and third dielectric layer 130. The fourth dielectric layer 140 directly contacts the conductive layer 112 and directly contacts the upper surface of the second insulating layer 117. Method 300 forms a memory device 100 having a transistor 501 and a capacitor 508 located below the transistor. As shown, a first insulating layer 115 and a second insulating layer 117 separate the dielectric layer 110, the second dielectric layer 120, and the third dielectric layer 130 corresponding to different interlayer dielectric layers. Furthermore, the first insulating layer 115 separates the gate 506 from the capacitor 508, and the second insulating layer 117 separates the gate 506 from the conductive layer 112. To achieve a higher capacitance, the height of the second source / drain feature 504 along the Z-direction may be greater than the height of the channel 505 along the Z-direction (as shown in the figure). In a different embodiment, to achieve a lower capacitance, the height of the second source / drain feature 504 along the Z-direction may be less than the height of the channel 505 along the Z-direction. In other words, the dimensional height and ratio between the second source / drain feature 504 and the channel 505 may be adjusted to meet the goal of low leakage current and high capacitance density.

[0195] Figure 41 It includes an A-A' line crossing the second source / drain feature 504 and a B-B' line crossing the channel 505. According to different embodiments disclosed herein, Figure 42A-1 , Figure 42A-2 and Figure 42A-3 for Figure 41 A top view of the memory device 100 along line A-A'. According to different embodiments disclosed herein, Figure 42B-1 , Figure 42B-2 and Figure 42B-3 for Figure 41 A top view of the memory device 100 along the B-B' line.

[0196] Please see Figure 42A-1 , Figure 42A-2 and Figure 42A-3 In the XY plane, the second source / drain feature 504 may be completely surrounded by a capacitor 508. The capacitor 508 includes an electrode 508c that directly contacts and completely surrounds the second source / drain feature 504. The capacitor 508 includes an insulating layer 508b that directly contacts and completely surrounds the electrode 508c. The capacitor 508 also includes an electrode 508a that directly contacts and completely surrounds the insulating layer 508b. Although not shown, the capacitor 508 may include additional interlayer interleaved metal and insulating layers in the electrodes 508a and 508c. In one embodiment, in the XY plane, the second source / drain feature 504 is circular (see...). Figure 42A-1 In another embodiment, in the XY plane, the second source / drain feature 504 is square (see...). Figure 42A-2 In another embodiment, in the XY plane, the second source / drain feature 504 is rectangular. Figure 42A-3 ).

[0197] Please see Figure 42B-1 , Figure 42B-2 and Figure 42B-3 In the XY plane, channel 505 may be completely surrounded by gate 506. Gate 506 includes a gate dielectric layer 106a that directly contacts and completely surrounds the channel 505. Gate 506 also includes a gate electrode 106b that directly contacts and completely surrounds the gate dielectric layer 106a. In one embodiment, in the XY plane, channel 505 is circular (see...). Figure 42B-1 In another embodiment, in the XY plane, channel 505 is square (see...). Figure 42B-2 In another embodiment, in the XY plane, channel 505 is rectangular (see...). Figure 42B-3 ).

[0198] Figure 42A-1 , Figure 42A-2 and Figure 42A-3 Each of them displays the width x2 of the second source / drain feature 504. Figure 42B-1 , Figure 42B-2 and Figure 42B-3 Each of them displays the width X1 of channel 505. In this embodiment, the width X1 of each pair of channels 505 and the second source / drain feature 504 is greater than X2 (e.g., Figure 42B-1 X1 is greater than Figure 42A-1 In other embodiments, the width X1 of each pair of channels 505 and the second source / drain feature 504 is smaller than X2 (e.g., X2 in the example). Figure 42B-1 X1 is less than Figure 42A-1 (X2 in the example above). In any of the above examples, the possible cause of this phenomenon is that the channel 505 and the second source / drain feature 504 form different widths (see reference). Figure 32 (For example, the first portion 501a has a different width than the second portion 501b of the semiconductor feature 501). The difference in width stems from the aforementioned... Figure 15A-1 , Figure 15A-2 , Figure 15A-3 , Figure 15B-1 , Figure 15B-2 and Figure 15B-3 This difference may also provide an additional tuning window for different capacitance values.

[0199] See Figure 43In method 300, operation 336 forms a first conductive post trench 131 that penetrates the fourth dielectric layer 140, the second insulating layer 117, the third dielectric layer 130, and the first insulating layer 115. In one illustrated embodiment, the first conductive post trench 131 also penetrates the second dielectric layer 120. The first conductive post trench 131 exposes the metal layer of capacitor 508 (e.g., electrode 508a). The exposed portion of electrode 508a may be... Figure 26 The portion with opening 223. Since the second dielectric layer 120 provides an insulating layer, the first conductive post trench 131 does not expose the electrodes 508c of the capacitor 508. The fourth dielectric layer 140, the second insulating layer 117, the third dielectric layer 130, the first insulating layer 115, and the second dielectric layer 120 may be etched in the same or respective etching processes that form the first conductive post trench 131. In one embodiment, the first conductive post trench 131 is etched using different etching parameters when the fourth dielectric layer 140, the third dielectric layer 130, the second dielectric layer 120, and the second insulating layers 117 and 115 are each etched.

[0200] See also Figure 43 In method 300, operation 338 forms a second conductive post trench 141 that penetrates the fourth dielectric layer 140, the second insulating layer 117, and the third dielectric layer 130. The second conductive post trench 141 exposes the gate 506. The exposed portion of the gate 506 is the horizontal portion of the gate 506 directly above the first insulating layer 115. Specifically, the second conductive post trench 141 exposes the horizontal surface of the gate electrode 106b. The trench depth of the second conductive post trench 141 is not the same as that of the first conductive post trench 131. The fourth dielectric layer 140, the second insulating layer 117, and the third dielectric layer 130 may be etched in the same or separate etching processes that form the second conductive post trench 141. In one embodiment, the second conductive post trench 141 is etched using different etching parameters when the fourth dielectric layer 140, the third dielectric layer 137, and the second insulating layer 117 are each etched.

[0201] See also Figure 43In method 300, operation 340 forms a third conductive post trench 151 that penetrates the fourth dielectric layer 140. The third conductive post trench 151 exposes the upper surface of the conductive layer 112. As shown, the depth of the third conductive post trench 151 may be shallower than that of the first conductive post trench 131 and the second conductive post trench 141. This is because the third conductive post trench 151 does not penetrate the insulating layer 115 and / or the second insulating layer 117. To avoid over-etching and damage to the conductive layer 112, the third conductive post trench 151 may be formed separately from the first conductive post trench 131 and the second conductive post trench 141. For example, the first conductive post trench 131 and the second conductive post trench 141 may be formed together in a first patterning process including lithography and etching processes, followed by the formation of the third conductive post trench 151 in a second patterning process including lithography and etching processes. In another embodiment, the first conductive post trench 131 and the second conductive post trench 141 may be partially formed in the first patterning process and etched to a first depth. Following the second patterning process, the first conductive post trench 131, the second conductive post trench 141, and the third conductive post trench 151 are formed together in a further etching process, wherein the first conductive post trench 131 and the second conductive post trench 141 are etched to a second depth, exposing the electrode 508a and the gate 506 of the capacitor 508, and the third conductive post trench 151 is etched to expose the conductive layer 112. In another embodiment, the first conductive post trench 131, the second conductive post trench 141, and the third conductive post trench 151 may all be formed in their respective patterning processes.

[0202] See Figure 44 In method 300, operation 342 forms first conductive pillars 132, second conductive pillars 142, and third conductive pillars 152 in the first conductive pillar trench 131, the second conductive pillar trench 141, and the third conductive pillar trench 151, respectively. These conductive pillars may be formed using any suitable deposition method, such as physical vapor deposition or chemical vapor deposition, to deposit metallic material in the first conductive pillar trench 131, the second conductive pillar trench 141, and the third conductive pillar trench 151. Next, a chemical mechanical planarization process may be performed to remove any overfilled portions of metallic material and planarize the memory device 100 to facilitate the formation of the first conductive pillars 132, the second conductive pillars 142, and the third conductive pillars 152. The metallic material of the first conductive pillars 132, the second conductive pillars 142, and the third conductive pillars 152 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo), or any combination thereof.

[0203] See also Figure 44The first conductive post 132 is directly located on the capacitor 508 and on the first electrode (electrode 508a), which is essentially a capacitor structure. The first electrode (electrode 508c) of the capacitor structure is electrically connected to the second source / drain feature 504 of the semiconductor feature 501. Specifically, electrode 508a directly contacts the first conductive post 132, and electrode 508c directly contacts the second source / drain feature 504. The first conductive post 132 may be a ground conductive post, conducting the circuit to the ground line of the memory device 100. The second conductive post 142 is directly located on the gate 506, wherein the gate 506 surrounds the channel 505 covering the semiconductor feature 501. The second conductive post 142 may be a word line conductive post, conducting the circuit to the word line of the memory device 100. The third conductive post 152 is directly located on the conductive layer 112 and is electrically connected to the first source / drain feature 502 of the semiconductor feature 501. The third conductive post 152 can be a ground bit line, which conducts the circuit to the bit line of the memory device 100.

[0204] According to the embodiments described herein, Figure 45A Method 3000 forms a structure containing Figure 20B (or Figure 44 The flowchart of the integrated circuit 1000 of the memory device 100 in the ) is shown. Figure 45B For Figure 45A The integrated circuit 1000 is formed using method 3000. (See also...) Figure 45A and Figure 45B Method 3000, operation 3002, forms a transistor device 104 over a substrate 102. The transistor device 104 may differ from the aforementioned memory device 100. In one embodiment, the transistor device 104 is a logic element. Each of the transistor devices 104 includes a channel region 104a located between source / drain regions 104b. The channel region 104a and the source / drain regions 104b may be portions of an active element region over the substrate 102. Each of the transistor devices 104 includes a gate 606 over the channel region 104a. The transistor device 104 may be a planar device (as shown) or may be a FinFET or a Gate All-Around (GAA) field-effect transistor.

[0205] Referring to operation 3004, method 3000 forms a first interconnect structure 1100 above the transistor device. The first interconnect structure 1100 includes metal contacts such as source / drain contacts, a gate contact (not shown) located in the source / drain region 104b and the gate 606, conductive pillars such as source / drain conductive pillars, a gate conductive pillar located in the metal contacts (not shown), and metal lines 108 situated and electrically connected to the plurality of metal contacts and conductive pillars. The plurality of metal contacts, conductive pillars, and metal lines of the first interconnect structure 1100 may be covered or embedded in an interlayer dielectric layer. Referring to operation 3006, method 3000 forms a vertical gate all-around memory device 100 above the first interconnect structure 1100. The vertical gate all-around memory device 100 may be formed using the aforementioned method 300. In one embodiment, the memory device 100 is formed above the dielectric layer 110 and above the first interconnect structure 1100. The dielectric layer 110 may cover the memory device 100 and embed other features such as through conductive pillars 107. Referring to operation 3008, method 3000 forms a second interconnect structure 1200 over the memory device 100 with a vertical gate completely surrounding it. The second interconnect structure 1200 includes various metal lines 108 electrically connected to the memory device 100. For example, multiple metal lines 108 may be located on the first conductive pillar 132, the second conductive pillar 142, and the third conductive pillar 152. These metal lines 108 are subsequently connected to metal lines 108 on higher layers as additional lines. Multiple metal lines 108 in the second interconnect structure 1200 may be located on through conductive pillars 107 that bypass the memory device 100 to be located on the metal lines 108 in the first interconnect structure 1100.

[0206] like Figure 45A and Figure 45B As stated and displayed, Figure 20B (or Figure 44The memory device 100 in the memory device 100 may be embedded and sandwiched between a plurality of metal lines 108. These metal lines 108, whether in the first interconnect structure 1100 or the second interconnect structure 1200, are front-side metal lines formed above the transistor device 104. In some embodiments, due to the increased density efficiency of the memory device 100, the vertical distance between each of the metal lines 108 sandwiched within the memory device 100 is approximately the same as the vertical distance between each of the metal lines 108 not sandwiched within any memory device 100. In other embodiments, the distance between each of the metal lines 108 sandwiched within the memory device 100 is greater than the distance between each of the metal lines 108 not sandwiched within any memory device 100. It should be noted that different memory devices 100 may be configured between different metal lines 108. In one embodiment, the formed integrated circuit 1000 may include a plurality of vertical gate all-around transistors for the memory device 100 and a plurality of horizontal gate all-around transistors for logic elements (such as the transistor device 104). That is, the memory device 100 has a vertical channel with a gate electrode horizontally covered, and a logic element (such as a transistor device 104) with a horizontal channel with a gate electrode vertically covered.

[0207] According to other embodiments disclosed herein, Figure 46A Method 5000 forms an integrated circuit 1000 comprising Figure 20B (or Figure 44 The flowchart of the memory device 100 in ) . Figure 46B for Figure 46A Integrated circuit 1000 formed by Chinese method 5000. (See also...) Figure 46A and Figure 46B Method 5000, operation 5002, forms a transistor device 104 over a substrate (the substrate is not shown in the figure). The transistor device 104 may differ from the aforementioned memory device 100. In one embodiment, the transistor device 104 is a logic element. Each transistor device 104 includes a channel region 104a located between source / drain regions 104b. In an illustrated embodiment, the channel region 104a may include a stack of multiple channel layers connecting the source / drain regions 104b. Each transistor device 104 includes a gate 606 over the channel region 104a. However, as... Figure 19BAs shown, after the circuit structure is flipped in operation 4006, gate 606 is positioned below channel region 104a. Gate 606 may include a gate dielectric and a gate electrode, and gate 606 may have portions that vertically surround and cover multiple channel layers. Gate 606 may include a gate dielectric and gate electrodes that vertically surround and cover multiple channel layers. Each of transistor devices 104 may include spacers 109, such as gate spacers, inner spacers, or insulating spacers between channel layers, gate structures, and other associated surrounding features. In some embodiments, spacers 109 comprise dielectric materials, wherein the dielectric materials comprise silicon, oxygen, carbon, nitrogen, other suitable materials, or any combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the spacer layer comprises a low dielectric constant material. Transistor device 104 may be a gate-all-around field-effect transistor as shown, or may be a planar device or a fin field-effect transistor (FinFET).

[0208] Referring to operation 5004, method 5000 forms a first internal connection structure 1100 above the transistor device 104, thereby forming a circuit structure having the first internal connection structure 1100 and the transistor device 104. It should be noted that... Figure 46BThe first interconnect structure 1100 is shown below the transistor device 104. This is because the circuit structure is flipped downwards in a subsequent manufacturing stage. The first interconnect structure 1100 includes metal contacts such as source / drain contacts, gate contacts located in the source / drain regions 104b and gate 606 (not shown), conductive pillars such as source / drain conductive pillars, gate conductive pillars located in the metal contacts (not shown), and metal lines 108 situated and electrically connected to multiple metal contacts and conductive pillars. The multiple metal contacts, conductive pillars, and metal lines of the first interconnect structure 1100 may be covered or embedded in an interlayer dielectric layer. Referring to operation 5006, method 5000 flips the circuit structure and transistor device 104 having the first interconnect structure 1100 and performs a thinning process on the back side of the circuit structure. Operation 5006 may include forming a bonding substrate 101 for structural strength over the first interconnect structure 1100, then flipping the entire working element, and performing a thinning process to remove the portion of the transistor device 104 previously formed over the circuit structure. Referring to operation 5008, method 5000 forms a second interconnect structure 1200 over the back side of the circuit structure (from this point onwards, the flipped structure). The second interconnect structure 1200 includes various metal lines 108 electrically connected to the transistor device 104. For example, the plurality of metal lines 108 may include back-side conductive pillars located from the back side of the source / drain regions 104b of the transistor device 104, and back-side conductive lines located on the back-side conductive pillars. These back-side conductive lines may also be referred to as back-side power rails to transmit power from the back side of the transistor device 104 via power winding circuitry. These metal lines 108 then further connect the circuitry to metal lines 108 in a third interconnect structure. Referring to operation 5010, method 5000 forms a vertical gate all-around memory device 100 over a second interconnect structure 1200. The vertical gate all-around memory device 100 may be formed using the aforementioned method 300. In some embodiments, the memory device 100 is formed over a dielectric layer 110 above the second interconnect structure 1200. The dielectric layer 110 may cover the memory device 100 and embed other features such as through-conductive pillars 107. Referring to operation 5012, method 5000 forms a third interconnect structure 1300 over the vertical gate all-around memory device 100. As described above, the vertical gate all-around memory device 100 is formed between the back-side power rail in the second interconnect structure 1200 and the metal circuit lines in the third interconnect structure 1300. The third interconnect structure 1300 includes a plurality of metal lines 108 electrically connected to the memory device 100. For example, multiple metal wires 108 may be located on the first conductive post 132, the second conductive post 142, and the third conductive post 152. These metal wires 108 are subsequently connected to metal wires 108 at higher levels as additional lines.In the third internal connection structure 1300, multiple metal lines 108 may be located on the through conductive post 107, which bypasses the memory device 100 to be located in the metal lines 108 in the second internal connection structure 1200.

[0209] like Figure 46A and Figure 46B As stated and displayed, Figure 20B (or Figure 44 The memory device 100 in the transistor device 104 may be embedded and sandwiched between a plurality of metal lines 108. These metal lines 108 are back-side metal lines formed above the back side of the transistor device 104. In some embodiments, due to the increased density efficiency of the memory device 100, the vertical distance between each of the metal lines 108 sandwiched within the memory device 100 is approximately the same as the vertical distance between each of the metal lines 108 not sandwiched within any memory device 100. In other embodiments, the distance between each of the metal lines 108 sandwiched within the memory device 100 is greater than the distance between each of the metal lines 108 not sandwiched within any memory device 100. It should be noted that different memory devices 100 may be configured between different metal lines 108. In one embodiment, the formed integrated circuit 1000 may include a plurality of vertical gate all-around transistors for the memory device 100 and a plurality of horizontal gate all-around transistors for logic elements (such as the transistor device 104). That is, the memory device 100 has a vertical channel with a gate electrode horizontally covered, and a logic element (such as a transistor device 104) with a horizontal channel with a gate electrode vertically covered.

[0210] While not limiting, this paper discloses the advantages of memory devices with transistors and capacitors. One example of this advantage is the vertical stacking of transistors and capacitors in a memory device, which reduces the passive component area of ​​the device and increases device density. The capacitors directly contact the source / drain regions of the transistors for direct coupling. Furthermore, this paper discloses the possibility of capacitors being located directly above or below the transistors. Additionally, this paper discloses the ability to adjust capacitance based on the different dimensions of the transistors and capacitors. Another example of this advantage is embedding vertically stacked memory devices in an integrated circuit, which may include vertical gate all-around transistors for memory device 100 and multiple horizontal gate all-around transistors for logic elements. Furthermore, multiple vertically stacked memory devices may be formed in a front-side interconnect structure or a back-side interconnect structure for easy integration.

[0211] This disclosure discloses a memory device. The memory device includes semiconductor features made of a compound semiconductor material. The semiconductor features include a first portion serving as a first source / drain feature, a second portion serving as a channel, and a third portion serving as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, with the second portion extending vertically from the first portion to the third portion. The memory device includes a gate structure horizontally surrounding and enclosing the second portion, and a capacitor structure directly contacting and surrounding the semiconductor features.

[0212] In one embodiment, the semiconductor feature has an amorphous or polycrystalline silicon structure. In another embodiment, the semiconductor feature comprises indium gallium zinc oxide.

[0213] In one embodiment, the capacitor structure has a first electrode, a second electrode, and an insulating layer between the first and second electrodes. The first electrode is directly situated on the horizontal and vertical surfaces of the semiconductor feature. The second electrode is electrically connected to a ground wire.

[0214] In another embodiment, the gate structure is electrically connected to a word line. A capacitor structure surrounds a third portion of the semiconductor feature, and a first portion of the semiconductor feature is electrically connected to a word line.

[0215] In another embodiment, a gate structure is electrically connected to a word line, a capacitor structure surrounds a first portion of a semiconductor feature, and a third portion of the semiconductor feature is electrically connected to a word line.

[0216] In one embodiment, the memory device further includes a dielectric layer between the gate structure and the capacitor structure, the dielectric layer separating the gate structure and the capacitor structure, and the dielectric layer being located on a plurality of sidewalls of the semiconductor feature. In another embodiment, the dielectric layer is a first dielectric layer, and the memory device further includes a second dielectric layer above the first dielectric layer, and a conductive layer above the second dielectric layer and in direct contact with the semiconductor feature. The second dielectric layer is located between the gate structure and the conductive layer, and the second dielectric layer separates the gate structure and the capacitor structure, and the second dielectric layer is located on a plurality of sidewalls of the semiconductor feature.

[0217] In one embodiment, the memory device further includes a conductive layer that directly contacts a semiconductor feature and is located on a pair of sides of a capacitor structure. A gate structure is vertically located between the conductive layer and the capacitor structure. The capacitor structure, gate structure, and conductive layer are separated from each other. In another embodiment, the memory device further includes bit line conductive posts situated on the conductive layer and electrically connected to a word line; ground conductive posts situated on the capacitor structure and electrically connected to a ground line; and word line conductive posts situated on the gate structure and electrically connected to a word line.

[0218] Another embodiment disclosed herein is a memory device. The memory device includes a conductive layer above a dielectric layer. The memory device includes a semiconductor feature made of a compound semiconductor material located above the conductive layer. The semiconductor feature includes a first portion serving as a first source / drain feature, a second portion serving as a channel, and a third portion serving as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, with the second portion extending vertically from the first portion to the third portion. The memory device includes a gate structure horizontally surrounding and covering the second portion of the semiconductor feature, a metal-insulator-metal capacitor structure located above the first portion of the semiconductor feature, wherein the coplanar metal-insulator-metal capacitor structure directly contacts multiple upper and side surfaces of the first portion of the semiconductor feature, and an insulating layer is located between the gate structure and the metal-insulator-metal capacitor structure.

[0219] In one embodiment, the metal-insulator-metal capacitor structure has a first electrode and a second electrode, the first electrode being electrically connected to a first portion of the semiconductor feature, and the second electrode being electrically connected to a ground line. A gate structure is electrically connected to a word line. A third portion of the semiconductor feature is electrically connected to a bit line.

[0220] In one embodiment, the compound semiconductor material forming the semiconductor features comprises oxygen and at least two of the following three materials: indium, gallium, and zinc.

[0221] In one embodiment, the gate structure includes a gate dielectric layer surrounding a second portion of the semiconductor feature, and a gate electrode layer surrounding the gate dielectric layer.

[0222] In one embodiment, the memory device further includes a first interlayer dielectric layer located above the conductive layer, wherein a gate structure is embedded in the first interlayer dielectric layer, and a second interlayer dielectric layer located above the insulating layer, wherein a capacitor structure is embedded in the second interlayer dielectric layer. The insulating layer separates the first interlayer dielectric layer from the second interlayer dielectric layer.

[0223] In another embodiment, the memory device further includes bit line conductive posts passing through a second interlayer dielectric layer, an insulating layer, and a first interlayer dielectric layer to lie on a conductive layer. The device includes ground conductive posts passing through the second interlayer dielectric layer to lie on a metal-insulator-metal capacitor structure, and word line conductive posts passing through the second interlayer dielectric layer. The device includes an insulating layer and a first interlayer dielectric layer to lie on a gate structure.

[0224] In one embodiment, a first portion of the memory device has a first width along a first direction, a second portion has a second width along the first direction, and a third portion has a third width along the first direction. The first and second widths are substantially the same, and the third width is larger than the second width.

[0225] Another aspect disclosed herein is a method. This method includes forming a conductive layer on a first dielectric layer. This method includes forming a semiconductor layer over the conductive layer. This method includes patterning the semiconductor layer to form a semiconductor feature having a first portion located over a second portion, wherein the second portion is wider than the first portion. This method includes forming a gate stack over the semiconductor feature. This method includes forming a second dielectric layer over the gate stack. This method includes etching through the second dielectric layer, the gate stack, and a second portion of the semiconductor feature to form a trench exposing a portion of the conductive layer. This method includes filling the trench with a dielectric material to reshape the second dielectric layer. This method includes performing a pull-back etching on the second dielectric layer to expose a top portion of the gate stack. This method includes etching the top portion of the gate stack to expose a top portion of the first portion of the semiconductor feature, wherein the remaining portion of the gate stack forms a gate structure horizontally surrounding a vertical channel enclosing the semiconductor feature. This method includes forming an insulating layer over the gate structure and the second dielectric layer. This method includes forming a metal-insulator-metal capacitor structure over an insulating layer, and multiple side surfaces and a top surface of the exposed top layer portion of a first semiconductor feature. This method also includes forming a third dielectric layer over the metal-insulator-metal capacitor structure.

[0226] In one embodiment, the method further includes forming a first conductive post through the third dielectric layer, the insulating layer, and the second dielectric layer, and the first conductive post passing through and residing on a portion of the conductive layer. The method includes forming a second conductive post through the third dielectric layer, the insulating layer, and the second dielectric layer, and the second conductive post residing on the gate structure. The method further includes forming a third conductive post through the third dielectric layer, and the third conductive post residing on a metal-insulator-metal capacitor structure.

[0227] In one embodiment, the semiconductor layer comprises indium gallium zinc oxide (IGZO).

[0228] This disclosure discloses a memory device. The memory device includes a compound semiconductor feature. The compound semiconductor feature includes a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature. The first portion is located above the second portion, and the second portion is located above the third portion, and the second portion extends vertically from the first portion to the third portion. The compound semiconductor feature has an amorphous or polycrystalline silicon structure. The memory device includes a gate structure horizontally surrounding and enclosing the second portion, and a capacitor structure directly contacting and surrounding the compound semiconductor feature.

[0229] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: Comprising: a compound semiconductor feature having a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature, wherein the first portion is located above the second portion, and the second portion is located above the third portion, and the second portion extends vertically from the first portion to the third portion; a gate structure horizontally surrounding the second portion; and a capacitor structure directly contacting and surrounding the compound semiconductor feature.

2. The memory device of claim 1, wherein, wherein the compound semiconductor feature has an amorphous or polysilicon structure.

3. The memory device of claim 1, wherein: the capacitor structure has a first electrode, a second electrode, and an insulating layer between the first electrode and the second electrode, the first electrode is directly located on a horizontal surface and a vertical surface of the compound semiconductor feature, the second electrode is electrically connected to a ground line.

4. The memory device of claim 3, wherein: the gate structure is electrically connected to a word line, the capacitor structure surrounds the third portion of the compound semiconductor feature and the first portion of the compound semiconductor feature is electrically connected to a bit line.

5. The memory device of claim 3, wherein: the gate structure is electrically connected to a word line, the capacitor structure surrounds the first portion of the compound semiconductor feature and the third portion of the compound semiconductor feature is electrically connected to a bit line.

6. The memory device of claim 1, wherein, further comprising: a dielectric layer between the gate structure and the capacitor structure, the dielectric layer separating the gate structure and the capacitor structure, and the dielectric layer being located on sidewalls of the compound semiconductor feature.

7. The memory device of claim 6, wherein, wherein the dielectric layer is a first dielectric layer, further comprising: a second dielectric layer above the first dielectric layer; and a conductive layer directly contacting the compound semiconductor feature and located above the second dielectric layer, wherein the second dielectric layer is between the gate structure and the conductive layer, the second dielectric layer separating the gate structure and the capacitor structure, and the second dielectric layer being located on the sidewalls of the compound semiconductor feature.

8. The memory device of claim 1, wherein, further comprising: a conductive layer directly contacting the compound semiconductor feature and located on a pair of sides of the capacitor structure, wherein the gate structure is vertically between the conductive layer and the capacitor structure, wherein one and another of the capacitor structure, the gate structure, and the conductive layer are separated from each other.

9. A memory device, comprising: Comprising: a conductive layer above a dielectric layer; a compound semiconductor feature above the conductive layer, the compound semiconductor feature comprising a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature, wherein the first portion is located above the second portion, and the second portion is located above the third portion, and the second portion extends vertically from the first portion to the third portion; a gate structure horizontally surrounding the second portion of the compound semiconductor feature; A metal-insulator-metal capacitor structure is located over the first portion of the compound semiconductor feature, wherein the metal-insulator-metal capacitor structure directly contacts a plurality of upper and side surfaces of the first portion of the compound semiconductor feature; and An insulating layer is located between the gate structure and the metal-insulator-metal capacitor structure.

10. A memory device, comprising: Comprises: A compound semiconductor feature having a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature, wherein the first portion is located over the second portion, and the second portion is located over the third portion, and the second portion extends vertically from the first portion to the third portion, wherein the compound semiconductor feature has an amorphous or polysilicon structure; A gate structure horizontally surrounds the second portion; and A capacitor structure directly contacts and surrounds the compound semiconductor feature. A metal-insulator-metal capacitor structure is located over the first portion of the compound semiconductor feature, wherein the metal-insulator-metal capacitor structure directly contacts a plurality of upper and side surfaces of the first portion of the compound semiconductor feature; and An insulating layer is located between the gate structure and the metal-insulator-metal capacitor structure. Comprises: A compound semiconductor feature having a first portion as a first source / drain feature, a second portion as a channel, and a third portion as a second source / drain feature, wherein the first portion is located over the second portion, and the second portion is located over the third portion, and the second portion extends vertically from the first portion to the third portion, wherein the compound semiconductor feature has an amorphous or polysilicon structure; A gate structure horizontally surrounds the second portion; and A capacitor structure directly contacts and surrounds the compound semiconductor feature.

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