Silicon wafer, battery piece and photovoltaic module

Abstract

The utility model discloses a silicon wafer, a battery piece and a photovoltaic module. The silicon wafer is provided with two opposite first edges and two opposite second edges, one first edge is connected with the two adjacent second edges through first chamfers, and the other first edge is connected with the two adjacent second edges through second chamfers; the first chamfer and the second chamfer are different in shape, and the ratio of the length of the first edge to the length of the second edge is 1.2-6. The silicon wafer is provided with the first chamfer and the second chamfer, and compared with a sharp corner, the chamfer arranged on the silicon wafer can reduce the fragment rate of the silicon wafer; the first chamfer and the second chamfer are different in shape, the direction of the battery piece can be determined by recognizing the shape of the chamfer in the subsequent preparation process of the battery, and a guiding effect is achieved for welding of the assembly end. Meanwhile, when the silicon wafer is used for preparing a back contact cell, the two opposite sides of the back contact cell can assist in distinguishing the positive electrode and the negative electrode of the cell through the first chamfer and the second chamfer which are different in shape, no mark needs to be additionally arranged on the silicon wafer, the marking procedure is omitted, and the processing efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of silicon wafer technology, and in particular to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0002] Currently, the fabrication of photovoltaic cells typically involves cutting round silicon rods grown using the Czochralski method into square silicon rods. These square rods are then chamfered and sliced ​​to obtain silicon wafers for photovoltaic cells. Photovoltaic cells often require laser dicing to create half-wafers. However, this method results in two sharp corners at the chamfered edges, leading to significant breakage during transportation and loading / unloading. Therefore, a silicon wafer with reduced breakage is urgently needed. Utility Model Content

[0003] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to reduce the breakage rate of the silicon wafer.

[0004] In a first aspect, the present invention provides a silicon wafer having two opposing first sides and two opposing second sides, wherein one of the first sides is connected to the two adjacent second sides by a first chamfer, and the other first side is connected to the two adjacent second sides by a second chamfer; wherein the shapes of the first chamfer and the second chamfer are different, and the ratio of the side length of the first side to the side length of the second side is 1.2 to 6.

[0005] With the above technical solution, the silicon wafer has two first chamfers on one first side and two second chamfers on the other first side. The ratio of the side length of the first side to the side length of the second side is 1.2 to 6. Because the silicon wafer of this application has first and second chamfers, compared to sharp corners, the chamfers reduce the breakage rate of the silicon wafer. The different shapes of the first and second chamfers allow for identification of the cell orientation during subsequent battery fabrication, providing guidance for module welding. Furthermore, when fabricating back-contact cells, the silicon wafer of this application, with its first and second chamfers on opposite sides, can help distinguish the positive and negative electrodes of the cells. Therefore, no additional marking is required on the silicon wafer or cell, eliminating the marking process, saving time, and improving processing efficiency.

[0006] In some possible implementations, the first chamfer is an arc chamfer, and the second chamfer is a linear chamfer. The shapes of the first and second chamfers are different. In the subsequent battery manufacturing process, the direction of the battery cell is determined by identifying the shape of the chamfer. The arc chamfer can make better use of the area of ​​the silicon rod, thereby improving the utilization rate of the silicon rod. The linear chamfer can increase the surface area of ​​the silicon wafer, thereby increasing the power generation of the photovoltaic module made using such silicon wafer.

[0007] In some possible implementations, the projected length of the first chamfer is greater than the projected length of the second chamfer. When using such a silicon wafer to fabricate solar cells, since the two opposite sides of the back-contact solar cell have different shapes—the first and second chamfers—and further, given that the projected length of the first chamfer is greater than the projected length of the second chamfer, it is easier to distinguish the positive and negative electrodes of the solar cell. Therefore, there is no need to add additional markings to the silicon wafer or solar cell, eliminating the marking process, saving time, and improving processing efficiency.

[0008] In some possible implementations, the projected length of the first chamfer is 0.01 mm to 9 mm.

[0009] When the above technical solution is adopted, if the projected length of the first chamfer is less than 0.01mm, the projected length of the first chamfer is too small, which will lead to an increase in the area to be removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer. At the same time, the first chamfer is too sharp, which increases the breakage rate of the silicon wafer during transportation or transfer. When the projected length of the first chamfer is greater than 9mm, the chamfer of the silicon wafer is too large. Using such a silicon wafer to prepare solar cells results in a large blank area between solar cells, which affects the power generation of photovoltaic modules.

[0010] In some possible implementations, the projected length of the second chamfer is 0.01 mm to 8.5 mm.

[0011] When the above technical solution is adopted, the projected length of the second chamfer is greater than 0.01mm to prevent the chamfer from being too sharp and increasing the breakage rate of the silicon wafer during transportation or transfer; the projected length of the second chamfer is less than or equal to 8.5mm to prevent the blank area between the cells from being too large due to the excessive chamfer of the silicon wafer, which would affect the power generation of the photovoltaic module.

[0012] In some possible implementations, the difference between the projected length of the first chamfer on the first side and the projected length on the second side is 0mm to 2mm;

[0013] And / or, the difference between the projected length of the second chamfer on the first side and the projected length on the second side is 0mm to 1mm.

[0014] With the above technical solution, the projections of the first chamfer on the first and second sides are different. Considering the different stress concentrations on different sides of the silicon wafer, setting the projection difference of the first chamfer on different sides to within 0-2mm can reasonably alleviate the stress on the edge of the silicon wafer and prevent the projection difference of the first chamfer on the first and second sides from being too large, thus reducing the utilization rate of the silicon rod used for processing silicon.

[0015] In some possible implementations, the projection length of the first chamfer on the first side is 0.05mm to 9mm, and the projection length of the first chamfer on the second side is 0.05mm to 7mm.

[0016] And / or, the projection length of the second chamfer on the first side is 0.05mm to 5mm, and the projection length of the second chamfer on the second side is 0.05mm to 5mm.

[0017] With the above technical solution, the projected length of the first chamfer on the first side can be greater than the projected length of the first chamfer on the second side, and the projected length of the second chamfer on the first side can be less than or equal to the projected length of the second chamfer on the second side. Because the projection of the first chamfer on the long side is longer, it effectively alleviates the problem of edge stress concentration corresponding to the long side; the projection on the short side is shorter, which alleviates stress concentration at the short edge while preventing excessively long projections on the short side from causing excessive blank space at the module end, thus affecting power generation.

[0018] In some possible implementations, the difference between the projected length of the first chamfer on the first side and the projected length of the second chamfer on the first side is 0.05mm to 8mm;

[0019] And / or, the difference between the projected length of the first chamfer on the second side and the projected length of the second chamfer on the second side is 0.05mm to 8mm.

[0020] When the above technical solution is adopted, the difference is within this range, which can make it easy to observe the size relationship between the first chamfer and the second chamfer with the naked eye. This prevents the difference from being less than 0.05mm, which makes it difficult to identify the positive and negative electrode arrangement order of the subsequently prepared solar cells. If the difference is greater than 8mm, the projected length of the first chamfer will be too large. In the silicon wafer preparation process, more silicon rods will be removed, resulting in low utilization of silicon rods and increased cost of silicon wafer preparation.

[0021] In some possible implementations, the central angle of the rounded chamfer is 2° to 6°.

[0022] When using the above technical solution, if the central angle of the arc chamfer is less than 2°, the arc chamfer will be too small, which will increase the area to be removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer. At the same time, if the arc chamfer is too sharp, the stress at the edge of the silicon wafer cannot be released in time, increasing the breakage rate of the silicon wafer during transportation or transfer. When the central angle of the arc chamfer is greater than 6°, the silicon wafer will have too large an arc. Using such silicon wafer to prepare solar cells will result in a large blank area between solar cells, which will affect the power generation of photovoltaic modules.

[0023] In some possible implementations, the first included angle between the tangent at the end of the curved chamfer that connects to the first side and the first side is 30° to 55°.

[0024] When the above technical solution is adopted, if the first angle between the tangent at the end of the arc chamfer connected to the first side and the first side is less than 30°, the chamfer is too sharp, which increases the breakage rate of the silicon wafer edge. If the first angle between the tangent at the end of the arc chamfer connected to the first side and the first side is greater than 55°, the projected length of the arc chamfer is large, resulting in more blank space at the module end, which affects the power generation of the battery.

[0025] And / or, the second included angle between the tangent at the other end of the curved chamfer that connects to the second side and the second side is 45° to 50°.

[0026] When the above technical solution is adopted, the angle between the tangent at the end of the arc chamfer that connects to the second side and the second side is 45° to 50°. Since the stress is relatively concentrated at the short edge of the silicon wafer, the second angle is within the above range, which can effectively reduce the breakage rate of the silicon wafer edge.

[0027] In some possible implementations, the angle between the linear chamfer and the first edge is 35° to 50°. This acute angle facilitates the release of stress at the silicon wafer edge, reduces the sharp corner stress between the chamfer and the wafer edge, and lowers the risk of edge breakage and microcracks.

[0028] In some possible implementations, the length of the first side is 182mm to 300mm, and the length of the second side is 83mm to 150mm. This allows for maximum utilization of the container's dimensions within the silicon wafer size range, while simultaneously increasing the power generation of solar cells by directly fabricating such wafers.

[0029] In some possible implementations, the surface of the silicon wafer has multiple spaced-apart first ridges, the extension direction of which is the same as the extension direction of the first edge or the second edge. The first ridges are cutting lines formed on the surface of the silicon wafer during the cutting process. When the extension direction of the first ridges is the same as the extension direction of the first edge, the extension direction of the first electrode on the solar cell made from this silicon wafer is the same as the long side direction of the solar cell. To ensure that the extension direction of the first electrode is the same as the extension direction of the first ridges on the solar cell, and to reduce the risk of first electrode grid breakage caused by the first ridges, the extension direction of the first ridges on the silicon wafer is the same as the long side direction of the silicon wafer, i.e., the same as the direction of the first edge.

[0030] Secondly, this utility model also provides a battery cell, which is prepared from the silicon wafer described in any of the above claims, and the surface of the battery cell has a first electrode that extends along a first side of the silicon wafer.

[0031] Since the solar cells are made from the silicon wafers described in the first aspect, they have the same beneficial effects as those described in the first aspect, which will not be elaborated further.

[0032] In some possible implementations, the number of first electrodes at the first chamfer is greater than or equal to the number of first electrodes at the second chamfer.

[0033] By setting a reasonable number of electrodes in different areas of the silicon wafer, the maximum light absorption rate of the solar cell can be ensured, thereby improving the photoelectric conversion efficiency of the cell.

[0034] In some possible implementations, the surface of the solar cell has a first texture, and the first texture extends in the same direction as the first electrode. This reduces the risk of grid breakage in the first electrode caused by the first texture.

[0035] In some possible implementations, the first electrode is a sub-gate line.

[0036] Thirdly, this utility model also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect, wherein the conductive interconnect is connected between two adjacent solar cells, and the solar cells are as described in any of the above embodiments. Since the photovoltaic module includes the solar cells of the second aspect, it has the same beneficial effects as the first and second aspects, and will not be described further.

[0037] In some possible implementations, the conductive interconnects extend along the first edge of the silicon wafer. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this invention, illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0039] Figure 1 This is a schematic diagram of the structure of a silicon wafer provided in an embodiment of the present utility model;

[0040] Figure 2 This is a schematic diagram of a silicon wafer with a first texture on its surface, provided as an embodiment of the present invention.

[0041] The attached diagram is labeled as follows: 4 represents the silicon wafer, 10 represents the first edge, 20 represents the second edge, 30 represents the first chamfer, 40 represents the second chamfer, and 50 represents the first texture. Detailed Implementation

[0042] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0043] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0045] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0046] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0047] The vast majority of solar cells use monocrystalline silicon wafers as their raw material. The cost and photoelectric conversion efficiency of monocrystalline silicon wafers directly affect the development of solar cells. Solar cells are typically produced by first cutting monocrystalline silicon rods into square rods, then cutting these square rods into whole silicon wafers. Multiple layers of films are then fabricated on these whole silicon wafers. Finally, the entire solar cell is cut into at least two shards, such as two half-cells. These sharded solar cells are then used to manufacture photovoltaic modules.

[0048] Currently, the fabrication of photovoltaic cells typically involves cutting round silicon rods grown using the Czochralski method into square silicon rods. These square rods are then chamfered and sliced ​​to obtain silicon wafers for photovoltaic cells. Photovoltaic cells often require laser dicing to create half-wafers. However, this method results in two sharp corners at the chamfered edges, leading to significant breakage during transportation and loading / unloading. Therefore, a silicon wafer with reduced breakage is urgently needed.

[0049] like Figure 1 and Figure 2 As shown, this embodiment of the present invention provides a silicon wafer 4, which has two opposing first sides 10 and two opposing second sides 20. One of the first sides 10 is connected to the two adjacent second sides 20 by a first chamfer 30, and the other first side 10 is connected to the two adjacent second sides 20 by a second chamfer 40. The first chamfer 30 and the second chamfer 40 have different shapes, and the ratio of the side length of the first side 10 to the side length of the second side is 1.2 to 6.

[0050] In the above-described technical solution, the silicon wafer 4 has two first chamfers 30 on one first side 10 and two second chamfers 40 on the other first side 10. The first chamfers 30 and the second chamfers 40 have different shapes, and the ratio of the side length of the first side 10 to the side length of the second side is 1.2 to 6. Because the silicon wafer of this application has the first chamfers 30 and the second chamfers 40, compared to sharp corners, the chamfers on the silicon wafer can reduce the breakage rate of the silicon wafer 4. The different shapes of the first chamfers 30 and the second chamfers 40 allow for identification of the orientation of the solar cells during subsequent cell fabrication, thus guiding the welding of the module end. Furthermore, when fabricating back-contact solar cells, the silicon wafer 4 of this application, with its first chamfers 30 and second chamfers 40 on opposite sides, allows for easy identification of the placement orientation of the solar cells through the different shapes of the first chamfers 30 and the second chamfers 40, assisting in the alignment of the PN regions between multiple solar cells and distinguishing the positive and negative electrodes of the solar cells. For example, when arranging multiple solar cells to form a battery string for a module, if each cell is placed in the same direction and aligned sequentially in a column with a first chamfer of 30°, a second chamfer of 40°, and so on, the P-region of the previous cell automatically aligns with the P-region or N-region of the next cell. This allows for convenient selection of suitable conductive interconnects and stringing processes to produce the battery module. Therefore, there is no need to add additional markings to the silicon wafers or solar cells, eliminating the marking process, saving time, and improving processing efficiency.

[0051] In some embodiments, the first chamfer 30 is an arc-shaped chamfer, and the second chamfer 40 is a linear chamfer. The first chamfer 30 and the second chamfer 40 have different shapes, and the differences between the arc-shaped chamfer and the linear chamfer are significant. In the subsequent battery manufacturing process, it is convenient to determine the orientation of the battery cell by identifying the shape of the chamfer. The arc-shaped chamfer can better utilize the area of ​​the silicon rod, thereby improving the utilization rate of the silicon rod. The linear chamfer can increase the surface area of ​​the silicon wafer, thereby increasing the power generation of the photovoltaic module made using such silicon wafer.

[0052] In some possible implementations, the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40. The projected length of the first chamfer 30 refers to its projection onto the first side 10 and / or the second side 20, and the projected length of the second chamfer 40 refers to its projection onto the first side 10 and / or the second side 20. The projection length of the first chamfer 30 being greater than the projection length of the second chamfer 40 means that the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than or equal to the projection length of the second chamfer 40 on the second side 20; or, the projection length of the first chamfer 30 on the first side 10 is greater than or equal to the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than the projection length of the second chamfer 40 on the second side 20. That is, when the projected length of the first chamfer 30 on the first side 10 is greater than the projected length of the second chamfer 40 on the first side 10, the projected length of the first chamfer 30 on the second side 20 cannot be less than the projected length of the second chamfer 40 on the second side 20, so that the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40. Alternatively, when the projected length of the first chamfer 30 on the second side 20 is greater than the projected length of the second chamfer 40 on the second side 20, the projected length of the first chamfer 30 on the first side 10 cannot be less than the projected length of the second chamfer 40 on the first side 10, so that the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40.

[0053] It should be noted that the projected length of the silicon wafer chamfer refers to the projected length on the first or second side of the silicon wafer after the edge or corner of the wafer has been chamfered. The shape of the silicon wafer chamfer can be an arc chamfer or a linear chamfer, where linear chamfers include right angles, bevels, etc.; arc chamfers include rounded chamfers, curved chamfers, etc. When the shape of the chamfer is a linear chamfer, the projected length mentioned in this application refers to the projected length of the linear chamfer on the first or second side.

[0054] The projected length of a chamfer can be measured using optical measurement, scanning microscopy, or other measurement methods to assess the size of the chamfer.

[0055] With the above scheme, compared to the second chamfer 40, the first chamfer 30 is larger and the second chamfer 40 is smaller. When using such a silicon wafer to fabricate solar cells, since the two opposite sides of the back-contact solar cell have different shapes (first chamfer 30 and second chamfer 40), and the different chamfer shapes on both sides, combined with the fact that the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40, makes it easier to distinguish the positive and negative electrodes of the solar cell. Therefore, there is no need to add additional markings to the silicon wafer or solar cell, eliminating the marking process, saving time, and improving processing efficiency.

[0056] In some embodiments, the projected length of the first chamfer 30 is 0.05mm to 9mm. That is, the projected length of the first chamfer 30 on the first side 10 and / or the second side 20 is greater than or equal to 0.05mm and less than or equal to 9mm. Specifically, the projected length of the first chamfer 30 can be 0.01mm, 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 3mm, 4mm, 4.8mm, 5mm, 6mm, 7mm, 7.5mm, 8mm, 9mm, etc.

[0057] When the above technical solution is adopted, if the projected length of the first chamfer 30 is less than 0.05mm, the projected length of the first chamfer 30 is too small, which will increase the area to be removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer. At the same time, the first chamfer 30 is too sharp, increasing the breakage rate of the silicon wafer during transportation or transfer. When the projected length of the first chamfer 30 is greater than 9mm, the chamfer of the silicon wafer is too large. Using such a silicon wafer to prepare solar cells results in a large blank area between solar cells, which affects the power generation of photovoltaic modules.

[0058] In some embodiments, the projected length of the second chamfer 40 is 0.01mm to 8.5mm. That is, the projected length of the second chamfer 40 on the first side 10 and / or the second side 20 is greater than 0.01mm and less than or equal to 8.5mm. Specifically, the projected length of the second chamfer 40 can be 0.01mm, 0.05mm, 0.1mm, 0.2mm, 0.5mm, 0.8mm, 1mm, 1.2mm, 1.5mm, 1.8mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 7.5mm, 8mm, 8.5mm, etc.

[0059] With the above technical solution, the projected length of the second chamfer 40 is greater than 0.01mm to prevent the chamfer from being too sharp and increasing the breakage rate of the silicon wafer during transportation or transfer; the projected length of the first chamfer 40 is less than or equal to 8.5mm to prevent the large chamfer of the silicon wafer from causing a large blank area between the cells, which would affect the power generation of the photovoltaic module.

[0060] Further, in this embodiment, the difference between the projected length of the first chamfer 30 on the first side 10 and the projected length on the second side 20 is 0mm to 2mm. Specifically, the difference can be 0, 0.2mm, 0.5mm, 0.8mm, 1mm, 1.2mm, 1.5mm, 1.7mm, 2mm, etc. That is, the projected length of the first chamfer 30 on the first side 10 and the projected length on the second side 20 can be the same or different. And / or, the difference between the projected length of the second chamfer 40 on the first side 10 and the projected length on the second side 20 is 0mm to 1mm. Specifically, the difference can be 0, 0.2mm, 0.5mm, 0.8mm, 1mm, etc. That is, the projected length of the second chamfer 40 on the first side 10 and the projected length on the second side 20 can be the same or different. When the projected lengths of the chamfer on the first and second sides are the same, it can be simply referred to as the projected length of the first chamfer 30 or the projected length of the second chamfer 40, simplifying the processing of the first chamfer 30 and the second chamfer 40. When the projected lengths of the chamfer on the first and second sides are different, the projected length of the first chamfer 30 on the first side 10 can be greater than the projected length of the first chamfer 30 on the second side 20, and the projected length of the second chamfer 30 on the first side 10 can be greater than or equal to the projected length of the second chamfer 40 on the second side 20. Since the first side 10 is the long side of the silicon wafer and the second side 20 is the short side of the silicon wafer, the projection of the chamfer on the long side is longer and the projection on the short side is shorter. Thus, the projections of the first chamfer on the first and second sides are different. Considering the different stress concentrations on different sides of the silicon wafer, setting the difference in the projection of the first chamfer on different sides within 0-2mm can reasonably alleviate the stress at the edge of the silicon wafer, prevent a large difference in the projection of the first chamfer on the first and second sides, and reduce the utilization rate of the silicon rod used for processing silicon.

[0061] For example, the projected length of the first chamfer 30 on the first side 10 is 0.05mm to 9mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, 6.5mm, 7mm, 7.5mm, 8mm, 8.5mm, 9mm, etc. The projected length of the first chamfer 30 on the second side 20 is 0.05mm to 7mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 4mm, 5mm, 6mm, 7mm, etc. It is acceptable as long as the projected length of the first chamfer 30 on the first side 10 is greater than the projected length on the second side 20.

[0062] For example, the projected length of the second chamfer 40 on the first side 10 is 0.05mm to 5mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. The projected length of the second chamfer on the second side is 0.05mm to 5mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. It is acceptable as long as the projected length of the second chamfer 40 on the first side 10 is greater than the projected length on the second side 20.

[0063] With the above technical solution, the projected length of the first chamfer on the first side can be greater than the projected length of the first chamfer on the second side, and the projected length of the second chamfer on the first side can be less than or equal to the projected length of the second chamfer on the second side. Because the projection of the first chamfer on the long side is longer, it effectively alleviates the problem of edge stress concentration corresponding to the long side; the projection on the short side is shorter, which alleviates stress concentration at the short edge while preventing excessively long projections on the short side from causing excessive blank space at the module end, thus affecting power generation.

[0064] In some embodiments, the difference between the projected length of the first chamfer 30 on the first side 10 and the projected length of the second chamfer 40 on the first side 10 is 0.05mm to 8mm, and the specific difference can be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projected length of the first chamfer 30 on the first side 10 is greater than the projected length of the second chamfer 40 on the first side 10.

[0065] And / or, the difference between the projected length of the first chamfer 30 on the second side 20 and the projected length of the second chamfer 40 on the second side 20 is 0.05mm to 8mm, and the specific difference can be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projected length of the first chamfer 30 on the second side 20 is greater than the projected length of the second chamfer 40 on the second side 20.

[0066] Within the aforementioned range, the size relationship between the first chamfer 30 and the second chamfer 40 can be easily observed visually. This prevents the difficulty in identifying the positive and negative electrode arrangement order of the solar cell fabricated from the silicon wafer if the difference is less than 0.05mm. Conversely, a difference greater than 8mm results in an excessively large projected length of the first chamfer 30, leading to excessive removal of the silicon rod during wafer fabrication, lower utilization of the silicon rod, and increased wafer fabrication costs. Alternatively, an excessively large difference could result in an excessively small second chamfer 40, causing stress concentration at the corners of the silicon wafer 4 and increasing the risk of breakage. Therefore, ensuring that the projected lengths of the first and second chamfers on the first and second sides of the silicon wafer are within the aforementioned range allows for identification of the chamfer size relationship, improves material utilization, and reduces the risk of breakage.

[0067] In some possible implementations, when the first chamfer 30 is an arc chamfer, the central angle of the arc chamfer is 2° to 6°. Specifically, it can be 2°, 2.5°, 3°, 3.5°, 4°, 4.5°, 5°, 5.5°, 6°, etc. The central angle of a chamfered wafer is the angle between the center of the silicon wafer and the two ends of the chamfer. The center of the silicon wafer is the intersection of the two diagonals. In practical applications, a silicon wafer is selected, and a point is chosen as the starting point along the intersection of the two diagonals. One end of the chamfer intersects the first side at the first point, and the other end of the chamfer intersects the second side of the wafer at the second point. Connecting the starting point of the diagonal intersection with the first point forms the first line segment, and connecting the starting point of the diagonal intersection with the second point forms the second line segment. The first and second line segments intersect at the starting point. The angle between the first and second line segments is the central angle, which can be measured using a micrometer or other precision instruments.

[0068] When the above technical solution is adopted, if the central angle of the arc chamfer is less than 2°, the arc chamfer is too small, which will increase the area to be removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer. At the same time, the arc chamfer is too sharp, increasing the breakage rate of silicon wafer during transportation or transfer. If the central angle of the arc chamfer is greater than 6°, the arc chamfer of the silicon wafer is too large. Using such silicon wafer to prepare solar cells results in a large blank area between solar cells, which affects the power generation of photovoltaic modules.

[0069] In some embodiments, the first included angle α between the tangent at the end of the arc-shaped chamfer connected to the first side 10 and the first side 10 is 30° to 55°, where the first included angle α is an acute angle, specifically 30°, 35°, 40°, 45°, 50°, 55°, etc. If the first included angle α between the tangent at the end of the arc-shaped chamfer connected to the first side 10 and the first side 10 is less than 30°, the chamfer is too sharp, leading to an increased breakage rate at the edge of the silicon wafer. If the first included angle α between the tangent at the end of the arc-shaped chamfer connected to the first side 10 and the first side 10 is greater than 55°, the projected length of the arc-shaped chamfer is large, resulting in more blank space at the module end, which affects the power generation of the photovoltaic module.

[0070] The second included angle β between the tangent at the other end of the arc chamfer that connects to the second side 20 and the second side 20 is 35° to 50°. The second included angle β is an acute angle, and the specific angle can be 35°, 40°, 45°, 50°, etc.

[0071] When the above technical solution is adopted, the second included angle between the tangent at the end of the arc chamfer that connects to the second side 20 and the second side 20 is 35° to 50°. Since the stress is relatively concentrated at the short edge of the silicon wafer, the second included angle β is within the above range, which can effectively reduce the breakage rate of the silicon wafer edge.

[0072] In some embodiments, when the second chamfer 40 is a linear chamfer, the angle between the linear chamfer and the first side 10 is 35° to 50°, specifically 35°, 40°, 45°, 50°, etc. The included angle is an acute angle, which facilitates the release of edge stress, reduces the sharp corner stress between the chamfer and the edge of the silicon wafer, and reduces the risk of edge breakage and microcracks in the silicon wafer.

[0073] In some possible implementations, the difference between the projected length of the first chamfer on the first side and the projected length of the second chamfer on the first side is 0.05mm to 8mm, specifically 0.05mm, 0.1mm, 0.5mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, etc.

[0074] And / or, the difference between the projected length of the first chamfer on the second side and the projected length of the second chamfer on the second side is 0.05mm to 8mm, specifically 0.05mm, 0.1mm, 0.5mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, etc.

[0075] When the above technical solution is adopted, the difference is within this range, which can make it easy to observe the size relationship between the first chamfer and the second chamfer with the naked eye. This prevents the difference from being less than 0.05mm, which makes it difficult to identify the positive and negative electrode arrangement order of the subsequently prepared solar cells. If the difference is greater than 8mm, the projected length of the first chamfer will be too large. In the silicon wafer preparation process, more silicon rods will be removed, resulting in low utilization of silicon rods and increased cost of silicon wafer preparation.

[0076] In some possible implementations, the first chamfer 30 is an arc-shaped chamfer or a linear chamfer; and / or, the second chamfer 40 is an arc-shaped chamfer or a linear chamfer. When the first chamfer 30 and the second chamfer 40 are arc-shaped chamfers, less part of the silicon rod is removed, thereby improving the utilization rate of silicon wafer cutting. The arc-shaped chamfer makes the transition between the first and second edges smooth, preventing excessive edge stress and excessive silicon wafer breakage during transportation or processing. When the first chamfer and the second chamfer are linear chamfers, compared with arc-shaped chamfers, the processing is simpler, the processing efficiency is improved, and the processing cost is reduced. The linear chamfer can increase the surface area of ​​the silicon wafer, thereby increasing the power generation of photovoltaic modules made using such silicon wafers.

[0077] In some embodiments, the length of the first side 10 is 182mm to 300mm. For those skilled in the art, the length of the first side can also refer to the long side distance. Due to the presence of chamfers, the length of the first side 10 can usually also be represented by the distance between the two opposing second sides 20, that is, the sum of the length of the first side 10 and the projected length of the two first chamfers 30 on the first side 10 is 182mm to 300mm, defined as the long side distance. The long side distance can specifically be 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc.; the second side 2 The length of 0 is 83mm to 150mm. For those skilled in the art, the second side 20 can also be defined as a short side distance. Due to the presence of chamfers, the length of the second side 20 can be defined as the distance between the two opposite first sides 10 being 83mm to 150mm. That is, the sum of the length of the second side 20, the projection length of the first chamfer 30 on the second side 20, and the projection length of the second chamfer 40 on the second side 20 is 83mm to 150mm, which is defined as the short side distance. The specific short side distance can be 83mm, 85mm, 90mm, 91mm, 96mm, 100mm, 105mm, 110mm, 115mm, 120mm, 125mm, 135mm, 145mm, 150mm, etc.

[0078] Those skilled in the art choose the first side 10 and the second side 20 within the aforementioned length range. Compared to other side lengths, the silicon rod has a higher utilization rate. At the same time, when using such silicon wafers to prepare battery modules, the blank area between the battery cells is small, which can maximize the use of the container size and improve the utilization rate of the container at the module end.

[0079] The silicon rod utilization data corresponding to silicon wafers with different edge distances and different sizes of first chamfer 30 and second chamfer 40 are shown in Table 1 below. The silicon rod utilization rate is the ratio of the area of ​​one side of the silicon wafer 4 prepared after slicing to the area of ​​the circular end face of the circular silicon rod 1 parallel to the slicing direction.

[0080] Table 1. Silicon rod utilization rates corresponding to different chamfer sizes on silicon wafers with different edge distances.

[0081]

[0082]

[0083] Based on the dimensions of the silicon wafer 4 in the above embodiments and the data in Table 1, it can be seen that in each embodiment, when the shapes of the first chamfer and the second chamfer are different, the utilization rate is higher than when the shapes of the first chamfer and the second chamfer are the same. Specifically, silicon wafers with arc-shaped chamfers and linear chamfers can improve the utilization rate of silicon rods compared to silicon wafers with the same chamfer shape. By comparing Embodiments 8 and 9 with Comparative Example 2, which have the same silicon rod diameter, it can be seen that although the side lengths of the first and second sides in Embodiments 8 and 9 are smaller than those in Comparative Example 2, Embodiments 8 and 9, by setting the projected length of the arc-shaped chamfer to be greater than that in Comparative Example 2, can form arc-shaped chamfers by using a small amount of grinding on the arc portion of the blank rod, reducing the cutting of the blank rod and improving the utilization rate of the silicon rod. By comparing Example 2, which has the same diameter of silicon rod, with Comparative Example 1, it can be seen that the length of the second side in Comparative Example 1 is 83 mm shorter than the length of the second side in this application, and its silicon rod utilization rate is the lowest. Similarly, in Comparative Example 2, the length of the first side of the silicon wafer is 300 mm longer than the length of the first side in this application, and its silicon rod utilization rate is also significantly lower than the silicon rod utilization rate of the silicon wafer size within the scope of this application.

[0084] like Figure 2As shown, in some embodiments, the surface of the silicon wafer 4 has a plurality of spaced-apart first ridges 50, the extension direction of which is the same as the extension direction of the first edge 10. It should be noted that the first ridges 50 are formed on the silicon wafer surface during the slicing process, through grinding between the dicing wires and the wafer surface. As the silicon rod feeds relative to the dicing wire mesh, the dicing wires bear pressure from the silicon rods, and while the dicing wires reciprocate, they bend to a certain extent in the feed direction, resulting in each first ridge 50 appearing as a visible arc on the silicon wafer surface. Figure 2 To illustrate the state of the first ridge 50 on the silicon wafer 4, a portion of the first ridge 50 is schematically drawn to show its outline and curvature, but does not represent the actual structure of the first ridge 50. Multiple first ridges 50 are densely arranged along the cutting direction as seen in the figure.

[0085] When the extension direction of the first ridge 50 is the same as the extension direction of the first side 10, the extension direction of the first electrode on the solar cell made from the silicon wafer is the same as the long side direction of the solar cell. In order to make the extension direction of the first electrode the same as the extension direction of the first ridge on the solar cell and reduce the risk of grid breakage of the first electrode caused by the first ridge, the extension direction of the first ridge 50 on the silicon wafer is the same as the long side direction of the silicon wafer 4, that is, the same as the extension direction of the first side 10.

[0086] In some embodiments, the spacing between two adjacent first textures 50 is 1mm to 4mm. Specifically, the spacing between two adjacent first textures 50 is 1mm, 2mm, 3mm, 4mm, etc. Since the first texture 50 is slightly curved and has a highest point and a lowest point, the distance between the highest point and the lowest point on the first texture 50 is 0.5mm to 4mm. Specifically, the distance between the highest point and the lowest point on the first texture 50 can be 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, etc.

[0087] When the spacing between two adjacent first ridges 50 is less than this range, the first ridges 50 are relatively dense, reducing the mechanical strength of the silicon wafer and lowering the efficiency of slicing by the cutting lines. If the spacing between the first ridges 50 is greater than this range, the spacing between the first ridges 50 is too large, affecting the appearance of the silicon wafer and easily causing slippage of conductive interconnects.

[0088] The spacing between two adjacent first ridges 50 refers to the distance between the lowest point or the highest point on the first ridge 50. This distance can be measured using a sorting machine or vernier calipers, or it can be obtained from data collected by a displacement sensor. This application does not impose specific limitations on this.

[0089] Since the first ridge 50 is arc-shaped, it has a highest point and a lowest point. The distance between the highest and lowest points on the first ridge 50 is 0.5mm to 4mm. Specifically, the distance between the highest and lowest points on the first ridge 50 can be 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, etc. When the distance between the highest and lowest points of the first ridge 50 is less than 0.5mm, it affects the cutting efficiency and increases the cutting cost; when the distance between the highest and lowest points of the first ridge 50 is greater than 4mm, it affects the flatness of the silicon wafer surface.

[0090] Based on the silicon wafer 4 described in any of the above embodiments, this utility model embodiment also provides a battery cell, which is prepared from the silicon wafer described in any of the above embodiments. The surface of the battery cell has a first electrode, which extends along a first side of the silicon wafer. The battery cell can be a back contact battery cell, with both positive and negative electrodes disposed on the back side of the battery cell.

[0091] In some possible implementations, the first electrode may include a main grid line and / or a sub-grid line. For a cell without a main grid line, since the sub-grid line is relatively small, the extension direction of the sub-grid line on the half-cell made from the silicon wafer in this application is parallel to the length direction of the cell, which can reduce the risk of grid breakage at the sub-grid line caused by the first ripple.

[0092] Since the solar cells are made from the silicon wafers described in any of the above embodiments, they have the same beneficial effects as the silicon wafers in the above embodiments, and will not be repeated here.

[0093] In some embodiments, the surface of the solar cell has a plurality of spaced-apart first ridges, and the extending direction of the first ridges is the same as the extending direction of the first electrode. This reduces the risk of grid breakage in the first electrode caused by the first ridges.

[0094] In some possible implementations, the number of first electrodes at the curved chamfer is greater than or equal to the number of first electrodes at the linear chamfer. By setting a reasonable number of electrodes in different regions of the silicon wafer, the maximum light absorption rate of the solar cell can be ensured, thereby improving the photoelectric conversion efficiency of the cell.

[0095] This utility model embodiment also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect. The conductive interconnect connects two adjacent solar cells, and the solar cells are as described in any of the above embodiments. The conductive interconnect extends along a first edge of the silicon wafer. The conductive interconnect can be a solder strip. One end of the conductive interconnect is connected to the positive electrode on the back of the previous solar cell, and the other end of the conductive interconnect is connected to the negative electrode on the back of the next solar cell, realizing the positive and negative electrode connection of adjacent solar cells. The positive and negative electrodes of the solar cells are identified and arranged according to the arc-shaped chamfer and linear chamfer on the cells to prevent incorrect connection of positive and negative electrodes.

[0096] Since the photovoltaic module includes solar cells, it has the same beneficial effects as the silicon wafers and solar cells described in any of the above embodiments, and will not be repeated here.

[0097] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0098] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A silicon wafer, characterized by, The silicon wafer has two opposite first edges and two opposite second edges, one of the first edges is connected with two adjacent second edges through a first chamfer, and the other first edge is connected with two adjacent second edges through a second chamfer; the first chamfer and the second chamfer are different in shape, and the length ratio of the first edge to the second edge is 1.2-6.

2. The silicon wafer of claim 1, wherein, The first chamfer is an arc chamfer, and the second chamfer is a linear chamfer.

3. The silicon wafer of claim 1, wherein, The projection length of the first chamfer is 0.05 mm-9 mm.

4. The silicon wafer of claim 1, wherein, The projection length of the second chamfer is 0.01 mm-8.5 mm.

5. The silicon wafer of claim 1, wherein, The difference between the projection length of the first chamfer on the first edge and the projection length of the first chamfer on the second edge is 0 mm-2 mm; And / or, the difference between the projection length of the second chamfer on the first edge and the projection length of the second chamfer on the second edge is 0 mm-1 mm.

6. The silicon wafer of claim 1, wherein, The projection length of the first chamfer on the first edge is 0.05 mm-9 mm, and the projection length of the first chamfer on the second edge is 0.05 mm-7 mm; And / or, the projection length of the second chamfer on the first edge is 0.05 mm-5 mm, and the projection length of the second chamfer on the second edge is 0.05 mm-5 mm.

7. The silicon wafer of claim 1, wherein, The difference between the projection length of the first chamfer on the first edge and the projection length of the second chamfer on the first edge is 0.05 mm-8 mm; And / or, the difference between the projection length of the first chamfer on the second edge and the projection length of the second chamfer on the second edge is 0.05 mm-8 mm.

8. The silicon wafer of claim 2, wherein, The central angle of the arc chamfer is 2°-6°.

9. The silicon wafer of claim 2, wherein, The first included angle between the tangent line of one end of the arc chamfer connected with the first edge and the first edge is 30°-55°; And / or, the second included angle between the tangent line of the other end of the arc chamfer connected with the second edge and the second edge is 30°-55°.

10. The silicon wafer of claim 2, wherein The included angle between the linear chamfer and the first edge is 35°-50°.

11. The silicon wafer of claim 1, wherein The length of the first edge is 182 mm-300 mm, and the length of the second edge is 83 mm-150 mm.

12. The silicon wafer of any of claims 1-11, wherein, The surface of the silicon wafer has a plurality of first textures arranged at intervals, and the extension direction of the first textures is the same as the extension direction of the first edge or the second edge.

13. The silicon wafer of claim 12, wherein, The distance between two adjacent first textures is 1 mm-4 mm, and the distance between the highest point and the lowest point on the first texture is 0.5 mm-4 mm.

14. A battery cell, characterized by The battery piece is prepared from the silicon wafer according to any one of claims 1-13, and the surface of the battery piece has a first electrode extending along the first edge of the silicon wafer.

15. The battery sheet of claim 14, wherein, The number of the first electrodes at the first chamfer is greater than or equal to the number of the first electrodes at the second chamfer.

16. The battery sheet of claim 14, wherein, The surface of the battery piece has a first texture, and the extension direction of the first texture is the same as that of the first electrode.

17. The battery sheet of claim 14, wherein, The first electrode is a sub-grid line.

18. A photovoltaic module comprising at least two cells and at least one electrically conductive interconnector connected between two adjacent cells, characterized in that, The battery piece is the battery piece according to any one of claims 14-17.

19. The assembly of claim 18, wherein, The conductive interconnect extends along a first edge of the silicon wafer. The conductive interconnect extends along a first edge of the silicon wafer.

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