Multi-area visual data processing display device

Abstract

The utility model provides a multi-area visual data processing display device, and belongs to the technical field of display devices. Comprising a main board, a central control unit, a partition control unit, a display screen and a data type identification module are arranged on the main board, the partition control unit is connected with the display screen, and the display screen can be divided into a plurality of areas by the partition control unit. According to the utility model, through close cooperation of core components such as the central control unit, the partition control unit, the data type identification module and the display screen, synchronous display of multiple data in multiple areas of the same screen is realized, and the purpose of conveniently carrying out association analysis is achieved; in addition, by means of collaborative operation among the data interface chip, the image processing unit and the control units, the effect that the data of the multiple data sources are accurately presented in different areas in various adaptive visualization forms is achieved.

Description

Technical Field

[0001] This utility model relates to the field of display device technology, and in particular to a multi-region visualization data processing display device. Background Technology

[0002] With the rapid development of information technology, the volume of data is exploding. In all fields, whether it's business operations, scientific research, or government decision-making, data plays a crucial role. To better understand and utilize this data, data visualization technology has emerged. Data visualization refers to presenting data in intuitive visual forms such as graphs, charts, and maps, enabling users to quickly identify patterns, trends, relationships, and outliers within the data. Through data visualization, complex data becomes easier to understand, helping users make more accurate and efficient decisions.

[0003] However, traditional data visualization techniques often present data using a single chart or a single full-screen function. For example, in business data analysis scenarios, to analyze sales and market share data, traditional techniques might only provide a single sales data bar chart or a full-screen pie chart of market share. This single display method forces users to frequently switch interfaces to view different data content when performing multi-data correlation analysis. This is not only cumbersome and time-consuming, but also makes it easy for users to miss key data information during the switching process, leading to biased understanding of the data and affecting the accuracy of decision-making. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a multi-area visualization data processing and display device, which solves the technical problems in traditional data visualization technology, such as the single or full-screen single-function display mode, which makes it cumbersome to switch interfaces and easy to miss information when performing multi-data correlation analysis, and the limitation of single chart display which cannot realize diversified processing of multiple data sources and thus cannot meet the user's needs for data integration and in-depth analysis.

[0005] Technical Solution: To achieve the above objectives, this utility model provides the following technical solution: A multi-area visualization data processing and display device, comprising: a motherboard, on which a central control unit, a partition control unit, a display screen, and a data type identification module are mounted; the partition control unit is connected to the display screen and can divide the display screen into multiple areas; the data type identification module is connected to the central control unit and is used to identify the type of incoming data; the central control unit controls the partition control unit to allocate different types of data to the corresponding areas of the display screen according to the identification results of the data type identification module, so as to realize the synchronous display of multiple data in multiple areas on the same screen; wherein the central control unit (MCU) can be selected from STMicroelectronics' STM32F4 series microcontroller as the central control unit, serving as the core control component of the device and responsible for coordination. The system includes a partition control unit (PCU) connected to the display screen, which handles data interaction and operation control between various modules. This PCU can utilize Texas Instruments' (TI) TMS320 series digital signal processor, which has built-in dedicated logic circuits and algorithms to divide the display screen into multiple areas. The display screen itself can be a Samsung UHD ultra-high-definition display, featuring a high-resolution, high-contrast panel capable of clearly displaying various data and image information. A data type recognition module, connected to the central control unit, can use a Xilinx FPGA (Field-Programmable Gate Array) chip, integrating advanced data recognition algorithms and high-speed data processing chips. A power supply module is also required on the motherboard, which supplies power to the various components on the motherboard through internal wiring.

[0006] In a further embodiment, the central control unit and the partition control unit are connected via an SPI bus, and a data type identification module is connected to the SPI bus. Specifically, the SCLK pin of the central control unit is connected to the SCLK pin of the partition control unit through the SCLK pin of the data type identification module; the MOSI pin of the central control unit is connected to the MOSI pin of the partition control unit through the MOSI pin of the data type identification module; the MISO pin of the central control unit is connected to the MISO pin of the partition control unit through the MISO pin of the data type identification module; and the SS pin of the central control unit is connected to the SS pin of the partition control unit through the SS pin of the data type identification module. The SPI bus adopts a master-slave mode, with the central control unit acting as the master device and the partition control unit and the data type identification module acting as slave devices. The data transmission mode is 8-bit or 16-bit data width, which can be selected according to the data type and transmission efficiency requirements. The rise and fall times of the signal on the SCLK pin are controlled between 5ns and 15ns to ensure the synchronization and stability of the data during transmission. The drive capability of the MOSI pin is 4mA-8mA, which can stably drive multiple slave devices. The input impedance of the MISO pin is 10kΩ-20kΩ to reduce the impact on the signal. The low-level active time of the SS pin is not less than 100ns to ensure that the slave device can correctly identify the selection signal.

[0007] In a further embodiment, a data interface chip and an image processing unit are included. The data interface chip is located in the external interface area on the motherboard and connected to the central control unit. The image processing unit is connected to the central control unit and the partition control unit. The data interface chip is used to access data from multiple data sources, and the image processing unit is used to perform diverse processing on the data from different data sources and display it in various visualization formats on different areas of the display screen. The data interface chip (DIC) can be a Realtek RTL8152 series data interface chip, such as the RTL8152B model. This chip supports multiple interface standards such as USB 3.0, Ethernet 10 / 100 / 1000Mbps, and HDMI 1.4, and is compatible with a wide range of external devices. The image processing unit (IPU) can be an NVIDIA Tegra series graphics processing unit, such as the Tegra X1 model. It integrates 256 CUDA cores, enabling parallel processing of large amounts of image and video data.

[0008] In a further embodiment, the connection pins between the data interface chip and the central control unit include: the TXD+ pin of the data interface chip is connected to the RXD+ pin of the central control unit, the TXD- pin of the data interface chip is connected to the RXD- pin of the central control unit, the RXD+ pin of the data interface chip is connected to the TXD+ pin of the central control unit, and the RXD- pin of the data interface chip is connected to the TXD+- pin of the central control unit; the image processing unit is connected to the central control unit via a data transmission line, specifically, the Data_In pin of the image processing unit is connected to the Data_Out pin of the central control unit, and the image processing unit is connected to the partition control unit via a display data signal line, that is, the Data_Out[X:0] pin of the image processing unit is connected to the corresponding data input pin of the partition control unit, wherein the output level of the TXD+ pin is 0-3.3V, conforms to the TTL level standard, and is compatible with the input level of the central control unit; the TXD- pin of the data interface chip is connected to the RXD- pin of the central control unit, and this set of pins is similar to the TXD+ and RXD+ pins mentioned above, forming a differential data transmission line. The common-mode rejection ratio (CMRR) of differential transmission is no less than 60dB, which effectively improves the anti-interference capability and transmission distance of data transmission, ensuring stable data transmission over long distances or in complex electromagnetic environments. The RXD+ pin of the data interface chip is connected to the TXD+ pin of the central control unit, and this set of pins enables reverse data transmission. When the central control unit needs to send control commands or feedback information to the data interface chip, it sends data to the RXD+ pin of the data interface chip through the TXD+ pin. The reverse data transmission rate is 1Mbps-10Mbps. The RXD- pin of the data interface chip is connected to the TXD- pin of the central control unit, forming a differential reverse transmission line with the aforementioned RXD+ and TXD+ pins, further enhancing the stability of reverse data transmission.

[0009] In a further embodiment, the motherboard is also provided with a storage chip, which is connected to the central control unit and is used to store the data transmitted by the data interface chip and the data processed by the image processing unit, so as to ensure the data temporary storage and retrieval requirements during the data processing process. The storage chip can be a Micron DDR4 series memory chip, such as the MT40A256M16GE-083E model.

[0010] In a further embodiment, the connection pins between the memory chip and the central control unit are as follows: the ADDR[X:0] pin of the central control unit is connected to the ADDR[X:0] pin of the memory chip, the DQ[Y:0] pin of the central control unit is connected to the DQ[Y:0] pin of the memory chip, the CAS# pin of the central control unit is connected to the CAS# pin of the memory chip, the RAS# pin of the central control unit is connected to the RAS# pin of the memory chip, and the WE# pin of the central control unit is connected to the WE# pin of the memory chip. The ADDR[X:0] pin (32-bit width, addressing 4GB) transmits the address signal, with an setup and hold time of 10-20ns; the DQ[Y:0] pin (16-bit width) reads and writes data, with a write time not exceeding 50ns and a read time not exceeding 40ns; the CAS# pin (pulse width 15-25ns) selects the column address and works with the RAS# pin (pulse width 20-30ns) for positioning; the WE# pin (rising and falling edges 5-10ns) enables writing, and the memory chip reads when the WE# pin is high, thus achieving efficient data reading and writing.

[0011] In a further embodiment, the partition control unit intelligently partitions the display screen according to data type information, and the partition control unit and the display screen are connected via display control signal lines. This includes connecting the HSYNC_Out pin of the partition control unit to the corresponding horizontal synchronization pin of the display screen, the VSYNC_Out pin to the corresponding vertical synchronization pin of the display screen, and the Disp_CLK pin to the corresponding clock pin of the display screen, so as to precisely control the display of data in each area of ​​the display screen. The HSYNC_Out pin (frequency 30kHz-80kHz, pulse width 1μs-5μs) sends a horizontal synchronization signal to control the start and end of each line of data, the VSYNC_Out pin (frequency 50Hz-75Hz, pulse width 1ms-5ms) sends a vertical synchronization signal to control the start and end of each frame of data, and the Disp_CLK pin (frequency 100MHz-200MHz) sends a display clock signal as a reference to ensure that the display screen displays accurate, stable, and smooth data.

[0012] In a further embodiment, a resistor is connected in series between the REF_CLK pin of the data interface chip and the CLK_OUT pin of the central control unit, and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the REF_CLK pin and the CLK_OUT pin, and the negative terminal is grounded to achieve stable, accurate and reliable signal transmission. The series resistor with an accuracy of ±1% and a resistance of 100Ω-500Ω limits the current (5mA-20mA) and attenuates the signal (attenuation amount 10%-30%) to prevent loss. The parallel 10pF-100pF ceramic chip capacitor filters the signal (high-frequency equivalent impedance less than 10Ω, filtering out high-frequency noise of 10MHz-100MHz). The combination of the two ensures stable signal transmission.

[0013] In a further embodiment, a pull-up resistor is connected in parallel on the connection line between the ADDR[X:0] pin on the central control unit and the ADDR[Y:0] pin on the memory chip. One end of the pull-up resistor is connected to the connection line between the ADDR[X:0] pin and the ADDR[Y:0] pin, and the other end is connected to the VCC pin on the memory chip. A resistor is connected in series between the DQ[Y:0] pin on the central control unit and the DQ[Y:0] pin on the memory chip, and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the DQ[Y:0] pin and the DQ[Y:0] pin, and the negative terminal is grounded to achieve stable and reliable data transmission. A 10kΩ carbon film pull-up resistor is connected in parallel to the VCC pin of the memory chip on the ADDR[X:0] pin connection line to ensure that the ADDR signal is stable at a high level when there is no transmission or a high impedance state, thereby enhancing signal stability and anti-interference. The DQ[Y:0] pins are connected in series with a ±5% carbon film resistor for current limiting and damage prevention, and for signal matching. A multilayer ceramic capacitor is connected in parallel to filter out high-frequency noise, thereby ensuring accurate and stable signal during data reading and writing, and achieving stable and reliable data transmission.

[0014] Beneficial effects: 1. Through the close cooperation of core components such as the central control unit, partition control unit, data type recognition module, and display screen, the synchronous display of multiple data in multiple areas on the same screen is realized, achieving the goal of conveniently conducting correlation analysis; the central control unit, as the core of data processing and scheduling, receives multi-source data from the data interface chip, and quickly directs the partition control unit to intelligently partition the display screen based on the accurate identification of data types by the data type recognition module; the partition control unit accurately allocates different types of data to the corresponding areas of the display screen, and the data display in each area is synchronized.

[0015] 2. By leveraging the collaborative operation of the data interface chip, image processing unit, and various control units, the system achieves the effect of accurately presenting data from multiple data sources in different areas using various adapted visualization formats. The data interface chip has a rich variety of interface types, allowing for the widespread access of data from multiple data sources such as databases, sensors, and network interfaces. The image processing unit, for different types of data, utilizes its powerful graphics processing capabilities and diverse algorithms to optimize and scale image data, adjust colors, and perform smooth decoding and frame rate adaptation on video data. Then, based on the resolution and display characteristics of different areas of the display screen, the processed data is output in the most suitable visualization format. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of this utility model.

[0018] Figure 2 This is the connection circuit diagram of this utility model.

[0019] The attached diagram is labeled as follows: 1. Motherboard; 2. Central control unit; 3. Data interface chip; 4. Partition control unit; 5. Image processing unit; 6. Memory chip; 7. Display screen. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions in this utility model are described clearly and completely. Obviously, the described embodiments are only some, not all, of the embodiments in this utility model. All other embodiments obtained by those skilled in the art based on the embodiments in this utility model without creative effort are within the scope of protection of this utility model.

[0021] This application provides a multi-region visualization data processing and display device, solving the technical problems of traditional data visualization technologies, such as cumbersome interface switching and easy information omission during multi-data correlation analysis due to single or full-screen single-function display modes, and the limitation of single chart display in failing to achieve diversified processing of multiple data sources, thus failing to meet users' needs for data integration and in-depth analysis. In practical use, it achieves the synchronous display of multiple data in multiple regions on the same screen, convenient correlation analysis without switching interfaces, and accurate presentation of data from multiple data sources in different regions using various adapted visualization formats.

[0022] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0023] Reference Figure 1-2A multi-area visualization data processing and display device includes: a motherboard 1, on which a central control unit 2, a partition control unit 4, a display screen 7, and a data type identification module are disposed. The partition control unit 4 is connected to the display screen 7 and can divide the display screen 7 into multiple areas. The data type identification module is connected to the central control unit 2 and is used to identify the type of data accessed. The central control unit 2 controls the partition control unit 4 to allocate different types of data to the corresponding areas of the display screen 7 according to the identification result of the data type identification module, so as to realize the synchronous display of multiple data in multiple areas on the same screen.

[0024] By integrating the motherboard 1, central control unit 2, partition control unit 4, display screen 7, and data type recognition module, a complete data processing and display system is constructed. It can centrally process multiple types of data and distribute them to different areas of the display screen 7 according to the data type, breaking the limitations of the traditional single display mode. This allows users to view different information from multiple sources of data on the same screen at the same time, greatly improving the richness of data visualization and information integration capabilities, and providing a convenient and intuitive platform for multi-data correlation analysis.

[0025] The central control unit 2 and the partition control unit 4 are connected via an SPI bus, and a data type identification module is connected to the SPI bus. Specifically, the SCLK pin of the central control unit 2 is connected to the SCLK pin of the partition control unit 4 through the SCLK pin of the data type identification module; the MOSI pin of the central control unit 2 is connected to the MOSI pin of the partition control unit 4 through the MOSI pin of the data type identification module; the MISO pin of the central control unit 2 is connected to the MISO pin of the partition control unit 4 through the MISO pin of the data type identification module; and the SS pin of the central control unit 2 is connected to the SS pin of the partition control unit 4 through the SS pin of the data type identification module.

[0026] By using the SPI bus to connect the central control unit 2 and the partition control unit 4 and connecting the data type identification module in series, the high speed, full-duplex and synchronous transmission of data between the modules are ensured. Precise clock signal control and specific pin connections enable control commands, data and status feedback to be transmitted accurately and quickly between the central control unit 2, the data type identification module and the partition control unit 4, effectively avoiding data transmission delays and errors, and ensuring the continuity and efficiency of the entire system's data processing flow.

[0027] The data interface chip 3 is located in the external interface area on the motherboard 1 and is connected to the central control unit 2. The image processing unit 5 is connected to the central control unit 2 and the partition control unit 4. The data interface chip 3 is used to access data from multiple data sources. The image processing unit 5 is used to perform diverse processing on data from different data sources and display it in various visualization forms on different areas of the display screen 7.

[0028] The data interface chip 3 is located in the external interface area of ​​the motherboard 1 and is connected to the central control unit 2. It can widely accept data from different data sources, such as various sensor data, network data, and external storage device data, thus broadening the data acquisition range of the system. The image processing unit 5 is connected to the central control unit 2 and the partition control unit 4. It can perform targeted processing on data from different data sources and convert them into various visualization forms suitable for display on the screen 7. For example, it can process geographic information data into map form, optimize and play surveillance video data, and draw statistical data into charts, thus enriching the data presentation methods, meeting the diverse needs of different users for data display, and making the data easier to understand and analyze.

[0029] The connection pins between the data interface chip 3 and the central control unit 2 include: the TXD+ pin of the data interface chip 3 is connected to the RXD+ pin of the central control unit 2, the TXD- pin of the data interface chip 3 is connected to the RXD- pin of the central control unit 2, the RXD+ pin of the data interface chip 3 is connected to the TXD+ pin of the central control unit 2, and the RXD- pin of the data interface chip 3 is connected to the TXD+- pin of the central control unit 2; the image processing unit 5 is connected to the central control unit 2 via a data transmission line, specifically, the Data_In pin of the image processing unit 5 is connected to the Data_Out pin of the central control unit 2, and the image processing unit 5 is connected to the partition control unit 4 via a display data signal line, that is, the Data_Out[X:0] pin of the image processing unit 5 is connected to the corresponding data input pin of the partition control unit 4.

[0030] The data interface chip 3 is connected to the central control unit 2 via specific pins (TXD+, TXD-, RXD+, RXD-), ensuring accurate data transmission and reception between the two. Both external data input and command output from the central control unit 2 can proceed stably. The pin connections between the image processing unit 5, the central control unit 2, and the partition control unit 4 establish a clear data transmission path, allowing the data to be processed to flow orderly from the central control unit 2 to the image processing unit 5. The processed results can then be accurately transmitted to the partition control unit 4 and displayed on the screen 7, avoiding data transmission chaos and errors, and improving the reliability and accuracy of data transmission.

[0031] The motherboard 1 is also equipped with a storage chip 6, which is connected to the central control unit 2 and is used to store the data transmitted from the data interface chip 3 and the data processed by the image processing unit 5, so as to ensure the data storage and retrieval needs during the data processing process.

[0032] The storage chip 6 on the motherboard 1 is connected to the central control unit 2, providing the system with the key function of data storage. During data processing, the raw data transmitted from the data interface chip 3 can be temporarily stored to avoid data loss or processing interruption due to transmission delay. At the same time, the data processed by the image processing unit 5 is stored for subsequent reuse or further analysis. This data storage and retrieval mechanism greatly improves the system's data processing efficiency and reduces the time cost of repeated data acquisition and transmission.

[0033] The connection pins between the memory chip 6 and the central control unit 2 are as follows: the ADDR[X:0] pin of the central control unit 2 is connected to the ADDR[X:0] pin of the memory chip 6, the DQ[Y:0] pin of the central control unit 2 is connected to the DQ[Y:0] pin of the memory chip 6, the CAS# pin of the central control unit 2 is connected to the CAS# pin of the memory chip 6, the RAS# pin of the central control unit 2 is connected to the RAS# pin of the memory chip 6, and the WE# pin of the central control unit 2 is connected to the WE# pin of the memory chip 6.

[0034] The central control unit 2 and the memory chip 6 are connected via pins such as ADDR, DQ, CAS#, RAS#, and WE#, forming a complete data read / write control system for the memory chip 6. The central control unit 2 can accurately send address signals to the memory chip 6 to determine the storage or retrieval location of data, and realize accurate data read / write operations through data signal pins. Meanwhile, the control pins such as CAS#, RAS#, and WE# work together to ensure the timing and correctness of read / write operations. This precise control mechanism enables the memory chip 6 to respond efficiently to the instructions of the central control unit 2, ensuring the orderly storage and rapid retrieval of data in the memory chip 6, and improving the data storage management capability of the entire system.

[0035] The partition control unit 4 intelligently partitions the display screen 7 according to the data type information, and the partition control unit 4 and the display screen 7 are connected through display control signal lines, including the HSYNC_Out pin of the partition control unit 4 being connected to the corresponding horizontal synchronization pin of the display screen 7, the VSYNC_Out pin being connected to the corresponding vertical synchronization pin of the display screen 7, and the Disp_CLK pin being connected to the corresponding clock pin of the display screen 7, so as to precisely control the display of data in each area of ​​the display screen 7.

[0036] The partition control unit 4 intelligently partitions the display screen 7 according to data type information and connects to the display screen 7 through pins such as HSYNC_Out, VSYNC_Out, and Disp_CLK, realizing precise control of the display in each area of ​​the display screen 7. It can dynamically divide the display screen 7 into areas according to different data types, so that various types of data are displayed in the most suitable area. At the same time, through horizontal synchronization, vertical synchronization and clock signals, it precisely controls the scanning and display sequence of data on the display screen 7, ensuring the stability and accuracy of data display, avoiding display problems such as screen tearing and flickering, and providing users with a clear and smooth multi-area data display experience.

[0037] A resistor is connected in series between the REF_CLK pin of the data interface chip 3 and the CLK_OUT pin of the central control unit 2, and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the REF_CLK pin and the CLK_OUT pin, and the negative terminal is grounded to achieve stable, accurate and reliable signal transmission.

[0038] A series resistor and a parallel capacitor are connected between the REF_CLK pin in the data interface chip 3 and the CLK_OUT pin in the central control unit 2. This effectively solves the problems of current control and noise interference during signal transmission. The series resistor limits the current to a reasonable range to prevent excessive current from damaging the central control unit 2, while also moderately attenuating the signal strength to avoid distortion. The parallel capacitor filters out high-frequency noise, ensuring that the signal transmitted from the data interface chip 3 to the central control unit 2 is pure and stable, thus guaranteeing the reliability and accuracy of signal transmission between the data interface and the central control unit 2.

[0039] A pull-up resistor is connected in parallel on the connection line between the ADDR[X:0] pin on the central control unit 2 and the ADDR[Y:0] pin on the memory chip 6. One end of the pull-up resistor is connected to the connection line between the ADDR[X:0] pin and the ADDR[Y:0] pin, and the other end is connected to the VCC pin on the memory chip 6. A resistor is connected in series with the DQ[Y:0] pin on the central control unit 2 and the DQ[Y:0] pin on the memory chip 6, and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the DQ[Y:0] pin and the DQ[Y:0] pin, and the negative terminal is grounded to achieve stable and reliable data transmission.

[0040] A pull-up resistor is connected in parallel between the ADDR[X:0] pin on the central control unit 2 and the ADDR[Y:0] pin on the memory chip 6, and a series resistor and a parallel capacitor are connected between the DQ[Y:0] pin on the central control unit 2 and the DQ[Y:0] pin on the memory chip 6. These components together ensure the stability of data transmission between the central control unit 2 and the memory chip 6. The pull-up resistor ensures that the ADDR signal remains at a stable high level when there is no transmission, reducing signal interference and misjudgment. The series resistor between the DQ pins limits the current to protect the chip and match the signal, and the parallel capacitor filters out high-frequency noise. This ensures that the signal is accurate and stable during the reading and writing process between the central control unit 2 and the memory chip 6, reducing the risk of data transmission errors and improving the reliability of data storage and retrieval.

[0041] During operation, the data interface chip 3 (DIC) is located in the external interface area of ​​the motherboard 1. It first receives data from multiple data sources, performs preliminary processing and buffering, and then transmits the data to the central control unit 2 (MCU). Data transmission and reception between the central control unit 2 and the data interface chip 3 are achieved through specific pin connections. The REF_CLK pin of the data interface chip 3 and the CLK_OUT pin of the central control unit 2 utilize series resistors for current limiting and signal attenuation, and parallel capacitors for filtering to ensure stable signal transmission. Simultaneously, the central control unit 2 and the partition control unit 4 (PCU) are connected via an SPI bus, on which a data type identification module (DTDM) is connected. The central control unit 2 generates a clock signal and transmits it sequentially to the partition control unit 4 through the data type identification module. Data and command interaction is achieved through the corresponding SCLK, MOSI, MISO, and SS pins of each unit. The central control unit 2 is also connected to the image processing unit 5 (IPU), transmitting data to it for processing. Data transmission occurs between the two units via the Data_In and Data_Out pins. After processing, the image processing unit 5 connects to the corresponding data input pin of the partition control unit 4 via the Data_Out[X:0] pin, transmitting the processed data to the partition control unit 4. The central control unit 2 is connected to the memory chip 6 (STM). Its ADDR[X:0] pin transmits address signals to determine data location, and its DQ[Y:0] pin transmits data signals to perform read / write operations. Parallel pull-up resistors are connected between ADDR pins to ensure signal stability, and series resistors are connected between DQ pins for current limiting and parallel capacitors for filtering, ensuring stable and reliable data transmission. The partition control unit 4 intelligently partitions the display screen 7 (DS) according to data type information. The HSYNC_Out, VSYNC_Out, and Disp_CLK pins are connected to the horizontal, vertical synchronization, and clock pins of the display screen 7, respectively, precisely controlling the display of data in each area. This ultimately achieves simultaneous display of multiple data sources in multiple areas on the same screen and precise presentation of data from multiple data sources in different areas using various adapted visualization formats.

[0042] The figures shown in the accompanying drawings are illustrative and are intended only to more intuitively demonstrate the key structure and connection relationships of the multi-area visualization data processing and display device of this utility model. In practical applications, the appearance and size of the device can be adjusted and optimized according to specific needs.

[0043] This utility model encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this utility model. To provide the public with a thorough understanding of this utility model, specific details have been described in detail in the above preferred embodiments; however, those skilled in the art can fully understand this utility model even without these detailed descriptions. Furthermore, to avoid unnecessary confusion regarding the essence of this utility model, well-known methods, processes, procedures, components, and circuits have not been described in detail.

[0044] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A multi-region visualization data processing and display device, characterized in that, include: The motherboard (1) is equipped with a central control unit (2), a partition control unit (4), a display screen (7), and a data type identification module. The partition control unit (4) is connected to the display screen (7) and can divide the display screen (7) into multiple areas. The data type identification module is connected to the central control unit (2) and is used to identify the type of data accessed. The central control unit (2) controls the partition control unit (4) to allocate different types of data to the corresponding areas of the display screen (7) according to the identification result of the data type identification module, so as to realize the synchronous display of multiple data in multiple areas on the same screen.

2. The multi-region visualization data processing and display device according to claim 1, characterized in that: The central control unit (2) and the partition control unit (4) are connected via an SPI bus, and a data type identification module is connected to the SPI bus. Specifically, the SCLK pin of the central control unit (2) is connected to the SCLK pin of the partition control unit (4) through the SCLK pin of the data type identification module; the MOSI pin of the central control unit (2) is connected to the MOSI pin of the partition control unit (4) through the MOSI pin of the data type identification module; the MISO pin of the central control unit (2) is connected to the MISO pin of the partition control unit (4) through the MISO pin of the data type identification module; and the SS pin of the central control unit (2) is connected to the SS pin of the partition control unit (4) through the SS pin of the data type identification module.

3. The multi-region visualization data processing and display device according to claim 1, characterized in that, Also includes: The data interface chip (3) and the image processing unit (5) are located in the external interface area on the motherboard (1) and connected to the central control unit (2). The image processing unit (5) is connected to the central control unit (2) and the partition control unit (4). The data interface chip (3) is used to access data from multiple data sources. The image processing unit (5) is used to perform diversified processing on data from different data sources and display it in various visualization forms in different areas of the display screen (7).

4. The multi-region visualization data processing and display device according to claim 3, characterized in that: The connection pins between the data interface chip (3) and the central control unit (2) include: the TXD+ pin of the data interface chip (3) is connected to the RXD+ pin of the central control unit (2), the TXD- pin of the data interface chip (3) is connected to the RXD- pin of the central control unit (2), the RXD+ pin of the data interface chip (3) is connected to the TXD+ pin of the central control unit (2), and the RXD- pin of the data interface chip (3) is connected to the TXD+- pin of the central control unit (2); the image processing unit (5) is connected to the central control unit (2) through a data transmission line, specifically, the Data_In pin of the image processing unit (5) is connected to the Data_Out pin of the central control unit (2), and the image processing unit (5) is connected to the partition control unit (4) through a display data signal line, that is, the Data_Out[X:0] pin of the image processing unit (5) is connected to the corresponding data input pin of the partition control unit (4).

5. The multi-region visualization data processing and display device according to claim 1, characterized in that: The motherboard (1) is also provided with a storage chip (6), which is connected to the central control unit (2) and is used to store the data transmitted by the data interface chip (3) and the data processed by the image processing unit (5) to ensure the data storage and retrieval needs during the data processing process.

6. The multi-region visualization data processing and display device according to claim 5, characterized in that: The connection pins between the memory chip (6) and the central control unit (2) are as follows: the ADDR[X:0] pin of the central control unit (2) is connected to the ADDR[X:0] pin of the memory chip (6), the DQ[Y:0] pin of the central control unit (2) is connected to the DQ[Y:0] pin of the memory chip (6), the CAS# pin of the central control unit (2) is connected to the CAS# pin of the memory chip (6), the RAS# pin of the central control unit (2) is connected to the RAS# pin of the memory chip (6), and the WE# pin of the central control unit (2) is connected to the WE# pin of the memory chip (6).

7. The multi-region visualization data processing and display device according to claim 1, characterized in that: The partition control unit (4) intelligently partitions the display screen (7) according to the data type information, and the partition control unit (4) and the display screen (7) are connected through display control signal lines, including the HSYNC_Out pin of the partition control unit (4) being connected to the corresponding horizontal synchronization pin of the display screen (7), the VSYNC_Out pin being connected to the corresponding vertical synchronization pin of the display screen (7), and the Disp_CLK pin being connected to the corresponding clock pin of the display screen (7), so as to precisely control the display of data in each area of ​​the display screen (7).

8. The multi-region visualization data processing and display device according to claim 4, characterized in that: A resistor is connected in series between the REF_CLK pin of the data interface chip (3) and the CLK_OUT pin of the central control unit (2), and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the REF_CLK pin and the CLK_OUT pin, and the negative terminal is grounded to achieve stable, accurate and reliable signal transmission.

9. A multi-region visualization data processing and display device according to claim 6, characterized in that: A pull-up resistor is connected in parallel on the connection line between the ADDR[X:0] pin on the central control unit (2) and the ADDR[Y:0] pin on the memory chip (6). One end of the pull-up resistor is connected to the connection line between the ADDR[X:0] pin and the ADDR[Y:0] pin, and the other end is connected to the VCC pin on the memory chip (6). A resistor is connected in series between the DQ[Y:0] pin on the central control unit (2) and the DQ[Y:0] pin on the memory chip (6), and a capacitor is connected in parallel. The positive terminal of the capacitor is connected to the connection line between the DQ[Y:0] pin and the DQ[Y:0] pin, and the negative terminal is grounded to achieve stable and reliable data transmission.

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