IC test carrier plate with FLASH chip

Abstract

The utility model discloses an IC test carrier plate with a FLASH chip, which is characterized in that a mother board is connected with a daughter board through a connector, the mother board can test data transmission of the FLASH chip, the daughter board can test output voltage of a controller connected with the FLASH chip, the same kind of chips can be tested on different controllers, and the test efficiency is improved. The power supply control module, the first interface module and the second interface module are arranged on the mother board, so that different chips can be connected into the mother board, the first voltage conversion module and the second voltage conversion module are arranged on the daughter board, so that the daughter board can perform different function and performance tests on the same chip, the circuit structure is simple, the operation is convenient, the test maintenance cost is reduced, and the test efficiency is improved. And the chip testing efficiency is also improved to a certain extent.

Description

Technical Field

[0001] This utility model belongs to the field of chip testing technology, and in particular relates to an IC test carrier board with a FLASH chip. Background Technology

[0002] After chip production, functional and performance testing is required. The main purpose of device testing is to ensure that the device can fully realize the functions and performance indicators specified in the design specifications under harsh environmental conditions. Currently, each IC test substrate on the market can usually only be used for one type of controller. Because the same chip requires different test substrates for different solutions and is inconvenient to switch between, it is necessary to purchase a large number of different types and quantities of IC test substrates, which increases testing costs and requires significant subsequent maintenance and development costs.

[0003] Therefore, there is a need to provide an IC test substrate with a FLASH chip to solve the aforementioned technical problems. Utility Model Content

[0004] To address the aforementioned issues, this invention provides an IC test carrier board with a FLASH chip, which can connect a motherboard and multiple daughterboards via connectors to perform various functional or performance tests on different ICs, thereby reducing testing and maintenance costs and improving IC testing efficiency.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This utility model provides an IC test carrier board with a FLASH chip, including a motherboard, multiple daughter boards and connectors. The motherboard is connected to the multiple daughter boards through the connectors. The motherboard is used to test the data transmission of the FLASH chip, and the daughter boards are used to test the output voltage of the controller connected to the FLASH chip.

[0007] The motherboard includes a power control module, a first interface module, and a second interface module. Both the first interface module and the second interface module are connected to the power control module. The first interface module is connected to the connector. The first interface module includes a VCCFQ signal connection unit, a VCCF signal connection unit, and an M.2 interface unit. The second interface module is connected to the M.2 interface unit.

[0008] The sub-board includes a first voltage conversion module and a second voltage conversion module. The first voltage conversion module includes a buck regulator unit, a voltage switching unit, and a voltage comparator unit. The VCCF signal connection unit, the voltage switching unit, and the voltage comparator unit are all connected to the buck regulator unit. The VCCFQ signal connection unit is connected to the voltage switching unit. One end of the second voltage conversion module is connected to the buck regulator unit, and the other end of the second voltage conversion module is connected to the voltage switching unit.

[0009] As a preferred embodiment of the above technical solution, the power control module includes a switch RK1, a fuse HF1, a chip HU1, and a fuse HF2. One end of the switch RK1 is connected to the voltage input terminal, and the other end of the switch RK1 is connected to the fuse HF1. ​​One end of both the fuse HF1 and the fuse HF2 is connected to the chip HU1. The chip HU1 is also connected in parallel to multiple capacitors, multiple resistors, multiple diodes, and an inductor. The other end of the fuse HF2 is connected to the voltage output terminal.

[0010] As a preferred embodiment of the above technical solution, the chip HU1 is model SY8205FCC, the voltage of the voltage input terminal is 12V, and the voltage of the voltage output terminal is 5V.

[0011] As a preferred embodiment of the above technical solution, the step-down voltage regulator unit includes a chip U1 and a first peripheral circuit. The chip U1 is connected to the first peripheral circuit, which includes multiple capacitors, multiple resistors, and an inductor connected in parallel. The voltage switching unit includes a switch K1, and the voltage comparison unit includes a chip U1A of model RS3515A.

[0012] As a preferred embodiment of the above technical solution, the second voltage conversion module includes a chip U2 and a second peripheral circuit. The chip is connected to the second peripheral circuit, and the second peripheral circuit includes multiple capacitors and multiple resistors connected in parallel.

[0013] As a preferred embodiment of the above technical solution, the chip U1 and the chip U2 are of model RS3413. The first voltage conversion module is used to convert the 5V input voltage to a 3.3V output voltage, and the second voltage conversion module is used to convert the 5V input voltage to a 1.8V output voltage or to convert the 5V input voltage to a 1.2V output voltage.

[0014] As a preferred embodiment of the above technical solution, the second interface module includes a data transceiver and a power receiver, wherein the data transceiver is connected to the M.2 interface unit and the power receiver is connected to the power control module.

[0015] As a preferred embodiment of the above technical solution, both the first interface module and the connector include an NGFF interface.

[0016] As a preferred embodiment of the above technical solution, the first interface module further includes a NOTCH unit located between the VCCF signal connection unit and the M.2 interface unit, the NOTCH unit being used to identify the access direction of the daughterboard.

[0017] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0018] By connecting the motherboard and daughterboard with connectors, the motherboard can test the data transmission of the FLASH chip, and the daughterboard can test the output voltage of the controller connected to the FLASH chip. This allows the same chip to be tested on different controllers. The motherboard is equipped with a power control module, a first interface module, and a second interface module, enabling the motherboard to connect to different chips. The daughterboard is equipped with a first voltage conversion module and a second voltage conversion module, allowing the daughterboard to perform different functional and performance tests on the same chip. The circuit structure is simple and easy to operate, reducing testing and maintenance costs and improving chip testing efficiency to a certain extent. Attached Figure Description

[0019] Figure 1 This is a structural block diagram of the IC test substrate with FLASH chip proposed in this utility model;

[0020] Figure 2 This is a circuit diagram of the power control module proposed in this utility model;

[0021] Figure 3 This is a circuit diagram of the first interface module proposed in this utility model;

[0022] Figure 4 This is a circuit diagram of the second interface module proposed in this utility model;

[0023] Figure 5 This is a circuit diagram of the first voltage conversion module proposed in this utility model;

[0024] Figure 6 This is a circuit diagram of the voltage comparison unit proposed in this utility model;

[0025] Figure 7 This is a circuit diagram of the second voltage conversion module proposed in this utility model;

[0026] Figure 8 The circuit diagram is for the connector proposed in this utility model.

[0027] The symbols for the main components are explained below:

[0028] 100 - Motherboard; 110 - Power control module; 120 - First interface module; 121 - VCCFQ signal connection unit; 122 - VCCF signal connection unit; 123 - M.2 interface unit; 130 - Second interface module; 200 - Daughterboard; 210 - First voltage conversion module; 211 - Buck regulator unit; 212 - Voltage switching unit; 213 - Voltage comparison unit; 220 - Second voltage conversion module; 300 - Connector. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0030] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0031] See Figure 1 This utility model provides an IC test carrier board with a FLASH chip, including a motherboard 100, multiple daughter boards 200 and a connector 300. The motherboard 100 is connected to the multiple daughter boards 200 through the connector 300. The motherboard 100 is used to test the data transmission of the FLASH chip, and the daughter boards 200 are used to test the output voltage of the controller connected to the FLASH chip.

[0032] The motherboard 100 includes a power control module 110, a first interface module 120, and a second interface module 130. Both the first interface module 120 and the second interface module 130 are connected to the power control module 110. The first interface module 120 is connected to the connector 300. The first interface module 120 includes a VCCFQ signal connection unit 121, a VCCF signal connection unit 122, and an M.2 interface unit 123. The second interface module 130 is connected to the M.2 interface unit 123.

[0033] The sub-board 200 includes a first voltage conversion module 210 and a second voltage conversion module 220. The first voltage conversion module 210 includes a buck regulator unit 211, a voltage switching unit 212, and a voltage comparator unit 213. The VCCF signal connection unit 122, the voltage switching unit 212, and the voltage comparator unit 213 are all connected to the buck regulator unit 211. The VCCFQ signal connection unit 121 is connected to the voltage switching unit 212. One end of the second voltage conversion module 220 is connected to the buck regulator unit 211, and the other end of the second voltage conversion module 220 is connected to the voltage switching unit 212.

[0034] In this embodiment, the power control module 110 includes a switch RK1, a fuse HF1, a chip HU1, and a fuse HF2. One end of the switch RK1 is connected to the voltage input terminal, and the other end of the switch RK1 is connected to the fuse HF1. ​​One end of each fuse HF1 and fuse HF2 is connected to the chip HU1. The chip HU1 is also connected in parallel with multiple capacitors, multiple resistors, multiple diodes, and an inductor. The other end of the fuse HF2 is connected to the voltage output terminal. The chip HU1 is model SY8205FCC, the voltage input terminal has a voltage of 12V, and the voltage output terminal has a voltage of 5V. The step-down voltage regulator unit 211 includes a chip U1 and a first peripheral circuit. The chip U1 is connected to the first peripheral circuit, which includes multiple capacitors, multiple resistors, and an inductor connected in parallel. The voltage switching unit 212 includes a switch K1, and the voltage comparison unit 213 includes a chip U1A of model RS3515A.

[0035] It should be noted that the second voltage conversion module 220 includes chip U2 and a second peripheral circuit. Chip U2 is connected to the second peripheral circuit, which includes multiple capacitors and multiple resistors connected in parallel. Chips U1 and U2 are of model RS3413. The first voltage conversion module 210 converts a 5V input voltage to a 3.3V output voltage, and the second voltage conversion module 220 converts a 5V input voltage to a 1.8V output voltage, or converts a 5V input voltage to a 1.2V output voltage. The second interface module 130 includes a data transceiver and a power receiver. The data transceiver is connected to the M.2 interface unit 123, and the power receiver is connected to the power control module 110. Both the first interface module 120 and the connector 300 include NGFF interfaces. The first interface module 120 also includes a NOTCH unit located between the VCCF signal connection unit 122 and the M.2 interface unit 123. The NOTCH unit is used to identify the access direction of the daughterboard 200.

[0036] Specifically, such as Figure 2 The power control module 110 mainly includes a switch RK1, a fuse HF1, resistors HR2, HR3, HR4, HR5, HR8, and HR9, capacitors HC1, HC2, HC3, HC4, HC5, HC6, HC7, HC8, HC9, and HC10, a chip HU1, a fuse HF2, a diode D2, a diode LED2, and an inductor HL1. Port 1 of switch RK1 is connected to the voltage input terminal, and port 2 of RK1 is connected to HF1. ​​HF1 is connected to HC1, HR3, and D2. Connect HC9, HR2, and pin 8 of chip HU1. D2 is connected in parallel with HC9. HC2 and HR3 are connected in parallel to pin 7 of chip HU1. HC2 and HC3 are connected to pin 6 of chip HU1. HR2 is connected to LED2. HR4, HR5, and HC4 are connected in parallel to pin 5 of chip HU1. HC7, HC8, and HC10 are connected in parallel to inductors HL1, HC5, and HF2. HF2 and HL1 are connected to pin 2 of chip HU1. HR8 and HR9 are connected in parallel to pin 3 of chip HU1. HC5 is connected to pin 1 of chip HU1. Pin 9 of chip HU1 is grounded. Pin 8 of chip HU1 receives 12V, and the output of HF2 is 5V.

[0037] Specifically, such as Figure 3 The first interface module 120 is designated CN1. A capacitor C1 is connected between pins 2 and 8 of CN1 and 5V is input. Pin 1 of CN1 is the VCCFQ signal connection unit 121. Pins 9 and 11 of CN1 are the VCCF signal connection unit 122. Pin 10 of CN1 outputs the signal F_VREF. CN1 includes a NOTCH unit and is used to output the signal PowerEN. CN1 can be connected to different storage devices such as solid-state drives and hard disk drives.

[0038] Specifically, such as Figure 4The second interface module 130 is designated CN2. CN2 consists of a 7-pin and a 15-pin connector. The 7-pin portion of CN2 is used for data transmission, i.e., the data transceiver. Pins P8 and P9 of the 15-pin portion of CN2 are connected to resistor R6. R6 is connected to the anode of diode D1, and the cathode of D1 is grounded. Both D1 and LED2 are light-emitting diodes and display red when powered on. Pin 8 of the 15-pin portion of CN2 receives 5V. Pin P11 of the 15-pin portion of CN2 is connected to pin 10 of CN1. The 15-pin portion of CN2 is used for power reception, i.e., the power receiver. Pins S2 of the 7-pin portion of CN2 are connected to C10, S3 to C11, S5 to C12, and S6 to C13. C10, C11, C12, and C13 output RX_P, RX_N, TX_N, and TX_P respectively and are connected to CN1, thereby improving the data transmission rate.

[0039] Specifically, such as Figure 5 , Figure 6 and Figure 8 The connector 300 includes pins corresponding to the VCCFQ signal connection unit 121, the VCCF signal connection unit 122, the NOTCH unit, and the M.2 interface unit 123. The step-down regulator unit 211 mainly includes a chip U1 and a first peripheral circuit. The first peripheral circuit includes capacitors C2, C3, C4, C5, C6, and C9, resistors R3, R4, and PB1, and an inductor L1. C2 and C3 are connected in parallel to pin 2 of the chip U1 to input a 5V voltage. R3, R4, and C9 are connected in parallel to pin 6 of the chip U1 to output the PEN signal. PB1 and C6 are connected in parallel to pin 1 of the chip U1. One end of L1 is connected to pin 3 of the chip U1, and the other end of L1 is connected to C6 and switch K1. C4 and C5 are connected in parallel to L1 and the VCCF signal connection unit 122. Switch K1 connects to four voltage divider resistors PA1, PA2, PA3, and PA4, with corresponding voltage ranges of 3.3V, 2.95V, 2.5V, and 1.2V. Pin 7 of switch K1 is connected to the VCCFQ signal connection unit 121. Voltage comparator unit 213 includes chip U1A, resistors R1 and R2, capacitors C7 and C8. R1 and R2 are connected in parallel to pins 9 and 10 of chip U1A; R2 and C7 are connected in parallel to pin 8 of chip U1A; C8 is connected to pin 7 of chip U1A; pins 1-3 of chip U1A are connected to pin 3 of chip U1; pin 6 of chip U1A is connected to pin 1 of chip U1; and pin 5 of chip U1A is connected to pin 6 of chip U1. Voltage comparator unit 213, in conjunction with voltage switching unit 212, can adjust the input voltage of buck regulator unit 211 to ensure normal and stable circuit operation.

[0040] Specifically, such as Figure 7The second voltage conversion module 220 includes a chip U2 and a second peripheral circuit. The second peripheral circuit includes capacitors C14, C15, C16, C17, and C18, resistors R5, PA5, and PB2, and inductor L2. C14 is connected to pin 2 of chip U2. One end of L2 is connected in parallel with C18 to pin 3 of chip U2, and the other end of L2 is connected to C17, PA5, C15, and C16. C15 and C16 are connected in parallel to the VCCFQ signal connection unit. One end of R5 is connected to pin 6 of chip U2, and the other end of R5 is connected to the VCCF signal connection unit. PB2, PA5, and C17 are connected in parallel to pin 1 of chip U2 and PA4 in the first voltage conversion module. The first voltage conversion module 210 and the second voltage conversion module 220 can effectively control the output voltage of the circuit to be suitable for various controllers, thereby improving the accuracy of IC testing.

[0041] This invention provides an IC test carrier board with a FLASH chip. A motherboard 100 and a daughterboard 200 are connected by a connector 300. The motherboard 100 can test the data transmission of the FLASH chip, and the daughterboard 200 can test the output voltage of the controller connected to the FLASH chip. This allows the same chip to be tested on different controllers. The motherboard 100 is equipped with a power control module 110, a first interface module 120, and a second interface module 130, enabling the motherboard 100 to connect to different chips. The daughterboard 200 is equipped with a first voltage conversion module 210 and a second voltage conversion module 220, enabling the daughterboard 200 to perform different functional and performance tests on the same chip. The circuit structure is simple and easy to operate, reducing testing and maintenance costs and improving chip testing efficiency to a certain extent.

[0042] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. An IC test substrate with a FLASH chip, characterized in that, It includes a motherboard, multiple daughterboards, and connectors. The motherboard is connected to the multiple daughterboards via the connectors. The motherboard is used to test the data transmission of the FLASH chip, and the daughterboards are used to test the output voltage of the controller connected to the FLASH chip. The motherboard includes a power control module, a first interface module, and a second interface module. Both the first interface module and the second interface module are connected to the power control module. The first interface module is connected to the connector. The first interface module includes a VCCFQ signal connection unit, a VCCF signal connection unit, and an M.2 interface unit. The second interface module is connected to the M.2 interface unit. The sub-board includes a first voltage conversion module and a second voltage conversion module. The first voltage conversion module includes a buck regulator unit, a voltage switching unit, and a voltage comparator unit. The VCCF signal connection unit, the voltage switching unit, and the voltage comparator unit are all connected to the buck regulator unit. The VCCFQ signal connection unit is connected to the voltage switching unit. One end of the second voltage conversion module is connected to the buck regulator unit, and the other end of the second voltage conversion module is connected to the voltage switching unit.

2. The IC test substrate with a FLASH chip according to claim 1, characterized in that, The power control module includes a switch RK1, a fuse HF1, a chip HU1, and a fuse HF2. One end of the switch RK1 is connected to the voltage input terminal, and the other end of the switch RK1 is connected to the fuse HF1. ​​One end of both the fuse HF1 and the fuse HF2 is connected to the chip HU1. The chip HU1 is also connected in parallel to multiple capacitors, multiple resistors, multiple diodes, and an inductor. The other end of the fuse HF2 is connected to the voltage output terminal.

3. The IC test substrate with a FLASH chip according to claim 2, characterized in that, The chip HU1 is model SY8205FCC, the voltage input terminal is 12V, and the voltage output terminal is 5V.

4. The IC test substrate with a FLASH chip according to claim 1, characterized in that, The step-down voltage regulator unit includes a chip U1 and a first peripheral circuit. The chip U1 is connected to the first peripheral circuit, which includes multiple capacitors, multiple resistors and an inductor connected in parallel. The voltage switching unit includes a switch K1, and the voltage comparison unit includes a chip U1A with model number RS3515A.

5. The IC test substrate with a FLASH chip according to claim 4, characterized in that, The second voltage conversion module includes a chip U2 and a second peripheral circuit. The chip is connected to the second peripheral circuit, which includes multiple capacitors and multiple resistors connected in parallel.

6. The IC test substrate with a FLASH chip according to claim 5, characterized in that, The chip U1 and the chip U2 are of model RS3413. The first voltage conversion module is used to convert the 5V input voltage to the 3.3V output voltage, and the second voltage conversion module is used to convert the 5V input voltage to the 1.8V output voltage, or to convert the 5V input voltage to the 1.2V output voltage.

7. The IC test substrate with a FLASH chip according to claim 1, characterized in that, The second interface module includes a data transceiver and a power receiver. The data transceiver is connected to the M.2 interface unit, and the power receiver is connected to the power control module.

8. The IC test substrate with a FLASH chip according to claim 1, characterized in that, Both the first interface module and the connector include NGFF interfaces.

9. The IC test substrate with a FLASH chip according to claim 8, characterized in that, The first interface module further includes a NOTCH unit located between the VCCF signal connection unit and the M.2 interface unit, the NOTCH unit being used to identify the access direction of the daughter board.

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