Electrostatic protection circuit, chip, display panel and display device

Abstract

The embodiment of the utility model provides an electrostatic protection circuit, a chip, a display panel and a display device. Relates to the technical field of electronic circuits, and comprises an electrostatic discharge module which comprises N potential nodes arranged in sequence and clamping circuits connected between every two adjacent potential nodes, the multiple clamping circuits are connected in series, the first potential node is connected with a first power supply end, and the Nth potential node is connected with a second power supply end, the potential nodes from the second potential node to the (N-1) th potential node are connected with different preset voltages. The signal input node is connected with a first potential node and an Nth potential node; the clamping circuits are configured to divide a voltage domain between the first potential node and the Nth potential node into at least two different voltage intervals, each voltage interval corresponds to a different clamping circuit, and charges corresponding to each voltage interval are discharged through the corresponding clamping circuit. The problem that an existing ESD circuit cannot adapt to a large-range cross-voltage scene can be solved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to an electrostatic discharge protection circuit, a chip, a display panel, and a display device. Background Technology

[0002] Electrostatic discharge (ESD) is a problem that must be considered in integrated circuit design. Because of its high voltage, it can generate a large current in an instant, forming a discharge pulse, which may cause permanent damage to sensitive semiconductor devices. In particular, when the chip's input / output interface is connected to external devices, it is easily affected by electrostatic shock, which is a major cause of chip failure. Therefore, it is necessary to design ESD protection circuits for chips to improve circuit reliability.

[0003] However, the large voltage variation range of existing I / O ports causes some components in the ESD circuit to be damaged during operation across a wide voltage range, ultimately leading to the failure of the ESD protection mechanism and damage to the internal circuitry of the chip. In other words, the existing ESD circuit cannot adapt to wide voltage range scenarios. Utility Model Content

[0004] This disclosure provides an electrostatic discharge (ESD) protection circuit, a chip, a display panel, and a display device to solve or alleviate the technical problem that existing ESD circuits cannot adapt to a wide range of voltage scenarios.

[0005] As a first aspect of the present disclosure, an embodiment of the present disclosure provides an electrostatic discharge (ESD) protection circuit, characterized in that it includes: an ESD discharge module, comprising N sequentially arranged potential nodes, and a clamping circuit connected between every two adjacent potential nodes, wherein multiple clamping circuits are connected in series, the first potential node is connected to a first power supply terminal, the Nth potential node is connected to a second power supply terminal, and each potential node from the 2nd to the (N-1th)th potential node is connected to a different preset voltage, wherein the preset voltage is located between the voltage of the first power supply terminal and the voltage of the second power supply terminal, and N is a positive integer greater than or equal to 3; a signal input node, wherein the signal input node is connected to the first potential node and the Nth potential node; the clamping circuit is configured to divide the voltage domain between the first potential node and the Nth potential node into at least two different voltage intervals, each voltage interval corresponding to a different clamping circuit, and the charge corresponding to each voltage interval is discharged through the corresponding clamping circuit.

[0006] As a second aspect of the present disclosure, an embodiment of the present disclosure provides a circuit board, including a substrate and at least one electrostatic discharge (ESD) protection circuit as described in any of the first aspects, the ESD protection circuit being located on one side of the substrate; for each ESD protection circuit, the substrate is provided with a clamping region corresponding to a clamping circuit in the ESD protection circuit, the clamping circuit in the ESD protection circuit being disposed in the clamping region, and a plurality of the clamping regions being arranged along a first direction; a plurality of first power traces are provided on one side of the substrate, the plurality of first power traces extending along the first direction, the first power traces being respectively connected to corresponding potential nodes in an ESD discharge module; at least a portion of the orthographic projection of the first power traces on the substrate is located within the clamping region.

[0007] As a third aspect of the present disclosure, the present disclosure provides a display panel including the circuit board described in any one of the second aspects.

[0008] As a fourth aspect of the present disclosure, the present disclosure provides a display device, including the display panel described in the present disclosure.

[0009] The technical solution of this disclosure provides an electrostatic discharge (ESD) protection circuit. By setting multiple series-connected clamping circuits between a first power supply terminal and a second power supply terminal, the clamping circuits are configured to divide the voltage domain between the first and second power supply terminals into at least two different voltage ranges. Each voltage range corresponds to a different clamping circuit, and the charge corresponding to each voltage range is discharged through the corresponding clamping circuit. This effectively prevents damage to components in the circuit due to excessive voltage difference between the first and second power supply terminals, enabling the ESD protection circuit to adapt to different voltage ranges. Even under wide voltage range scenarios, it can ensure voltage control and ESD discharge within each range. Furthermore, the introduction of clamping circuits can further refine the voltage gradient, enhancing the circuit's adaptability to different voltage ranges.

[0010] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0012] Figure 1 A schematic diagram of the existing technology is shown;

[0013] Figure 2 This diagram illustrates the structure of an electrostatic protection circuit provided in this embodiment.

[0014] Figure 3 Another structural schematic diagram of an electrostatic protection circuit provided in this embodiment is given;

[0015] Figure 4 A schematic diagram of the electrostatic discharge protection circuit provided in this embodiment is given;

[0016] Figure 5 This diagram illustrates the structure of a circuit board provided in this embodiment.

[0017] Figure 6 This diagram illustrates a telecommunications isolation structure provided in this embodiment.

[0018] Explanation of reference numerals in the attached figures:

[0019] Clamping circuit 100, connection port 101, delay circuit 102, inverter 103, substrate 200, first power supply trace 201, second power supply trace 202, clamping area 203, preset area 204, third power supply trace 205. Detailed Implementation

[0020] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0021] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate (also called the gate electrode), the signal input terminal is the source, and the signal output terminal is the drain. The switching transistors used in these embodiments can be P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high; an N-type transistor conducts when the gate is high and is cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential simply represent two different potential states of the signal, and do not imply that the first potential or the second potential has a specific value throughout the entire text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0022] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the utility model does not limit the coupling method between the two ends.

[0023] Figure 1 A schematic diagram of the existing technology is shown, such as Figure 1 As shown, related technologies typically employ a Power RC Clamp circuit structure for electrostatic discharge (ESD) protection to provide a low-impedance electrostatic discharge path. In practical applications, the I / O Pad is used to transmit voltages with a wide range of variations (e.g., -3 to 5V). Because the two ends of the Power RC Clamp need to be connected to the I / O Pad to transmit the maximum (5V) and minimum (-3V) voltages respectively to ensure that the ESD circuit stops working when the chip is powered on normally, the diodes or MOSFETs in the ESD circuit are damaged during operation across a wide voltage range, ultimately leading to the failure of the ESD protection mechanism and damage to the internal circuitry of the chip.

[0024] To address the problem that the large voltage variation range of existing I / O ports leads to the damage of some components in the electrostatic discharge (ESD) circuit under wide voltage range operation, ultimately causing the ESD protection mechanism to fail and the internal circuitry of the chip to be damaged, the existing ESD circuits cannot adapt to wide voltage range scenarios.

[0025] This application provides an electrostatic discharge (ESD) protection circuit. By setting multiple series-connected clamping circuits between a first power supply terminal and a second power supply terminal, the clamping circuits are configured to divide the voltage domain between the first and second power supply terminals into at least two different voltage ranges. Each voltage range corresponds to a different clamping circuit, and the charge corresponding to each voltage range is discharged through the corresponding clamping circuit. This effectively prevents damage to components in the circuit due to excessive voltage difference between the first and second power supply terminals, enabling the ESD protection circuit to adapt to different voltage ranges. Even under wide voltage range scenarios, it can ensure voltage control and ESD discharge within each range. Furthermore, the introduction of clamping circuits can further refine the voltage gradient, enhancing the circuit's adaptability to different voltage ranges.

[0026] Figure 2 This embodiment shows a schematic diagram of an electrostatic discharge (ESD) protection circuit. Figure 2 As shown, the electrostatic discharge circuit includes: an electrostatic discharge module 10 and a signal input node A. The electrostatic discharge module includes N potential nodes arranged sequentially. Figure 2 Power1 to PowerN in the diagram, and a clamping circuit 100 connected between every two adjacent potential nodes, where N is a positive integer greater than or equal to 3, and the clamping circuit 100 is as follows: Figure 2 Clamping circuits 1 to n are shown, with multiple clamping circuits 100 connected in series. The first potential node Power1 is connected to the first power supply terminal VDD, the Nth potential node PowerN is connected to the second power supply terminal VSS, and each of the second to (N-1)th potential nodes is connected to a different preset voltage. The preset voltage is located between the voltage of the first power supply terminal and the voltage of the second power supply terminal.

[0027] The preset voltage in this embodiment can be provided by an external power supply circuit or obtained by voltage division of the power supply that provides voltage to the protected device. This embodiment takes the external power supply circuit as an example. Different potential nodes can be connected to the external power supply circuit according to the voltage requirements, so as to input the preset voltage to each node.

[0028] In this embodiment, the protected device can be a chip or a circuit that integrates chips, transistors, and other components.

[0029] Signal input node A is connected to the first potential node and the Nth potential node, as follows: Figure 2 Signal input node A is connected to Power1 and the Nth potential node PowerN, thus forming a signal transmission path. When static electricity is present at signal input node A, it will be processed by a clamping circuit before entering the protected device. The clamping circuit can limit the voltage within a safe range, preventing damage to the protected device caused by overvoltage due to static electricity.

[0030] In this embodiment, the clamping circuit 100 is configured to divide the voltage domain between the first potential node and the Nth potential node into at least two different voltage intervals, each voltage interval corresponding to a different clamping circuit, and the charge corresponding to each voltage interval is discharged through the corresponding clamping circuit.

[0031] like Figure 2 As shown, the voltage domain between the first potential node and the Nth potential node is the voltage range spanned between VDD and VSS. There are n clamping circuits between the first and Nth potential nodes, meaning the voltage domain between them is divided into n distinct voltage intervals. These n voltage intervals correspond to clamping circuits 1 through n, where n is a positive integer greater than 2 and less than N. The charge corresponding to each voltage interval is discharged through clamping circuits 1 through n.

[0032] The above embodiments divide the voltage domain between the first and second power supply terminals into multiple voltage ranges by introducing different preset voltages. The charge corresponding to each voltage range is discharged through a corresponding clamping circuit. On the one hand, this allows the electrostatic discharge protection circuit to adapt to different voltage ranges, ensuring voltage control and electrostatic discharge within each range even under wide voltage cross-range scenarios. On the other hand, the clamping circuits are connected in series to form a multi-level protection mechanism. Even if one clamping circuit fails, the others can still function, avoiding ESD protection failure due to a single point of failure. The multi-clamping circuits can quickly respond and discharge electrostatic energy, preventing high voltage and high current from impacting sensitive semiconductor devices and extending the lifespan of the chips in the protected components.

[0033] In this embodiment, the voltage at the first power supply terminal is greater than 0, and the voltage at the second power supply terminal is less than 0. That is, VDD voltage is greater than 0 (positive voltage), and VSS voltage is less than 0 (negative voltage). This allows the electrostatic discharge (ESD) protection circuit to operate in both positive and negative power supply environments, covering the entire voltage range from positive to negative. The ESD protection circuit can simultaneously clamp and discharge both positive and negative static electricity, thus providing comprehensive ESD protection.

[0034] In the embodiments of this application, such as Figure 2 As shown, the electrostatic protection circuit also includes a first diode D1 and a second diode D2. The first diode D1 is disposed between the signal input node A and the first potential node. The positive terminal of the first diode D1 is connected to the signal input node A, and the negative terminal of the first diode D1 is connected to the first power supply terminal. The second diode D2 is disposed between the signal input node A and the Nth potential node. The negative terminal of the second diode D2 is connected to the signal input node A, and the positive terminal of the second diode D2 is connected to the Nth potential node.

[0035] The anode of the first diode D1 is connected to the signal input node A, and the cathode is connected to the first power supply terminal. Thus, in the event of an electrostatic discharge (ESD) event, if a forward high voltage occurs at the signal input node A, the first diode D1 can quickly conduct, discharging the electrostatic current to the first power supply terminal VDD, thereby protecting the downstream circuitry. Furthermore, the first diode D1 can limit the ESD voltage. When the voltage at the signal input node A exceeds the voltage at the first power supply terminal VDD, the first diode conducts in the forward direction, clamping the voltage to the level at the first power supply terminal. Under normal operating conditions, the first diode D1 is in a high-impedance state and will not affect signal transmission.

[0036] The cathode of the second diode D2 is connected to the signal input node A, and the anode is connected to the Nth potential node. Thus, in the event of an electrostatic discharge (ESD) event, if a negative high voltage occurs at the signal input node A, the second diode D2 can quickly conduct, discharging the electrostatic current to the Nth potential node, thereby protecting the downstream circuitry. Furthermore, the second diode D2 can limit the ESD voltage. When the voltage at the signal input node A is lower than the voltage at the second power supply terminal VSS, the second diode D2 conducts in reverse, clamping the voltage at the second power supply terminal. Under normal operating conditions, the second diode D2 is in a high-impedance state and will not affect signal transmission.

[0037] This embodiment of the application provides a first diode and a second diode, enabling signal input node A to simultaneously cope with both positive and negative electrostatic discharge shocks. This bidirectional protection mechanism ensures that signal input node A is effectively protected in electrostatic discharge events in any direction.

[0038] In this embodiment, the voltage of each potential node decreases sequentially from the first potential node to the Nth potential node. This sequential decrease in voltage creates a voltage gradient, allowing each clamping circuit to handle only a small voltage range, thus reducing the burden on individual clamping circuits and improving circuit reliability.

[0039] For example, when an electrostatic shock enters the circuit from signal input node A, clamping circuit 1 will respond first, clamping the voltage within the voltage range corresponding to the first potential node and the second potential node. If the voltage is still too high, clamping circuit 2 will continue to release the excess energy, and so on.

[0040] In this embodiment of the application, the electrostatic protection circuit further includes a connection port 101, which is connected to the signal input node A and is used to connect to an external device.

[0041] Connection ports include, for example, I / O ports, GPIO interfaces, USB, RS-232, RS-485, and other interfaces.

[0042] The connection port provides a channel for signal transmission between external devices and the circuit. The signal enters the circuit through the connection port and then enters the electrostatic discharge module through the signal input node, ensuring that the signal can be transmitted normally and is protected against electrostatic discharge during the transmission process.

[0043] Figure 3 Another structural schematic diagram of the electrostatic protection circuit provided in this embodiment is given. Figure 3 Preferably, the electrostatic discharge protection circuit includes two clamping circuits. When this circuit is applied in the liquid crystal driving circuit, VGH (Gate Voltage High) and VGL (Ground Voltage Low) are the gate driving voltage and source driving voltage, respectively, and AVSS is the reference voltage. VGH, VGL and AVSS each correspond to a potential node and are connected to different preset voltages.

[0044] In this embodiment of the application, the clamping circuit is configured with a first connection node and a second connection node. The first connection node of the i-th clamping circuit is connected to the i-th potential node, and the second connection node of the i-th clamping circuit is connected to the (i+1)-th potential node. i is a positive integer, 1≤i≤N-1.

[0045] For example, the first connection node of the first clamping circuit is connected to the first potential node, and the second connection node of the first clamping circuit is connected to the second potential node; the first connection node of the second clamping circuit is connected to the second potential node, and the second connection node of the second clamping circuit is connected to the third potential node. That is, multiple clamping circuits are connected in series in the direction from the first potential node to the Nth potential node. This connection method allows the clamping circuit to control the voltage difference between adjacent potential nodes and to discharge electrostatic energy after conduction.

[0046] Figure 4 A circuit structure diagram of an electrostatic discharge protection circuit provided in this embodiment is given, as follows: Figure 4 As shown, for each clamping circuit 100, the clamping circuit 100 includes a delay circuit 102, an inverter 103, and an electrostatic discharge (ESD) protection transistor Nmos2; the first terminal of the delay circuit 102, the first terminal of the inverter 103, and the first terminal of the ESD protection transistor Nmos2 are all connected to the first connection node of the clamping circuit, and the second terminal of the delay circuit 102, the second terminal of the inverter 103, and the second terminal of the ESD protection transistor Nmos2 are all connected to the second connection node of the clamping circuit; the third terminal of the delay circuit 102 is connected to the input terminal of the inverter 103, and the output terminal of the inverter 103 is connected to the third terminal of the ESD protection transistor Nmos2.

[0047] The delay circuit 102 is used to input a first level signal to the inverter 103; the first level signal is used to control the output terminal of the inverter 103 to output a target control signal, and the target control signal is used to control the first terminal and the second terminal of the electrostatic protection transistor Nmos2 to be turned on, so that the first connection node and the second connection node of the clamping circuit are turned on.

[0048] Delay circuits can introduce a time delay to ensure that the circuit has enough time to respond when an electrostatic discharge (ESD) occurs. This delay can prevent false triggering and ensure that signal changes can be accurately detected on the rising or falling edge of the ESD.

[0049] An inverter reverses the logic state of an input signal (e.g., converting a low level to a high level, or vice versa). This inverted signal can be used to control the conduction state of an electrostatic discharge (ESD) transistor.

[0050] After receiving the target control signal output by the inverter, the electrostatic protection transistor turns on its first and second terminals, thereby turning on the first and second connection nodes of the clamping circuit. When the electrostatic protection transistor is turned on, the voltage difference between adjacent potential nodes is quickly discharged, thereby protecting the circuit from electrostatic shock.

[0051] The clamping circuit, through the combination of a delay circuit, an inverter, and an electrostatic protection transistor, achieves rapid detection, delayed processing, and reliable discharge of electrostatic shocks, which can significantly improve the circuit's anti-static capability and overall reliability.

[0052] refer to Figure 3 and Figure 4 , Figure 4 Power1 in the middle is equivalent to Figure 3 VGH in Figure 4 Power2 in the middle is equivalent to Figure 3 AVSS in Figure 4 Power3 in the middle is equivalent to Figure 3In the VGL circuit, taking clamping circuit 1 as an example, the delay circuit includes a resistor R and a capacitor C. One end of resistor R is connected to Power1, and the other end of R is connected to one end of capacitor C. The other end of capacitor C is connected to Power2. The inverter includes a first transistor Pmos and a second transistor Nmos1. The gates of the first transistor Pmos and the second transistor Nmos1 are connected to the other end of R. The source of the first transistor Pmos is connected to Power1, and the drain of the first transistor Pmos is connected to the drain of the second transistor Nmos1. The source of the second transistor Nmos1 is connected to Power2. The drain of the first transistor Pmos is connected to the gate of the electrostatic discharge (ESD) protection transistor Nmos2. The drain of the ESD protection transistor Nmos2 is connected to Power1, and the source of the ESD protection transistor Nmos2 is connected to Power2.

[0053] When an electrostatic discharge (ESD) event occurs, such as at an I / O port, the voltage rises rapidly (within 10ns). Due to the RC delay, the voltage between R and C in delay circuit 102 remains low, providing a first-level input signal to inverter 103. This first-level signal is low and is inverted by the inverter, outputting a target control signal to ESD protection transistor Nmos2. The target control signal is the effective level of Nmos2. If the target control signal is high, Nmos2 conducts, and Power1 and Power2 also conduct. Similarly, Power2 and Power3 conduct, guiding the ESD signal from VDD to GND, thus achieving ESD protection between power and ground.

[0054] When the circuit of the protected component is powered on normally, the power-on time is generally about 1ms, which is much longer than the RC time constant. Therefore, there is enough time to fully charge the capacitor. In other words, the static electricity can be released before the capacitor is fully charged by several capacitors. When the circuit of the protected component is powered on normally, the electrostatic discharge protection transistor Nmos2 remains off, and the clamping circuit does not affect the normal operation of the circuit of the protected component.

[0055] In this embodiment of the application, N = 3, that is, as shown in the example. Figure 3 The electrostatic discharge protection circuit shown has a voltage greater than 0 at the first power supply terminal, a preset voltage of 0 at the second potential node, and a voltage less than 0 at the second power supply terminal.

[0056] With N=3, the electrostatic discharge (ESD) protection circuit divides the voltage range into two intervals (VDD to 0V and 0V to VSS) through two clamping circuits and a voltage gradient design. Each interval is protected by an independent clamping circuit, improving the precision and reliability of the protection. This achieves ESD protection from positive voltage to ground and then to negative voltage. This configuration effectively protects the circuit from both positive and negative ESD shocks while ensuring signal integrity and circuit reliability, significantly improving the circuit's ESD immunity.

[0057] Figure 5 This embodiment shows a schematic diagram of a circuit board structure, such as... Figure 5 As shown, this application embodiment provides a circuit board, which includes a substrate and at least one of the above-mentioned electrostatic discharge (ESD) protection circuits, the ESD protection circuits being located on one side of the substrate 200; for each ESD protection circuit, the substrate 200 is provided with a clamping region 203 corresponding to a clamping circuit in the ESD protection circuit, the clamping circuit in the ESD protection circuit being disposed in the clamping region 203, and a plurality of the clamping regions 203 being arranged along a first direction; a plurality of first power lines 201 are provided on one side of the substrate 200, the plurality of first power lines 201 extending along the first direction, the first power lines 201 being respectively connected to corresponding potential nodes in the ESD discharge module; at least a portion of the orthographic projection of the first power lines 201 on the substrate 200 is located within the clamping region 203.

[0058] In this embodiment, the substrate 200 serves as the basic structure of the circuit board, used to support various circuit components and traces.

[0059] The substrate 200 is provided with a clamping region 203 corresponding to the clamping circuit in the electrostatic discharge protection circuit. The clamping circuit in the electrostatic discharge protection circuit is set in the clamping region 203. That is, each clamping circuit is set in the corresponding clamping region 203. By integrating the clamping circuit on the substrate 200, the complexity of external connections is reduced and the reliability of the circuit is improved.

[0060] Multiple clamping regions 203 are arranged along the first direction. This arrangement makes the circuit board layout more regular and facilitates manufacturing and maintenance.

[0061] The first power trace 201 is the power trace used to connect the various potential nodes in the electrostatic discharge protection circuit and to transmit different preset voltages. At least a portion of the orthographic projection of the first power trace 201 onto the substrate 200 lies within the clamping region 203, which allows for a tight connection between the power trace and the clamping circuit, reducing trace length and parasitic effects. The first direction is, for example, horizontal; in one example, the first direction could also be vertical.

[0062] The circuit board in this embodiment has the advantages of high integration and reliable performance, making it suitable for high-density, high-reliability electronic devices and significantly improving the performance and reliability of the circuit board.

[0063] In this embodiment, the substrate 200 is provided with a plurality of preset regions 204. The first diode and the second diode in the electrostatic protection circuit are located in the preset regions 204. The plurality of preset regions 204 are arranged along a first direction. A plurality of second power lines 202 are also provided on one side of the substrate 200. The plurality of second power lines 202 extend along the first direction. The second power lines 202 are respectively connected to the corresponding diodes. At least a portion of the orthographic projection of the second power lines 202 on the substrate 200 is located within the preset regions 204.

[0064] The first power supply trace 201 connected to the first potential node is connected to the first power supply terminal, and the first power supply trace 201 connected to the Nth potential node is connected to the second power supply terminal; the second power supply trace 202 connected to the negative terminal of the first diode is connected to the first power supply terminal, and the second power supply trace 202 connected to the positive terminal of the second diode is connected to the second power supply terminal.

[0065] In this embodiment, multiple preset regions 204 are arranged along the first direction, making the layout of the circuit board more regular. The second power trace 202 extends along the first direction and is connected to the first diode and the second diode respectively. At least part of the orthographic projection of the second power trace 202 on the substrate 200 is located within the preset region 204. This design ensures the tight connection between the second power trace 202 and the diode, reducing trace length and parasitic effects.

[0066] In this embodiment, the first power supply trace 201 connected to the first potential node is connected to the first power supply terminal, and the first power supply trace 201 connected to the Nth potential node is connected to the second power supply terminal. This connection method ensures that the potential nodes of the electrostatic discharge module can obtain a stable power supply voltage.

[0067] In this embodiment, the second power supply trace 202, which is connected to the negative terminal of the first diode, is connected to the first power supply terminal, and the second power supply trace 202, which is connected to the positive terminal of the second diode, is connected to the second power supply terminal. This connection method provides a stable power supply for the first and second diodes, ensuring that they can function normally under electrostatic discharge (ESD) shocks.

[0068] The circuit board in this embodiment integrates the first diode and the second diode in the electrostatic protection circuit within a preset area 204, and achieves efficient and reliable electrostatic protection through an optimized design of the second power supply trace 202. The tight integration of the preset area 204 and the second power supply trace not only improves the circuit's anti-static capability but also reduces signal interference and improves signal integrity.

[0069] In this embodiment, for each electrostatic discharge protection circuit, the connection port in the electrostatic discharge protection circuit is located between the preset area 204 and the clamping area 203.

[0070] The connection port serves as the interface between external devices and the electrostatic discharge (ESD) protection circuit. It allows external signals to be introduced into the circuit and processed by the ESD protection module. The connection port is located between the preset region 204 and the clamping region 203. This layout facilitates easy connection of the connection port to the first diode (located in the preset region 204) and the clamping circuit (located in the clamping region 203). This layout reduces the path length of signals during transmission, thereby minimizing signal interference and parasitic effects.

[0071] This embodiment further optimizes the layout and function of the electrostatic discharge (ESD) protection circuit by placing the connection port between the preset area 204 and the clamping area 203. This layout not only improves the efficiency of ESD protection but also reduces the length of the signal transmission path, thereby reducing signal interference and parasitic effects. It is suitable for high-density, high-reliability electronic devices and can significantly improve the performance and reliability of the circuit board.

[0072] In this embodiment of the application, a plurality of third power lines 205 are also provided on one side of the substrate 200. The third power lines 205 extend along the second direction and are at least partially located between two adjacent preset regions 204. The second direction intersects with the first direction.

[0073] like Figure 5 As shown, the third power supply trace 205 extends along the second direction, which intersects with the first direction. Preferably, the second direction is perpendicular to the first direction. The third power supply trace 205 can be used as a power rail to access a preset voltage, or it can be used as a power supply transmission line for various components on the circuit board, such as providing working voltage for various components in the clamping circuit within the clamping area 203.

[0074] The third power supply trace 205 is located at least partially between two adjacent preset areas 204. This layout provides greater flexibility in power distribution and can better meet the power supply needs of different components.

[0075] In this embodiment, the substrate 200 includes a telecommunications isolation structure located in the clamping region 203. The clamping circuit is disposed within the telecommunications isolation structure, which is used to isolate signal interference between two adjacent clamping circuits.

[0076] In this embodiment, the telecommunications isolation structure can effectively reduce the impact of electromagnetic interference and noise. By isolating the signal paths between different clamping circuits, interference from high-frequency signals or electrostatic discharge to other circuits can be avoided.

[0077] In this embodiment, since the preset voltages are different, the voltages between different power lines may be different. That is, the electrostatic protection circuit in this embodiment uses different power domains, so a telecommunications isolation structure needs to be set up.

[0078] Specifically, Figure 6 This diagram illustrates a telecommunications isolation structure provided in this embodiment. Figure 6 As shown, the telecommunications isolation structure can be an N-well+DNW isolation structure. Using N-well and deep N-well (DNW) to isolate the clamping circuit can isolate signal interference between two adjacent clamping circuits and prevent crosstalk between the P-Sub (P-type substrate) on the substrate 200 and the power supply signals on the N-well.

[0079] This embodiment can effectively prevent potential conflicts and signal interference, and improve the circuit's ESD resistance.

[0080] In this embodiment, a display panel is also provided, including the circuit board described above.

[0081] For example, the aforementioned circuit board, especially its electrostatic discharge (ESD) protection circuit, is integrated into the display panel. This design ensures that the display panel can effectively resist ESD shocks in various usage scenarios (such as touch operation, signal transmission, etc.), protecting sensitive display driver circuits and pixel units. It is suitable for display panels requiring high ESD protection capabilities, such as touch screens, OLED displays, and LCD displays.

[0082] In this embodiment, a display device is also provided, which includes a display panel using the aforementioned embodiment. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0083] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0084] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0087] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0088] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0089] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that, include: An electrostatic discharge module includes N potential nodes arranged sequentially, and a clamping circuit connected between every two adjacent potential nodes. Multiple clamping circuits are connected in series. The first potential node is connected to a first power supply terminal, the Nth potential node is connected to a second power supply terminal, and each potential node from the 2nd to the (N-1)th potential node is connected to a different preset voltage. The preset voltage is located between the voltage of the first power supply terminal and the voltage of the second power supply terminal, where N is a positive integer greater than or equal to 3. A signal input node, wherein the signal input node is connected to the first potential node and the Nth potential node; The clamping circuit is configured to divide the voltage domain between the first potential node and the Nth potential node into at least two different voltage intervals, each voltage interval corresponding to a different clamping circuit, and the charge corresponding to each voltage interval is discharged through the corresponding clamping circuit.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The voltage at the first power supply terminal is greater than 0, and the voltage at the second power supply terminal is less than 0.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that, It also includes a first diode and a second diode. The first diode is disposed between the signal input node and the first potential node. The positive terminal of the first diode is connected to the signal input node, and the negative terminal of the first diode is connected to the first power supply terminal. A second diode is provided between the signal input node and the Nth potential node, with the negative terminal of the second diode connected to the signal input node and the positive terminal of the second diode connected to the Nth potential node.

4. The electrostatic protection circuit according to claim 1, characterized in that, From the first potential node to the Nth potential node, the voltage of each potential node decreases sequentially.

5. The electrostatic discharge protection circuit according to claim 1, characterized in that, It also includes a connection port, which is connected to the signal input node and is used to connect to external devices.

6. The electrostatic discharge protection circuit according to any one of claims 1-5, characterized in that, The clamping circuit is configured with a first connection node and a second connection node. The first connection node of the i-th clamping circuit is connected to the i-th potential node, and the second connection node of the i-th clamping circuit is connected to the (i+1)-th potential node. i is a positive integer, 1≤i≤N-1. For each clamping circuit, the clamping circuit includes a delay circuit, an inverter, and an electrostatic discharge (ESD) protection transistor; the first terminal of the delay circuit, the first terminal of the inverter, and the first terminal of the ESD protection transistor are all connected to the first connection node of the clamping circuit; the second terminal of the delay circuit, the second terminal of the inverter, and the second terminal of the ESD protection transistor are all connected to the second connection node of the clamping circuit; the third terminal of the delay circuit is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the third terminal of the ESD protection transistor. The delay circuit is used to input a first level signal to the inverter; The first level signal is used to control the output terminal of the inverter to output a target control signal. The target control signal is used to control the first and second terminals of the electrostatic protection transistor to be turned on, so that the first connection node and the second connection node of the clamping circuit are turned on.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that, N＝3， The voltage at the first power supply terminal is greater than 0, the preset voltage at the second potential node is equal to 0, and the voltage at the second power supply terminal is less than 0.

8. A circuit board, characterized in that, It includes a substrate and at least one electrostatic discharge (ESD) protection circuit as described in any one of claims 1-7, wherein the ESD protection circuit is located on one side of the substrate; For each electrostatic discharge protection circuit, the substrate is provided with a clamping region corresponding to the clamping circuit in the electrostatic discharge protection circuit, the clamping circuit in the electrostatic discharge protection circuit is disposed in the clamping region, and a plurality of the clamping regions are arranged along a first direction. Multiple first power lines are provided on one side of the substrate. The multiple first power lines extend along the first direction and are respectively connected to the corresponding potential nodes in the electrostatic discharge module. At least a portion of the orthographic projection of the first power trace onto the substrate lies within the clamping region.

9. The circuit board according to claim 8, characterized in that, The substrate is provided with a plurality of preset regions. The first diode and the second diode in the electrostatic protection circuit are located in the preset regions. The plurality of preset regions are arranged along the first direction. A plurality of second power lines are also provided on one side of the substrate. The plurality of second power lines extend along the first direction. The second power lines are respectively connected to the corresponding diodes. At least a portion of the orthographic projection of the second power lines on the substrate is located within the preset regions. The first power trace connected to the first potential node is connected to the first power terminal, and the first power trace connected to the Nth potential node is connected to the second power terminal; the second power trace connected to the negative terminal of the first diode is connected to the first power terminal, and the second power trace connected to the positive terminal of the second diode is connected to the second power terminal.

10. The circuit board according to claim 9, characterized in that, For each electrostatic discharge (ESD) protection circuit, the connection port in the ESD protection circuit is located between the preset region and the clamping region.

11. The circuit board according to claim 9, characterized in that, The substrate is further provided with a plurality of third power lines on one side. The third power lines extend along a second direction and are at least partially located between two adjacent preset areas. The second direction intersects with the first direction.

12. The circuit board according to claim 8, characterized in that, The substrate includes a telecommunications isolation structure located in the clamping region, and the clamping circuit is disposed within the telecommunications isolation structure. The telecommunications isolation structure is used to isolate signal interference between two adjacent clamping circuits.

13. A display panel, characterized in that, The circuit board includes any one of claims 8 to 12.

14. A display device, characterized in that, Includes the display panel as described in claim 13.

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