Power module and vehicle

Abstract

The utility model provides a power module and a vehicle. The power module comprises a substrate, the substrate is provided with a first positive terminal connection area, a second positive terminal connection area, a neutral terminal connection area, a first negative terminal connection area and a second negative terminal connection area, and the power module is provided with a first commutation loop and a second commutation loop. The first commutation loop comprises a first commutation path from the first positive terminal connection area to the neutral terminal connection area and a second commutation path from the second positive terminal connection area to the neutral terminal connection area; the second commutation loop comprises a third commutation path from the first negative terminal connection area to the neutral terminal connection area and a fourth commutation path from the second negative terminal connection area to the neutral terminal connection area, and the first commutation path and the second commutation path are symmetrically arranged relative to the center line of the substrate; and the third commutation path and the fourth commutation path are symmetrically arranged relative to the center line of the substrate. According to the invention, the stray inductance of the commutation loop can be reduced and the electrical reliability is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of power electronics, and particularly relate to a power module and a vehicle. BACKGROUND

[0002] With the continuous heat of the domestic new energy vehicle market, the development of the power module as a core component of the new energy vehicle is also widely concerned. The reliability of the power module is directly related to the use safety of the new energy vehicle, and therefore higher requirements are put forward for the reliability of the power module.

[0003] Compared with the conventional two-level power module, the three-level power module has two commutation loops. The path of the commutation loop in the conventional three-level power module is relatively long, and the corresponding commutation loop inductance is much larger than that of the conventional half-bridge circuit. Especially when multiple chips are connected in parallel, the path of the commutation loop is longer, resulting in larger commutation loop inductance. A large voltage spike is generated on the chip during the switching process of the power module, causing voltage overstress, which will lead to low electrical reliability of the three-level power module in the long term. CONTENT OF THE UTILITY MODEL

[0004] Embodiments of the present application aim to provide a power module and a vehicle, which can reduce the inductance of the commutation loop and improve the electrical reliability.

[0005] One aspect of embodiments of the present application provides a power module. The power module includes a substrate, the substrate is provided with a first positive terminal connection area, a second positive terminal connection area, a neutral terminal connection area, a first negative terminal connection area and a second negative terminal connection area, the power module has a first commutation loop and a second commutation loop, the first commutation loop includes a first commutation path from the first positive terminal connection area to the neutral terminal connection area and a second commutation path from the second positive terminal connection area to the neutral terminal connection area; the second commutation loop includes a third commutation path from the first negative terminal connection area to the neutral terminal connection area and a fourth commutation path from the second negative terminal connection area to the neutral terminal connection area, wherein the first commutation path and the second commutation path are symmetrically arranged with respect to the center line of the substrate, and the third commutation path and the fourth commutation path are symmetrically arranged with respect to the center line of the substrate.

[0006] Further, the power module includes a first chip group, a second chip group, a third chip group and a fourth chip group, the first chip group, the second chip group, the third chip group and the fourth chip group are symmetrically arranged on the substrate with respect to the center line of the substrate.

[0007] Further, the fourth chip group, the first chip group, the second chip group and the third chip group are arranged in parallel along a first direction of the substrate, and the chips included in each of the first chip group, the second chip group, the third chip group and the fourth chip group are arranged in sequence along a second direction of the substrate, the first direction being perpendicular to the second direction.

[0008] Further, the neutral terminal connection area is symmetrically arranged with respect to a center line of the substrate, the first positive terminal connection area and the second positive terminal connection area are symmetrically arranged on opposite sides of the neutral terminal connection area, and the first negative terminal connection area and the second negative terminal connection area are symmetrically arranged on opposite sides of the neutral terminal connection area and respectively located outside the first positive terminal connection area and the second positive terminal connection area.

[0009] Further, the substrate is further provided with an alternating current terminal connection area, the substrate has a first end and a second end opposite to each other along the first direction, the first positive terminal connection area, the second positive terminal connection area, the neutral terminal connection area, the first negative terminal connection area and the second negative terminal connection area are located at the first end of the substrate, and the alternating current terminal connection area is located at the second end of the substrate.

[0010] Further, the substrate includes first, second, third, fourth, fifth and sixth conductive areas which are spaced apart from each other, wherein the neutral terminal connection area and the second chip group are located in the first conductive area, the first positive terminal connection area, the second positive terminal connection area and the first chip group are located in the second conductive area, the first negative terminal connection area is located in the third conductive area, the second negative terminal connection area is located in the fourth conductive area, the fourth chip group and the alternating current terminal connection area are located in the fifth conductive area, and the third chip group is located in the sixth conductive area.

[0011] Further, the substrate further comprises a seventh conductive region, an eighth conductive region, a ninth conductive region, a tenth conductive region, an eleventh conductive region, a twelfth conductive region and a thirteenth conductive region, wherein the seventh conductive region and the eighth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, and serve as a driving source electrode loop and a driving gate electrode loop of the fourth chip group, respectively; the ninth conductive region and the tenth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, and serve as a driving source electrode loop and a driving gate electrode loop of the first chip group, respectively; the eleventh conductive region, the twelfth conductive region and the thirteenth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, the twelfth conductive region serves as a common source electrode driving loop of the second chip group and the third chip group, and the eleventh conductive region and the thirteenth conductive region serve as a driving gate electrode loop of the third chip group and the second chip group, respectively.

[0012] Further, the power module further comprises a first bonding wire group, a second bonding wire group and a third bonding wire group, wherein the first bonding wire group is electrically connected with the third conductive region, a source electrode of the fourth chip group and the fourth conductive region along the second direction, respectively; the second bonding wire group is electrically connected with the fifth conductive region, a source electrode of the first chip group and the sixth conductive region along the first direction, respectively; and the third bonding wire group is electrically connected with a source electrode of the third chip group and a source electrode of the second chip group along the first direction, respectively.

[0013] Further, the power module comprises a positive electrode power terminal, a neutral power terminal and a negative electrode power terminal, the positive electrode power terminal has a positive electrode planar main body part and a positive electrode connecting part connected with the positive electrode planar main body part, the positive electrode connecting part is electrically connected with the first positive electrode terminal connecting area and the second positive electrode terminal connecting area; the neutral power terminal has a neutral planar main body part and a neutral connecting part connected with the neutral planar main body part, the neutral connecting part is electrically connected with the neutral terminal connecting area; the negative electrode power terminal has a negative electrode planar main body part and a negative electrode connecting part connected with the negative electrode planar main body part, the negative electrode connecting part is electrically connected with the first negative electrode terminal connecting area and the second negative electrode terminal connecting area, wherein the positive electrode planar main body part, the neutral planar main body part and the negative electrode planar main body part are arranged in a manner of overlapping and spacing, and the neutral planar main body part is located between the positive electrode planar main body part and the negative electrode planar main body part.

[0014] Yet another aspect of the embodiments of the present application provides a vehicle. The vehicle comprises the power module as described above.

[0015] The power module and the vehicle of one or more embodiments of the present application reduce the inductance of the whole module by forming two first commutation paths and two second commutation paths in the module, respectively, and by making the two first commutation paths and the two second commutation paths be annular and left-right symmetrical, so that the inductance of the whole commutation loop is equivalent to the parallel connection of the inductance of the two commutation paths, thereby improving the electrical reliability. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A circuit schematic diagram of the power module of one embodiment of the present application.

[0017] Figure 2 A simplified schematic diagram of the commutation loop of the power module of one embodiment of the present application.

[0018] Figure 3 A structural schematic diagram of the power module of one embodiment of the present application.

[0019] Figure 4 An exploded schematic diagram of the positive power terminal, the negative power terminal and the neutral power terminal of one embodiment of the present application.

[0020] Figure 5 An assembled schematic diagram of the positive power terminal, the negative power terminal and the neutral power terminal. Figure 4

[0021] A side view of the positive power terminal, the negative power terminal and the neutral power terminal. Figure 6 Figure 5 An exploded schematic diagram of the positive power terminal, the negative power terminal and the neutral power terminal of another embodiment of the present application.

[0022] Figure 7 An assembled schematic diagram of the positive power terminal, the negative power terminal and the neutral power terminal.

[0023] Figure 8 Figure 7 A side view of the positive power terminal, the negative power terminal and the neutral power terminal.

[0024] Figure 9 A side view of the positive power terminal, the negative power terminal and the neutral power terminal. Figure 8 DETAILED DESCRIPTION

[0025] ​​​Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0026] The power modules and vehicles of various embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Figure 1 A circuit diagram of a power module 1 according to an embodiment of this application is disclosed. Figure 2 A simplified schematic diagram of the commutation circuit of a power module 1 according to an embodiment of this application is shown. (Referring to...) Figure 1 and Figure 2 As shown, in one embodiment of this application, the power module 1 is a three-level power module. The power module 1 includes a positive power terminal DC+, a neutral power terminal N, a negative power terminal DC-, a first chip T1, a second chip T2, a third chip T3, and a fourth chip T4. The power module 1 has a first commutation circuit and a second commutation circuit. The first commutation circuit runs from the positive power terminal DC+ through the first chip T1, the third chip T3, and the second chip T2 to the neutral power terminal N; the second commutation circuit runs from the negative power terminal DC- through the fourth chip T4, the third chip T3, and the second chip T2 to the neutral power terminal N.

[0028] The following will combine Figure 3 This application details how it addresses the spurious inductance problem in the converter circuit by altering the internal layout of the power module 1.

[0029] Figure 3 A schematic diagram of the structure of a power module 1 according to an embodiment of this application is disclosed, as shown below. Figure 3 As shown, a power module 1 in one embodiment of this application includes a substrate 100, which may include, but is not limited to, a ceramic substrate 100.

[0030] The substrate 100 is provided with a first positive terminal connection area 1211, a second positive terminal connection area 1212, a neutral terminal connection area 1220, a first negative terminal connection area 1231 and a second negative terminal connection area 1232.

[0031] like Figure 3As shown by the thick solid line in FIG. 1, the first commutation loop of the power module 1 includes a first commutation path from the first positive terminal connection area 1211 to the neutral terminal connection area 1220 and a second commutation path from the second positive terminal connection area 1212 to the neutral terminal connection area 1220, and the first commutation path and the second commutation path are in parallel connection.

[0032] As shown by the thick solid line in FIG. 1, the first commutation loop of the power module 1 includes a first commutation path from the first positive terminal connection area 1211 to the neutral terminal connection area 1220 and a second commutation path from the second positive terminal connection area 1212 to the neutral terminal connection area 1220, and the first commutation path and the second commutation path are in parallel connection. Figure 3 As shown by the thick dashed line in FIG. 1, the second commutation loop includes a third commutation path from the first negative terminal connection area 1231 to the neutral terminal connection area 1220 and a fourth commutation path from the second negative terminal connection area 1232 to the neutral terminal connection area 1220, and the third commutation path and the fourth commutation path are in parallel connection.

[0033] As shown by the thick dashed line in FIG. 1, the second commutation loop includes a third commutation path from the first negative terminal connection area 1231 to the neutral terminal connection area 1220 and a fourth commutation path from the second negative terminal connection area 1232 to the neutral terminal connection area 1220, and the third commutation path and the fourth commutation path are in parallel connection.

[0034] The power module 1 of the present application reduces the commutation loop inductance in the entire module by forming two ring-shaped and left-right symmetrical first commutation paths and second commutation paths and two ring-shaped and left-right symmetrical third commutation paths and fourth commutation paths in the module, so that the equivalent inductance of the entire commutation loop is the parallel connection of the inductance of the two commutation paths, thereby reducing the commutation loop inductance in the entire module and improving the electrical reliability.

[0035] As shown by the thick dashed line in FIG. 1, the second commutation loop includes a third commutation path from the first negative terminal connection area 1231 to the neutral terminal connection area 1220 and a fourth commutation path from the second negative terminal connection area 1232 to the neutral terminal connection area 1220, and the third commutation path and the fourth commutation path are in parallel connection. Figure 3 As shown by the thick dashed line in FIG. 1, the second commutation loop includes a third commutation path from the first negative terminal connection area 1231 to the neutral terminal connection area 1220 and a fourth commutation path from the second negative terminal connection area 1232 to the neutral terminal connection area 1220, and the third commutation path and the fourth commutation path are in parallel connection.

[0036] In some embodiments, the first chip set, the second chip set, the third chip set and the fourth chip set of the present application are respectively arranged on the substrate 100 symmetrically relative to the center line OO' of the substrate 100.

[0037] Specifically, the first chip set includes at least two first chips T1 connected in parallel with each other, and the at least two first chips T1 are respectively arranged symmetrically on opposite sides of the center line OO' of the substrate 100; the second chip set includes at least two second chips T2 connected in parallel with each other, and the at least two second chips T2 are respectively arranged symmetrically on opposite sides of the center line OO' of the substrate 100; the third chip set includes at least two third chips T3 connected in parallel with each other, and the at least two third chips T3 are respectively arranged symmetrically on opposite sides of the center line OO' of the substrate 100; and the fourth chip set includes at least two fourth chips T4 connected in parallel with each other, and the at least two fourth chips T4 are respectively arranged symmetrically on opposite sides of the center line OO' of the substrate 100.

[0038] As shown by the thick dashed line in FIG. 1, the second commutation loop includes a third commutation path from the first negative terminal connection area 1231 to the neutral terminal connection area 1220 and a fourth commutation path from the second negative terminal connection area 1232 to the neutral terminal connection area 1220, and the third commutation path and the fourth commutation path are in parallel connection. Figure 3As shown by the thick solid line on the left, the first commutation path includes a first positive terminal connection area 1211, passing sequentially through the first chip T1, the third chip T3, and the second chip T2 located on one side of the center line OO′ of the substrate 100, to the neutral terminal connection area 1220; as shown by the thick solid line on the left, the first commutation path includes a first positive terminal connection area 1211, passing sequentially through the first chip T1, the third chip T3, and the second chip T2 located on one side of the center line OO′ of the substrate 100, to the neutral terminal connection area 1220; Figure 3 As shown by the thick solid line on the right, the second commutation path includes a first chip T1, a third chip T3, and a second chip T2 located on the other side of the center line OO′ of the substrate 100, from the second positive terminal connection area 1212 through the first chip T1, the third chip T3, and the second chip T2 located on the other side of the center line OO′ of the substrate 100 to the neutral terminal connection area 1220.

[0039] like Figure 3 As shown by the thick dashed line on the left, the third commutation path includes a path from the first negative terminal connection area 1231, sequentially passing through the fourth chip T4, the third chip T3, and the second chip T2 located on one side of the center line OO′ of the substrate 100, to the neutral terminal connection area 1220; as shown by the thick dashed line on the left, the third commutation path includes a path from the first negative terminal connection area 1231, passing through the fourth chip T4, the third chip T3, and the second chip T2 located on one side of the center line OO′ of the substrate 100, to the neutral terminal connection area 1220; Figure 3 As shown by the thick dashed line on the right, the fourth commutation path includes the fourth chip T4, the third chip T3 and the second chip T2 located on the other side of the center line OO′ of the substrate 100, from the second negative terminal connection area 1232 through the fourth chip T4, the third chip T3 and the second chip T2 located on the other side of the center line OO′ of the substrate 100 to the neutral terminal connection area 1220.

[0040] The power module 1 of this application forms a symmetrical first commutation path and a symmetrical second commutation path, as well as a symmetrical third commutation path and a symmetrical fourth commutation path, by symmetrically arranging the first chipset, the second chipset, the third chipset and the fourth chipset on the substrate 100 with respect to the center line OO′.

[0041] Continue to refer to Figure 4 As shown, in some embodiments, the fourth chip group, the first chip group, the second chip group and the third chip group are arranged in parallel along the first direction D1 of the substrate 100, and the multiple chips contained in each of the first chip group, the second chip group, the third chip group and the fourth chip group are arranged in parallel along the second direction D2 of the substrate 100, with the first direction D1 and the second direction D2 being perpendicular.

[0042] In some embodiments, the neutral terminal connection area 1220 is symmetrically arranged with respect to the center line OO′ of the substrate 100, the first positive terminal connection area 1211 and the second positive terminal connection area 1212 are symmetrically arranged on opposite sides of the neutral terminal connection area 1220, and the first negative terminal connection area 1231 and the second negative terminal connection area 1232 are symmetrically arranged on opposite sides of the neutral terminal connection area 1220 and are located outside the first positive terminal connection area 1211 and the second positive terminal connection area 1212, respectively.

[0043] The substrate 100 further comprises an alternating-current terminal connection area 1240. The substrate 100 has a first end and a second end opposite to each other along the first direction D1. In some embodiments, the first positive terminal connection area 1211, the second positive terminal connection area 1212, the neutral terminal connection area 1220, the first negative terminal connection area 1231 and the second negative terminal connection area 1232 are located at the first end of the substrate 100, and the alternating-current terminal connection area 1240 is located at the second end of the substrate 100.

[0044] In some embodiments, the substrate 100 of the present application comprises a first conductive area 101, a second conductive area 102, a third conductive area 103, a fourth conductive area 104, a fifth conductive area 105 and a sixth conductive area 106 which are spaced apart from each other.

[0045] The neutral terminal connection area 1220 and the second chip group are located at the first conductive area 101, and the drain of each second chip T2 in the second chip group is electrically connected to the first conductive area 101; the first positive terminal connection area 1211, the second positive terminal connection area 1212 and the first chip group are located at the second conductive area 102, and the drain of each first chip T1 in the first chip group is electrically connected to the second conductive area 102; the first negative terminal connection area 1231 is located at the third conductive area 103; the second negative terminal connection area 1232 is located at the fourth conductive area 104; the fourth chip group and the alternating-current terminal connection area 1240 are located at the fifth conductive area 105, and the drain of each fourth chip T4 in the fourth chip group is electrically connected to the fifth conductive area 105; the third chip group is located at the sixth conductive area 106, and the drain of each third chip T3 in the third chip group is electrically connected to the sixth conductive area 106.

[0046] In some embodiments, the substrate 100 of the present application further comprises a seventh conductive area 107, an eighth conductive area 108, a ninth conductive area 109, a tenth conductive area 110, an eleventh conductive area 111, a twelfth conductive area 112 and a thirteenth conductive area 113.

[0047] The seventh conductive area 107 and the eighth conductive area 108 are arranged in parallel along the first direction D1 and extend in a strip shape along the second direction D2, and are respectively used as a driving source electrode loop and a driving gate electrode loop of the fourth chip group.

[0048] The ninth conductive area 109 and the tenth conductive area 110 are arranged in parallel along the first direction D1 and extend in a strip shape along the second direction D2, and are respectively used as a driving source electrode loop and a driving gate electrode loop of the first chip group.

[0049] The eleventh conductive region 111, the twelfth conductive region 112 and the thirteenth conductive region 113 are arranged in parallel along the first direction D1 and extend in a strip shape along the second direction D2. The twelfth conductive region 112 serves as a common source driving circuit of the second chip set and the third chip set, and the eleventh conductive region 111 and the thirteenth conductive region 113 respectively serve as a driving gate circuit of the third chip set and the second chip set.

[0050] In some embodiments, the power module 1 of the present application further comprises a first bonding wire group 131, a second bonding wire group 132 and a third bonding wire group 133.

[0051] The first bonding wire group 131 is respectively electrically connected with the third conductive region 103, the source of each fourth chip T4 in the fourth chip set and the fourth conductive region 104 along the second direction D2.

[0052] The second bonding wire group 132 is respectively electrically connected with the fifth conductive region 105, the source of each first chip T1 in the first chip set and the sixth conductive region 106 along the first direction D1.

[0053] The third bonding wire group 133 is respectively electrically connected with the source of the third chip set and the source of each second chip T2 in the second chip set along the first direction D1. The second bonding wire group 132 and the third bonding wire group 133 are perpendicular to the first bonding wire group 131.

[0054] Figure 5 A disassembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N of an embodiment of the present application is shown, Figure 4 A disassembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N of an embodiment of the present application is shown, Figure 6 An assembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N is shown, Figure 5 An assembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N is shown, Figure 4 to Figure 6 A side view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N is shown.

[0055] As Figure 5 As shown, in some embodiments, the positive power terminal DC+ has a positive planar body part 211 and a pair of positive connecting parts 212 extending from the positive planar body part 211. The pair of positive connecting parts 212 are respectively electrically connected to the first positive terminal connecting area 1211 and the second positive terminal connecting area 1212.

[0056] The neutral power terminal N has a neutral planar body part 221 and a neutral connecting part 222 extending from the neutral planar body part 221, and the neutral connecting part 222 is electrically connected to the neutral terminal connecting area 1220.

[0057] The negative power terminal DC- has a negative planar main body part 231 and a pair of negative connecting parts 232 extending from the negative planar main body part 231. The pair of negative connecting parts 232 are respectively electrically connected to the first negative terminal connecting area 1231 and the second negative terminal connecting area 1232.

[0058] As shown in FIG. 1, the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a space position manner, and the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a staggered manner. Figure 5 And 6 As shown in FIG. 1, the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a space position manner, and the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a staggered manner. Figure 7 As shown in FIG. 1, the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a space position manner, and the positive planar main body part 211, the neutral planar main body part 221 and the negative planar main body part 231 are arranged in a staggered manner.

[0059] The power module 1 of the present application can reduce the stray inductance of the power terminals as much as possible based on the magnetic field cancellation effect by arranging the neutral power terminal N between the positive power terminal DC+ and the negative power terminal DC-, and arranging the neutral power terminal N in a laminated structure with the positive power terminal DC+ and the negative power terminal DC-.

[0060] In some embodiments, the positive power terminal DC+ further has a second positive connecting part 213 extending from the positive planar main body part 211, and the second positive connecting part 213 is used for external connection. The positive connecting part 212 and the second positive connecting part 213 are respectively located on opposite sides of the positive planar main body part 211.

[0061] The neutral power terminal N further has a second neutral connecting part 223 extending from the neutral planar main body part 221, and the second neutral connecting part 223 is used for external connection. The neutral connecting part 222 and the second neutral connecting part 223 are respectively located on opposite sides of the neutral planar main body part 221.

[0062] The negative power terminal DC- further has a second negative connecting part 233 extending from the negative planar main body part 231, and the second negative connecting part 233 is used for external connection. The negative connecting part 232 and the second negative connecting part 233 are respectively located on opposite sides of the negative planar main body part 231.

[0063] Figure 8 FIG. 2 shows an exploded schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N of another embodiment of the present application, Figure 7 FIG. 3 shows a schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N of another embodiment of the present application, Figure 9Assembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N shown, Figure 8 Disclosed are Figure 7 to Figure 9 Assembled schematic view of the positive power terminal DC+, the negative power terminal DC- and the neutral power terminal N shown.

[0064] As ​ As shown in some other embodiments, the positive power terminal DC+ and the negative power terminal DC- of the present application adopt a double-end structure, i.e. the positive power terminal DC+ has a pair of second positive connection portions 213, and the negative power terminal DC- has a pair of second negative connection portions 233. The pair of second negative connection portions 233 is located outside the pair of second positive connection portions 213, and the second neutral connection portion 223 is located between the pair of second positive connection portions 213.

[0065] The positive power terminal DC+ and the negative power terminal DC- of the present application can be connected to the double-positive-terminal connection area and the double-negative-terminal connection area inside the power module 1 by adopting the double-end structure, so as to form two first commutation paths and second commutation paths in the form of annular and left-right symmetry, and two third commutation paths and fourth commutation paths in the form of annular and left-right symmetry inside the module.

[0066] The present application also provides a vehicle. The vehicle comprises the power module 1 as described in each of the above embodiments.

[0067] The vehicle of the present application has generally similar beneficial technical effects as the power module 1 described above, and thus will not be described here again.

[0068] The power module and the vehicle provided by the embodiments of the present application are described in detail above. The power module and the vehicle of the embodiments of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the core idea of the present application, and does not limit the present application. It should be pointed out that, for those skilled in the art, without departing from the spirit and principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications should also fall within the protection scope of the appended claims of the present application.

Claims

1. A power module, characterized by: The substrate is provided with a first positive terminal connection area, a second positive terminal connection area, a neutral terminal connection area, a first negative terminal connection area and a second negative terminal connection area, The power module has a first commutation loop and a second commutation loop, the first commutation loop includes a first commutation path from the first positive terminal connection area to the neutral terminal connection area and a second commutation path from the second positive terminal connection area to the neutral terminal connection area; the second commutation loop includes a third commutation path from the first negative terminal connection area to the neutral terminal connection area and a fourth commutation path from the second negative terminal connection area to the neutral terminal connection area, wherein the first commutation path and the second commutation path are symmetrically arranged relative to the center line of the substrate, and the third commutation path and the fourth commutation path are symmetrically arranged relative to the center line of the substrate.

2. The power module of claim 1, wherein: The power module includes a first chip set, a second chip set, a third chip set and a fourth chip set, which are symmetrically arranged on the substrate relative to the center line of the substrate.

3. The power module of claim 2, wherein: The fourth chip set, the first chip set, the second chip set and the third chip set are arranged in parallel along a first direction of the substrate, and the plurality of chips included in each of the first chip set, the second chip set, the third chip set and the fourth chip set are arranged in sequence along a second direction of the substrate, and the first direction is perpendicular to the second direction.

4. The power module of claim 3, wherein: The neutral terminal connection area is symmetrically arranged relative to the center line of the substrate, the first positive terminal connection area and the second positive terminal connection area are symmetrically arranged on opposite sides of the neutral terminal connection area, and the first negative terminal connection area and the second negative terminal connection area are symmetrically arranged on opposite sides of the neutral terminal connection area and are located outside the first positive terminal connection area and the second positive terminal connection area.

5. The power module of claim 4, wherein: The substrate is further provided with an alternating current terminal connection area, and the substrate has a first end and a second end opposite to each other along the first direction, the first positive terminal connection area, the second positive terminal connection area, the neutral terminal connection area, the first negative terminal connection area and the second negative terminal connection area are located at the first end of the substrate, and the alternating current terminal connection area is located at the second end of the substrate.

6. The power module of claim 5, wherein: The substrate includes first, second, third, fourth, fifth and sixth conductive regions spaced from each other, The neutral terminal connection area and the second chip set are located in the first conductive region; the first positive terminal connection area, the second positive terminal connection area and the first chip set are located in the second conductive region; the first negative terminal connection area is located in the third conductive region; the second negative terminal connection area is located in the fourth conductive region; the fourth chip set and the alternating current terminal connection area are located in the fifth conductive region; and the third chip set is located in the sixth conductive region.

7. The power module of claim 6, wherein: The substrate further comprises a seventh conductive region, an eighth conductive region, a ninth conductive region, a tenth conductive region, an eleventh conductive region, a twelfth conductive region and a thirteenth conductive region, wherein, The seventh conductive region and the eighth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, and serve as a driving source electrode loop and a driving gate electrode loop of the fourth chip group, respectively; The ninth conductive region and the tenth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, and serve as a driving source electrode loop and a driving gate electrode loop of the first chip group, respectively; The eleventh conductive region, the twelfth conductive region and the thirteenth conductive region are arranged in parallel along the first direction and extend in a strip shape along the second direction, the twelfth conductive region serves as a common source electrode driving loop of the second chip group and the third chip group, and the eleventh conductive region and the thirteenth conductive region serve as a driving gate electrode loop of the third chip group and the second chip group, respectively.

8. The power module of claim 7, wherein: The power module further comprises a first bonding wire group, a second bonding wire group and a third bonding wire group, wherein, The first bonding wire group is electrically connected with the third conductive region, the source electrode of the fourth chip group and the fourth conductive region along the second direction, respectively; The second bonding wire group is electrically connected with the fifth conductive region, the source electrode of the first chip group and the sixth conductive region along the first direction, respectively; The third bonding wire group is electrically connected with the source electrode of the third chip group and the source electrode of the second chip group along the first direction, respectively.

9. The power module of claim 1, wherein: The power module comprises a positive electrode power terminal, a neutral power terminal and a negative electrode power terminal, the positive electrode power terminal has a positive electrode planar main body part and a positive electrode connecting part connected with the positive electrode planar main body part, the positive electrode connecting part is electrically connected with the first positive electrode terminal connecting area and the second positive electrode terminal connecting area; the neutral power terminal has a neutral planar main body part and a neutral connecting part connected with the neutral planar main body part, the neutral connecting part is electrically connected with the neutral terminal connecting area; the negative electrode power terminal has a negative electrode planar main body part and a negative electrode connecting part connected with the negative electrode planar main body part, the negative electrode connecting part is electrically connected with the first negative electrode terminal connecting area and the second negative electrode terminal connecting area, wherein, the positive electrode planar main body part, the neutral planar main body part and the negative electrode planar main body part are arranged in an overlapping and spaced manner, and the neutral planar main body part is located between the positive electrode planar main body part and the negative electrode planar main body part.

10. A vehicle characterized by: The power module as claimed in any one of claims 1 to 9. The power module as claimed in any one of claims 1 to 9.

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