Bidirectional threshold gate tube
By designing a bidirectional threshold selector, employing a Zn-doped HfO2 thin film and an asymmetric electrode structure, the leakage current problem in memristor arrays was solved, enabling memristor applications with high integration and low power consumption, and exhibiting excellent stability and on/off ratio.
Patent Information
- Application Number
- CN202422458922.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-10-11
AI Technical Summary
Existing memristor arrays suffer from leakage current issues in cross-array configurations, leading to misreading and misoperation, which limits the improvement of integration density. Furthermore, existing selectors have low on-state current, high threshold voltage, and poor stability and consistency.
A bidirectional threshold selector is designed, employing an asymmetric electrode structure and using a Zn-doped HfO2 thin film as the functional layer, combined with inert and active metal electrodes, and fabricated by magnetron sputtering to achieve symmetric gating characteristics and high integration of the device.
It improves the performance stability and integration of the gate transistor, has stable characteristics that can be repeated multiple times, and has an on/off ratio greater than 105, making it suitable for high-density integration and low-power applications of memristors.
Smart Images
Figure CN223798622U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a bidirectional threshold selector, belonging to the field of microelectronics technology. Background Technology
[0002] Currently, driven by deep learning (DL) technology, the application of artificial intelligence (AI) in various fields is entering a phase of rapid growth, resulting in a dramatic increase in data volume. In the traditional von Neumann computing architecture, the separation of memory and processing units, along with limitations in communication bandwidth, prevent it from meeting the data computation requirements of emerging technologies such as artificial neural networks, pattern recognition, and in-memory computing. Memristors, due to their unique non-volatile characteristics, can perform storage and computation in a cross-array configuration with lower power consumption and greater integration density. Theoretically, this will significantly reduce power consumption and improve in-memory processing capabilities. However, non-ideal branch currents still exist in this passive structure, leading to problems such as misreading and misoperation, severely limiting the improvement of integration density.
[0003] To suppress the crosstalk leakage current problem in memristor arrays, existing solutions include: 1. Complementary memristors: improving memory performance, reliability, and anti-interference capabilities through complementary operating mechanisms, but significantly increasing process complexity; 2. 1T1R structure: using transistors to select memristor cells, but the cell area is limited by transistor size, restricting storage density; 3. 1D1R structure: using the unidirectional conductivity of diodes to select memristor cells, but the low forward current density of diodes can easily cause memristor cells to malfunction; 4. 1S1R structure: adding a selector transistor to each memristor cell to suppress crosstalk and improve array read / write performance.
[0004] Among these schemes, the 1S1R structure is simple, which not only improves the stability and reliability of the memory array but also retains its passive characteristics, resulting in lower power consumption. This makes it easy to achieve high-density integration of three-dimensional stacking of memristor cross arrays. However, in existing methods, the turn signal transistors fabricated using the 1S1R structure have small on-state currents, large threshold voltages, and poor stability and consistency in practical applications. These factors place higher demands on the fabrication process of the turn signal transistors.
[0005] Therefore, it is necessary to design a bidirectional threshold gate to overcome the bottlenecks in existing technologies. Utility Model Content
[0006] To overcome the above problems, a bidirectional threshold gate is proposed, wherein the gate comprises, from bottom to top, a substrate layer 1, an adhesive layer 2, a bottom electrode 3, a functional layer 4, and a top electrode 5.
[0007] In a preferred embodiment, the adhesive layer is Ti.
[0008] In a preferred embodiment, the bottom electrode is an inert metal electrode, and the top electrode is an active metal electrode.
[0009] In a preferred embodiment, the functional layer is a Zn-doped HfO2 thin film.
[0010] In a preferred embodiment, the mass percentage of Zn is 1% to 5%.
[0011] More preferably, the mass percentage of Zn is 4% to 5%.
[0012] In a preferred embodiment, the bottom electrode is a Pt electrode.
[0013] In a preferred embodiment, the top electrode is an Ag electrode.
[0014] In a preferred embodiment, the thickness of the adhesive layer Ti and the bottom electrode layer Pt is 100–200 nm.
[0015] In a preferred embodiment, the thickness of the Zn-doped HfO2 film is 20–100 nm.
[0016] In a preferred embodiment, the thickness of the top electrode layer is 100–200 nm.
[0017] The beneficial effects of this utility model include:
[0018] (1) The functional layer material of the gate tube of this utility model is Zn-doped HfO2. The introduction of Zn can suppress the randomness of the growth of conductive filaments, thereby improving the performance of the device. The asymmetric electrode structure realizes bidirectional gating characteristics that tend to be symmetrical.
[0019] (2) This utility model provides an integrated fabrication process compatible with the selection tube and the transition metal oxide memristor, which mainly involves microelectronics process. Its advantages of high integration, low power consumption, small size and high manufacturing process precision greatly improve the performance of the chip. The fabrication process of the selection tube is highly compatible with the fabrication process of the transition metal oxide memristor, and the device performance is stable.
[0020] (3) The bidirectional threshold selector of this invention has a stable characteristic that can be repeated multiple times. That is, in the IV characteristic test, the characteristics of a large number of test points tend to be consistent and can all show stable cycle characteristics of more than 100 times and have a value greater than 10. 5 Its switching ratio provides a good performance match with memristors in practical applications.
[0021] Symbol Explanation
[0022] 1-Substrate;
[0023] 2-Adhesive layer;
[0024] 3-Bottom electrode;
[0025] 4-Functional layer;
[0026] 5-Top electrode. Attached Figure Description
[0027] Figure 1 This diagram shows a bidirectional threshold selection tube structure according to a preferred embodiment of the present invention.
[0028] Figure 2 The test results of the selector tube IV characteristics in Example 1 are shown. Detailed Implementation
[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Through these descriptions, the features and advantages of the present invention will become clearer and more apparent.
[0030] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.
[0031] According to the present invention, a bidirectional threshold selector is provided, wherein the selector adopts an asymmetric electrode structure.
[0032] The gate tube, from bottom to top, includes: a substrate layer 1, an adhesion layer 2, a bottom electrode 3, a functional layer 4, and a top electrode 5, as follows: Figure 1 As shown.
[0033] The substrate layer 1 is a Si / SiO2 layer.
[0034] The adhesive layer is Ti. Due to the poor direct adhesion between Pt and Si / SiO2, peeling or uneven growth is prone to occur during Pt film deposition. Ti has good adhesion, which can promote the formation of a uniform and stable Pt film on the Si / SiO2 surface.
[0035] The bottom electrode is an inert metal electrode, preferably a Pt electrode.
[0036] The functional layer is Zn-doped HfO2.
[0037] Furthermore, the introduction of Zn can suppress the randomness of conductive filament growth, thereby improving the performance of the device, and the asymmetric electrode structure achieves bidirectional gating characteristics that tend towards symmetry.
[0038] Preferably, the mass percentage of Zn is 1% to 5%, more preferably 4% to 5%. The introduction of Zn as a dopant reduces the formation energy of oxygen vacancies in HfO2 and increases their mobility. This allows the conductive filaments formed by oxygen vacancies to complete the switching process of the gate under the action of an electric field when the inert electrode is selected. Controlling the mass percentage can adjust the negative threshold voltage to be symmetrical with the positive threshold voltage.
[0039] The top electrode is an active metal electrode, preferably an Ag electrode.
[0040] This utility model also discloses a method for preparing a bidirectional threshold selection transistor, comprising the following steps:
[0041] S1. Fabricate an oxide layer on the substrate surface;
[0042] S2. Prepare an adhesion layer on the oxide layer;
[0043] S3. Prepare a bottom electrode layer on the adhesive layer;
[0044] S4. Photolithographically form a bottom electrode strip on the surface of the bottom electrode;
[0045] S5. Dry etching to obtain the bottom electrode pattern;
[0046] S6. Prepare Zn-doped HfO2 thin films to form functional layers;
[0047] S7. Photolithography is used to form the functional layer pattern on the surface of the functional layer;
[0048] S8. Fabricate a top electrode layer on the functional layer;
[0049] S9. Photolithography is used to form the top electrode pole on the top electrode layer;
[0050] S10. Dry etching to obtain the top electrode pattern.
[0051] Preferably, the following steps are also included:
[0052] S11, Growth of oxide layer: Silicon dioxide is grown on the substrate surface by thermal oxidation.
[0053] S12. Electrode hole patterns are formed on the silicon dioxide surface by photolithography;
[0054] S13. Etch the silicon dioxide layer to form a bonding pad.
[0055] In a preferred embodiment, prior to S1, the wafer is cleaned using RCA.
[0056] In a preferred embodiment, in S1, silicon dioxide is grown on the substrate surface by thermal oxidation, preferably with a thickness of 300-500 nm.
[0057] In a preferred embodiment, the adhesion layer in S2 is prepared by magnetron sputtering, and the adhesion layer is made of Ti material.
[0058] More preferably, in the magnetron sputtering method, when the vacuum level in the chamber decreases to below 6 Pa, the molecular pump is turned on until the pressure in the chamber decreases to 1 × 10⁻⁶ Pa. -3 When the pressure reaches 1 Pa, O2 and Ar are introduced, and sputtering begins when the pressure inside the chamber is adjusted to 1 Pa.
[0059] More preferably, the magnetron sputtering method uses DC sputtering.
[0060] In a preferred embodiment, in S3, the bottom electrode layer is prepared by magnetron sputtering, and the bottom electrode layer is made of Pt material.
[0061] More preferably, in the magnetron sputtering method, when the vacuum level in the chamber decreases to below 6 Pa, the molecular pump is turned on until the pressure in the chamber decreases to 1 × 10⁻⁶ Pa. -3 When the pressure reaches 1 Pa, O2 and Ar are introduced, and sputtering begins when the pressure inside the chamber is adjusted to 1 Pa.
[0062] More preferably, the magnetron sputtering method uses radio frequency sputtering.
[0063] More preferably, the thickness of the adhesive layer and the bottom electrode layer is 100–200 nm, for example, 150 nm.
[0064] In a preferred embodiment, in S5, the bottom electrode pattern is a horizontal rectangular bottom electrode strip, which can achieve higher integration density.
[0065] Preferably, cleaning is performed after S5 to remove etching residue.
[0066] Preferably, the thickness of the Zn-doped HfO2 thin film in S6 is 20–100 nm, for example, 40 nm.
[0067] In this invention, the specific method for preparing the functional layer is not limited. Those skilled in the art can choose any one of magnetron sputtering, chemical vapor deposition, atomic layer deposition, or sol-gel method, with magnetron sputtering being the preferred method.
[0068] More preferably, the magnetron sputtering method uses radio frequency sputtering.
[0069] In a preferred embodiment, in S7, the functional layer is a rectangular pattern, with two sides having a length less than or equal to the width of the horizontal electrode strip and the width of the vertical top electrode strip.
[0070] Preferably, the functional layer is formed by dry etching.
[0071] In a preferred embodiment, cleaning is performed after S7 to remove etching residue.
[0072] In a preferred embodiment, in S8, the top electrode layer is prepared by magnetron sputtering, and preferably, the top electrode layer is made of Ag material.
[0073] More preferably, the magnetron sputtering method uses a DC sputtering top electrode Ag.
[0074] In a preferred embodiment, the thickness of the top electrode layer is 100–200 nm, for example, 150 nm.
[0075] In a preferred embodiment, in S10, the top electrode pattern is a vertically rectangular bottom electrode strip, which can achieve higher integration density.
[0076] Preferably, the top electrode pattern is formed by dry etching.
[0077] Preferably, cleaning is performed after S10 to remove etching residue.
[0078] In a preferred embodiment, the thickness of silicon dioxide in S11 is 300–500 nm.
[0079] Example
[0080] The gate tube is prepared by the following steps:
[0081] S1. Fabricate an oxide layer on the substrate surface;
[0082] S2. Prepare an adhesion layer on the oxide layer;
[0083] S3. Prepare a bottom electrode layer on the adhesive layer;
[0084] S4. Photolithographically form a bottom electrode strip on the surface of the bottom electrode;
[0085] S5. Dry etching to obtain the bottom electrode pattern;
[0086] S6. Prepare Zn-doped HfO2 thin films to form functional layers;
[0087] S7. Photolithography is used to form the functional layer pattern on the surface of the functional layer;
[0088] S8. Fabricate a top electrode layer on the functional layer;
[0089] S9. Photolithography is used to form the top electrode pole on the top electrode layer;
[0090] S10. Dry etching to obtain the top electrode pattern.
[0091] In S1, silicon dioxide is grown on the substrate surface by thermal oxidation, with a thickness of 400 nm.
[0092] In S2, the adhesion layer is prepared by magnetron sputtering. The adhesion layer is made of Ti material and DC sputtering is used in the magnetron sputtering process. The thickness of the adhesion layer is 10-30 nm.
[0093] In S3, the bottom electrode layer is prepared by magnetron sputtering. The bottom electrode layer is made of Pt material and the magnetron sputtering is carried out by radio frequency sputtering. The thickness of the bottom electrode layer is 120-150 nm.
[0094] The Zn-doped HfO2 thin film described in S6 has a thickness of 40 nm and is prepared by magnetron sputtering via radio frequency sputtering.
[0095] In S8, the top electrode layer is prepared by magnetron sputtering. Preferably, the top electrode layer is made of Ag material and is prepared by DC sputtering. The thickness of the top electrode layer is 150 nm.
[0096] The silicon dioxide thickness in S11 is 400 nm.
[0097] The final selected tube has an asymmetric electrode structure of Si / SiO2 / Ti / Pt / HfO2:Zn / Ag, consisting of a substrate, an adhesive layer, a bottom electrode, a functional layer, and a top electrode, from bottom to top.
[0098] The gate transistor underwent IV characteristic testing on a test bench constructed using a semiconductor parameter analyzer (Keithley 4200-SCS, Tektronix, Solon, Ohio, USA) and a manual probe station (PW-400, Advanced, Shanghai, China). First, two probes were used to contact the top and bottom electrodes respectively. Then, the forward scan voltage was set to 0–2V, the negative scan voltage to 0–-2V, and the forward scan limiting current was set to 1 x 10. -3 A, The limiting current for negative scanning is set to 1 x 10. -3 A, the step size for each scan is 0.01Vs.
[0099] Test results are as follows Figure 2 As shown in the figure, red indicates positive bias activation, and blue indicates negative bias activation. It can be seen from the figure that the absolute values of the positive and negative threshold voltages of the selector are both distributed within the range of 0.2V to 0.5V, and the on / off ratio is >10. 5 A large number of test points exhibited consistent characteristics and all demonstrated stable cycling performance exceeding 100 cycles with a value greater than 10. 5 The on / off ratio indicates that the selector has stable characteristics that can be repeated multiple times.
[0100] The present invention has been described above with reference to preferred embodiments; however, these embodiments are merely exemplary and serve only an illustrative purpose. Based on this, various substitutions and improvements can be made to the present invention, all of which fall within the protection scope of the present invention.
Claims
1. A bidirectional threshold selector, characterized in that, The gate tube, from bottom to top, includes: a substrate layer, an adhesive layer, a bottom electrode, a functional layer, and a top electrode. The bottom electrode is a Pt electrode, and the top electrode is an Ag electrode, forming an asymmetric electrode structure. The adhesive layer is Ti. The functional layer is a Zn-doped HfO2 thin film.
2. The bidirectional threshold gate transistor according to claim 1, characterized in that, The thickness of the adhesive layer Ti and the bottom electrode layer Pt is 100–200 nm.
3. The bidirectional threshold gate transistor according to claim 1, characterized in that, The thickness of the Zn-doped HfO2 thin film is 20–100 nm.
4. The bidirectional threshold gate transistor according to claim 1, characterized in that, The thickness of the top electrode layer is 100–200 nm.