Semiconductor device, wafer structure, and electronic apparatus

Abstract

The utility model provides a semiconductor device, a wafer structure and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device includes: a substrate; the first logic circuit is formed on the substrate; the interface circuit is formed on the substrate, is coupled with the first logic circuit and is used for providing an external connection interface of the semiconductor device; and the interconnection circuit is formed on the substrate, is coupled with the first logic circuit and is used for providing an internal expansion interface of the semiconductor device. Through the technical scheme, the development cost can be reduced while various application scenes are coped with.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, wafer structure, and electronic device. Background Technology

[0002] With the explosion of information technology in human society, chips, as carriers of information processing, have been widely used. However, the increasing variety of application scenarios has also posed challenges to chip design. How to cope with the increasingly diverse application scenarios at a lower development cost has become an urgent technical problem to be solved. Utility Model Content

[0003] This application provides a semiconductor device, wafer structure, and electronic device that can reduce development costs while addressing a variety of application scenarios.

[0004] In a first aspect, a semiconductor device is provided, comprising: a substrate; a first logic circuit formed on the substrate; an interface circuit formed on the substrate, the interface circuit being coupled to the first logic circuit for providing an external connection interface for the semiconductor device; and an interconnect circuit formed on the substrate, the interconnect circuit being coupled to the first logic circuit for providing an internal expansion interface for the semiconductor device.

[0005] Through the design of the semiconductor devices described above, interconnect design can be performed before wafer fabrication, based on the computing power or specification requirements of different application scenarios. For example, when the computing power or specification requirements are relatively low, internal expansion of the semiconductor device can be omitted to obtain a chip structure including one logic circuit. Conversely, when the computing power or specification requirements are high, internal expansion of the semiconductor device can be performed to obtain a chip structure including multiple logic circuits. This allows a chip to be reused from architecture design to wafer fabrication, and even its verification process, making it suitable for chip development of various specifications or computing power levels. This allows for meeting the needs of different application scenarios or businesses at a lower chip development cost. For instance, during the engineering change instruction stage after chip development tape-out, the interconnect scheme can be determined, mask design performed, and the design of some metal layers adjusted to obtain a chip structure including one or more logic circuits. When multiple logic circuits are included, interconnect circuits are used to connect the different logic circuits, achieving the effect of producing chips with different computing power or specifications with a single tape-out. This allows a single chip architecture design to simultaneously meet the needs of multiple scenarios. Compared to the traditional approach of developing independent chips for each scenario, the technical solution of this application can reduce the number of architecture designs, and even the number of verification and tape-out processes, thereby saving time, manpower, materials, or design costs in the chip development process, reducing R&D risks, and shortening the development cycle.

[0006] In some implementations of the first aspect, the state of the interconnect circuit includes a connected state or a disconnected state.

[0007] This technical solution allows interconnect circuits to support both connection to and disconnection from other logic circuits. In the disconnected state, the semiconductor device can include one logic circuit to perform the corresponding function, while in the connected state, the semiconductor device can include multiple logic circuits to perform the corresponding function. Interconnect circuits can form semiconductor devices of different specifications in different states, thus enabling applications in different scenarios and meeting the needs of diverse applications.

[0008] In some implementations of the first aspect, the interconnect circuit is asynchronous with the clock of the first logic circuit, which can prevent the interconnect circuit from affecting the logic circuit.

[0009] In some implementations of the first aspect, the semiconductor device includes a plurality of interconnect circuits, including a first interconnect circuit and a second interconnect circuit.

[0010] This technical solution provides multiple interconnect circuits within a semiconductor device, offering more internal expansion interfaces. This allows for more flexible expansion of the number of logic circuits within the device, enabling the architecture design during chip development to be applicable to a wider range of specifications and computing power scenarios. Consequently, a single design can yield a semiconductor device suitable for a broader range of applications. Furthermore, multiple interconnect circuits can be located at different physical locations within the semiconductor device. When interconnect circuits are positioned at the edge, it facilitates internal wiring within the circuit unit, reducing wiring complexity and minimizing signal interference.

[0011] In some implementations of the first aspect, the first interconnect circuit and the second interconnect circuit are in a non-connected state.

[0012] In some implementations of the first aspect, a first interconnect circuit is used to provide in-line extension of the semiconductor device in a first direction; and a second interconnect circuit is used to provide in-line extension of the semiconductor device in a second direction.

[0013] This technical solution allows multiple interconnect circuits in a semiconductor device to provide expansion interfaces in different directions, facilitating the interconnection of logic circuits with other logic circuits in different directions. This enables a more flexible expansion of the number of logic circuits within the semiconductor device, making it suitable for a wider range of applications.

[0014] In some implementations of the first aspect, the first interconnect circuit is in a non-connected state, the second interconnect circuit is in a connected state, and the semiconductor device further includes a second logic circuit. The multiple interconnect circuits also include a third interconnect circuit, which is coupled to the second logic circuit and is in a connected state. The first logic circuit is connected to the second logic circuit through the second interconnect circuit and the third interconnect circuit.

[0015] This technical solution allows a semiconductor device to include multiple logic circuits. The arrangement of multiple logic circuits can improve the specifications or computing power of the semiconductor device, meeting the needs of scenarios with higher requirements for specifications and computing power.

[0016] In some implementations of the first aspect, the multiple interconnect circuits also include a fourth interconnect circuit coupled to the first logic circuit.

[0017] In some implementations of the first aspect, the fourth interconnect circuit is in a disconnected state; or, the fourth interconnect circuit is in a connected state, and the semiconductor device further includes a third logic circuit, and the plurality of interconnect circuits further include a fifth interconnect circuit, the fifth interconnect circuit being coupled to the third logic circuit and in a connected state; the first logic circuit is connected to the third logic circuit through the fourth interconnect circuit and the fifth interconnect circuit.

[0018] This technical solution allows a semiconductor device to include a large number of logic circuits. The arrangement of these multiple logic circuits can further enhance the specifications or computing power of the semiconductor device to meet the needs of scenarios with higher requirements for specifications and computing power.

[0019] In some implementations of the first aspect, the interface circuitry and interconnect circuitry are located at at least one edge of the substrate.

[0020] In this technical solution, the interface circuit and interconnect circuit are placed at the edge of the substrate, which facilitates the wiring connection between the interface circuit and interconnect circuit and the logic circuit, reduces wiring complexity and signal interference, improves the performance of the semiconductor structure and semiconductor device, and enhances the reliability of the semiconductor device.

[0021] In some implementations of the first aspect, the substrate includes a first edge, a second edge, a third edge, and a fourth edge, the third edge being opposite to the first edge, the fourth edge being opposite to the second edge, and an interface circuit being disposed at the first edge, and at least one of the first edge, the second edge, the third edge, and the fourth edge being disposed of an interconnect circuit.

[0022] In a second aspect, a wafer structure is provided, comprising: a wafer substrate; a plurality of semiconductor structures arrayed on the wafer substrate, the semiconductor structures including logic circuits, interface circuits and interconnect circuits, the interface circuits being coupled to the logic circuits and used to provide external connection interfaces for the semiconductor structures; and interconnect circuits being coupled to the logic circuits and used to provide internal expansion interfaces for the semiconductor structures.

[0023] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0024] In some implementations of the second aspect, the plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; the first semiconductor structure includes a first edge, a second edge, a third edge, and a fourth edge, the first edge being opposite to the third edge, the second edge being opposite to the fourth edge, the first edge and the third edge intersecting with the second edge, and also intersecting with the fourth edge; the second semiconductor structure includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge, the fifth edge being opposite to the seventh edge, the sixth edge being opposite to the eighth edge, the fifth edge and the seventh edge intersecting with the sixth edge, and also intersecting with the eighth edge; an interface circuit is formed at the first edge and the fifth edge; the third edge and the seventh edge are adjacent, and an interconnect circuit is formed at the third edge and the seventh edge.

[0025] In some implementations of the second aspect, interconnecting circuits are formed at the second and fourth edges; and / or, interconnecting circuits are formed at the sixth and eighth edges.

[0026] Thirdly, an electronic device is provided, comprising: a semiconductor device as described in the first aspect or any possible implementation of the first aspect. Attached Figure Description

[0027] Figure 1 A schematic diagram of a wafer structure according to an exemplary embodiment of this application is shown.

[0028] Figure 2 A schematic diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0029] Figure 3 A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown.

[0030] Figure 4 A schematic diagram of a semiconductor structure according to an exemplary embodiment of this application is shown.

[0031] Figure 5 A schematic diagram of another semiconductor structure according to an exemplary embodiment of this application is shown.

[0032] Figure 6A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown.

[0033] Figure 7 A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown.

[0034] Figure 8 A schematic diagram of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown.

[0035] Figure 9 A schematic diagram of a chip development process according to an exemplary embodiment of this application is shown.

[0036] Figure 10 A schematic diagram of another chip development process according to an exemplary embodiment of this application is shown.

[0037] Figure 11 A schematic diagram of the partitioning of a wafer structure according to an exemplary embodiment of this application is shown.

[0038] Figure 12 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0039] Figure 13 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0040] Figure 14 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0041] Figure 15 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0042] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0043] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0044] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0045] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0046] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0047] In semiconductor technology, semiconductor manufacturing processes can be used to integrate one or more semiconductor components (such as transistors, resistors, capacitors, or inductors) onto one or more semiconductor wafers or substrates to form semiconductor devices, including integrated circuits (ICs). These semiconductor devices are called chips. Chips are the core of electronic devices and are widely used in various fields such as computers, communications, consumer electronics, automobiles, industry, and medicine.

[0048] Chip specifications and computing power requirements vary significantly across different application scenarios. Traditional chip development involves developing separate chips for different applications, using a complete chip development workflow to adapt to the needs of various scenarios. However, chip development is a complex process involving multiple stages, from requirements confirmation to final mass production. Developing separate chips for different application scenarios leads to high development costs, including higher time, labor, material, and design costs.

[0049] Therefore, embodiments of this application provide a semiconductor device that can solve the problems of high development costs of the aforementioned chips. The following description is in conjunction with the accompanying drawings.

[0050] Figure 1 A schematic diagram of a wafer structure according to an exemplary embodiment of this application is shown. Figure 1 As shown, the wafer structure 100 may include a wafer substrate 110 and a semiconductor structure 120, the semiconductor structure 120 being formed on the wafer substrate 110. Figure 1 As shown, the semiconductor structure 120 includes: a logic circuit 121, an interface circuit 122, and an interconnect circuit 123. The interface circuit 122 is coupled to the logic circuit 121 and provides an external connection interface for the semiconductor structure 120. The interconnect circuit 123 is coupled to the logic circuit 121 and provides an internal expansion interface for the semiconductor structure 120.

[0051] Semiconductor structure 120 can also be called a circuit unit (or logic unit). The logic circuit 121 included in the circuit unit (cell) can implement one or more logic operations by processing signals, which may include digital signals, analog signals, or a combination of digital and analog signals. This application embodiment does not limit the type or number of logic operations of the logic circuit. Different logic circuit designs are possible in different application scenarios, and the logic circuit may include digital circuits, analog circuits, or a hybrid circuit of digital and analog circuits. Furthermore, the logic circuits of different circuit units may be the same or different; this application does not impose any limitations, and different designs are possible in different application scenarios. Interface circuit 122 is used to provide an external connection interface for the circuit unit. After wafer production, the above-mentioned wafer structure 100 can be obtained. By dicing the wafer, a bare die can be obtained. This bare die can be packaged, and interface circuit 122 can connect to the pins of the packaged chip, providing an external connection interface for the chip, allowing the chip to connect with other chips or to a circuit board. Interconnect circuit 123 can provide an internal expansion interface for the circuit unit, so that during the chip development process, before wafer production, the interconnect scheme can be adjusted according to computing power or specification requirements to obtain a chip structure scheme including one or more circuit units. This allows an architecture design scheme to be applied to the development of chips with different specifications or computing power requirements. After wafer production, the wafer can be diced to obtain bare dies that meet the needs of different application scenarios.

[0052] By designing the semiconductor structure described above, interconnect designs can be performed before wafer fabrication, based on the computing power or specification requirements of different application scenarios. For example, when the computing power or specification requirements are low, internal expansion of the semiconductor structure can be omitted, resulting in a chip structure including a single circuit unit. Conversely, when the computing power or specification requirements are high, internal expansion of the semiconductor structure can be performed, resulting in a chip structure including multiple circuit units. This allows for the reuse of the chip's architecture design, wafer fabrication, and even verification processes, making it suitable for chip development with various specifications or computing power requirements. This enables meeting the needs of different application scenarios or businesses at a lower chip development cost. For instance, the interconnect scheme can be determined, mask design performed, and the design of some metal layers adjusted during the engineering change order (ECO) stage after chip development tape-out, resulting in a chip structure including one or more circuit units. When multiple circuit units are included, interconnect circuits are used to connect the different circuit units, achieving the effect of producing chips with different computing power or specifications with a single tape-out. This allows a single chip architecture design to simultaneously meet the needs of multiple scenarios. Compared to the traditional approach of developing independent chips for each scenario, the technical solution of this application can reduce the number of architecture designs, and even the number of verification and tape-out processes, thereby saving time, manpower, materials, or design costs in the chip development process, reducing R&D risks, and shortening the development cycle.

[0053] The semiconductor structure 120 described above may include one interconnect circuit to achieve interconnect expansion in one direction, or may include multiple interconnect circuits to achieve interconnect expansion in multiple directions. The number of interconnect circuits included in different semiconductor structures 120 may be the same or different, and the directions of expansion may be the same or different. This application also provides a semiconductor device, which can be obtained by dicing the above wafer structure. Optionally, the semiconductor device may include a chip, which may include a packaged or unpackaged chip, such as a bare die or a chip made from a bare die after packaging. The semiconductor device may include one semiconductor structure or multiple semiconductor structures. The following description is in conjunction with the accompanying drawings.

[0054] Figure 2 A schematic diagram of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 As shown, the semiconductor device 200 includes logic circuit 210, interface circuit 220 and n interconnect circuits 230, where n is a positive integer greater than or equal to 1.

[0055] The descriptions of logic circuit 210, interface circuit 220, and interconnection circuit 230 are the same as in the above embodiments.

[0056] This application does not limit the function of the semiconductor device. Different functions can be achieved depending on the application scenario or business requirements. The structure of the semiconductor device provided in this application is also unrelated to its function, but can be related to its computing power or specifications. As an example and not a limitation, it is assumed that a first type of semiconductor device and a second type of semiconductor device can be obtained using the above wafer structure. The first type of semiconductor device is used in consumer electronics products to implement inference functions, and the second type of semiconductor device is used in servers to implement training functions or both inference and training functions. The second semiconductor device has a higher computing power requirement than the first semiconductor device, or its specifications are higher than the first semiconductor device. The second semiconductor device may include more semiconductor structures (or circuit units) than the first semiconductor device. For example, different semiconductor device structural designs can be implemented using the ECO stage. The embodiments of this application do not limit the implementation of the logic circuit. It can be implemented using digital circuits, analog circuits, or a combination of analog and digital circuits. The logic circuit can be implemented using the von Neumann architecture or a memory computing architecture.

[0057] Interface circuits 122 / 220 can provide an external connection interface for semiconductor device 200, thereby enabling coupling between semiconductor device 200 and other semiconductor devices. As an example, interface circuit 220 can connect to other semiconductor devices via package bonding or electrical connectors, wherein electrical connectors include, but are not limited to, circuit board connectors such as printed circuit boards (PCBs). This application does not limit the interface protocol type of interface circuit 220, and it can include serial communication interfaces or parallel communication interfaces, and can include existing data transmission interface types or data transmission interface types that have evolved with technology. For example, the interface type may include, but is not limited to, peripheral component interconnect express (PCIe), universal chiplet interconnect express (UCIe), mobile industry processor interface (MIPI), universal serial bus (USB), general-purpose input / output (GPIO), universal asynchronous receiver / transmitter (UART), inter-integrated circuit (I2C), serial peripheral interface (SPI), or controller area network (CAN), etc.

[0058] In some embodiments, interface circuits 122 / 220 may include a connected state or a disconnected state. Semiconductor device 200 may include one or more circuit units, and each circuit unit may include one or more interface circuits 220; wherein the interface circuits may be entirely disconnected, partially connected, or entirely connected. For example, if semiconductor device 200 includes one circuit unit, the interface circuit of that circuit unit may be in a connected state. If semiconductor device 200 includes multiple circuit units, the interface circuit of one circuit unit may be used for external connections of the semiconductor device, while the interface circuits of other circuit units may be in a disconnected state, thus simplifying the interface design and preventing interference between more interface circuits. Alternatively, the interface circuits of some or all circuit units may be used for external connections of the semiconductor device to provide flexibility in external connections.

[0059] Interconnect circuit 230, also known as an interconnect cell, provides an internal expansion interface for semiconductor device 200, thereby enabling coupling between logic circuits within semiconductor device 200 and facilitating the expansion of the number of logic circuits within semiconductor device 200. This application does not limit the structure of interconnect circuits 123 / 230; they can have the same or different structures in different application or business scenarios, as long as the structure does not affect the functional implementation of the logic circuits and provides coupling capabilities between different logic circuits. For example, interconnect circuit 123 / 230 may include one or more functions such as buffering, conversion, or control to buffer data transmitted between logic circuits, convert signals transmitted between logic circuits, or control the collaborative operation between logic circuits, thereby achieving efficient collaborative operation between different logic circuits. As an example, interconnect circuit 123 / 230 may include one or more semiconductor elements such as transistors, resistors, capacitors, or inductors.

[0060] In some implementations, interconnect circuits 123 / 230 may be connected to a metal interconnect layer, which can provide an interface for interconnection with the metal interconnect layer, which can be fabricated through mask design.

[0061] In some implementations, the clocks of interconnect circuits 123 / 230 and logic circuits 121 / 210 are asynchronous; that is, within the same semiconductor device or semiconductor structure, the logic circuits and interconnect circuits use different clock signals. For example, the logic circuits and interconnect circuits may include sequential logic circuits that use different clock signals to prevent the interconnect circuits from affecting the logic circuits.

[0062] In some implementations, interconnect circuits 123 / 230 may include a connected state or a disconnected state. When interconnect circuits 123 / 230 are used to couple with other logic circuits, they may be in a connected state; when interconnect circuits 123 / 230 are not used to couple with other logic circuits, they may be in a disconnected state.

[0063] Semiconductor device 200 may include one or more circuit units, and each circuit unit may include one or more interconnect circuits 230; wherein the interconnect circuits may be all in a disconnected state, partially in a connected state, or all in a connected state. For example, semiconductor device 200 may include a single circuit unit, and regardless of the number of interconnect circuits included in that circuit unit, all interconnect circuits within that circuit unit may be in a disconnected state. Alternatively, semiconductor device 200 may include multiple circuit units, wherein each circuit unit includes at least one interconnect circuit in a connected state. Optionally, a circuit unit may also include at least one interconnect circuit in a disconnected state.

[0064] When an interconnect circuit is in a connected state, it can achieve one or more of the above-mentioned coupling capabilities when the semiconductor device is powered on, and the semiconductor elements in the circuit can be turned on. When an interconnect circuit is in a disconnected state, its above-mentioned coupling capabilities are turned off when the semiconductor device is powered on, thus not affecting the operation of other circuits. For example, some semiconductor elements of the interconnect circuit are connected to specific pins through a metal layer design. When the semiconductor device is powered on, these pins are coupled to a target voltage or current or ground, so that the semiconductor elements therein are in a turned-off state.

[0065] Multiple interconnect circuits within a circuit unit can provide more internal expansion interfaces for semiconductor devices, which is conducive to more flexible expansion of the number of logic circuits within the semiconductor device. This makes it easier for the architecture design in the chip development process to be applicable to more specifications or computing power scenarios, and enables the semiconductor device that can be obtained from a single design to be suitable for more application scenarios.

[0066] For ease of understanding, Figure 3 Let's take an example to describe it. Figure 3 A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown. In this semiconductor device, two interconnect circuits are shown in one circuit unit; however, this application is not limited to this and may include more interconnect circuits.

[0067] like Figure 3As shown, the semiconductor device 300 may include: logic circuit 311, logic circuit 312, interface circuit 321, interface circuit 322, and interconnect circuits 331 to 334. Interface circuit 321, interconnect circuit 331, and interconnect circuit 332 are coupled to logic circuit 311. Interface circuit 322, interconnect circuit 333, and interconnect circuit 334 are coupled to logic circuit 312. Interconnect circuits 332 and 333 are in a connected state, and logic circuit 311 is connected to logic circuit 312 through interconnect circuits 332 and 333. Optionally, interconnect circuit 332 may be in a connected state to couple to interconnect circuits of other logic circuits, or interconnect circuit 332 may be in a disconnected state. Interconnect circuit 334 may be in a connected state to couple to interconnect circuits of other logic circuits, or interconnect circuit 334 may be in a disconnected state. One of the interface circuits 321 or 322 can be in a connected state, or both interface circuits 321 and 322 can be in a connected state. When the semiconductor device 300 also includes other circuit units, the interface circuits of the other circuit units can be in a connected state, while both interface circuits 321 and 322 are in a disconnected state.

[0068] In some implementations, multiple interconnect circuits can be located at different physical locations within a semiconductor structure or device. When interconnect circuits are located at the edge, it facilitates the wiring within the circuit unit, reduces wiring complexity, minimizes signal interference, and makes it easier to establish connections between interconnect circuits.

[0069] For example, Figure 4 A schematic diagram of a semiconductor structure according to an exemplary embodiment of this application is shown. A semiconductor device may include this semiconductor structure. Figure 4 As shown, the semiconductor structure 400 may include logic circuit 411, interface circuit 421, interconnect circuit 431, and interconnect circuit 432. Interface circuit 421, interconnect circuit 431, and interconnect circuit 432 are coupled to logic circuit 411. Interconnect circuit 431 provides in-line extension of the semiconductor structure 400 in a first direction, and interconnect circuit 432 provides in-line extension of the semiconductor structure 400 in a second direction, where the first and second directions are different.

[0070] As an example, the semiconductor structure 400 may further include a substrate 401 on which logic circuits 411, interface circuits 421, interconnect circuits 431 and 432 may be formed. The interconnect circuits 431 may be located in a first direction of the logic circuits 411, and the interconnect circuits 432 may be located in a second direction of the logic circuits 411. In some examples, there is an angle between the first and second directions, which may include an acute angle, a right angle, an obtuse angle, or a straight angle. For example, the first and second directions may be perpendicular to each other; or, for instance, the first and second directions may be opposite.

[0071] Through the technical solutions of the embodiments of this application, multiple interconnect circuits in a semiconductor device can provide expansion interfaces in different directions, thereby facilitating the interconnection of logic circuits in the semiconductor device with other logic circuits in different directions. This allows for a more flexible expansion of the number of logic circuits within the semiconductor device, making the semiconductor device suitable for more application scenarios.

[0072] Figure 5 A schematic diagram of another semiconductor structure according to an exemplary embodiment of this application is shown.

[0073] like Figure 5 As shown, the semiconductor structure 500 may include: logic circuit 511, interface circuit 521, and multiple interconnect circuits (e.g., Figure 5 The diagram illustrates interconnect circuits 531, 532, and 533. The interface circuit 521 and multiple interconnect circuits are coupled to the logic circuit 511. The semiconductor structure 500 may further include a substrate 501 on which the logic circuit 511, interface circuit 521, and interconnect circuits may be formed. Optionally, the interface circuit 521 and interconnect circuits may be located at at least one edge of the substrate 501. For example, one interconnect circuit may be disposed on one edge, or more than one interconnect circuit may be disposed on one edge, allowing for greater expansion possibilities in the direction of the edge. The edge where the interface circuit 521 is located may not have interconnect circuits disposed to reduce routing complexity.

[0074] Interconnect circuit 531 is used to provide in-line extension of semiconductor structure 500 in a first direction, interconnect circuit 532 is used to provide in-line extension of semiconductor structure 500 in a second direction, and interconnect circuit 533 is used to provide in-line extension of semiconductor structure 500 in a third direction. The first direction, the second direction, and the third direction are different. For a description of the different directions, please refer to the above description of the difference between the first direction and the second direction.

[0075] As an example, Figure 5The substrate 501 shown may include four edges, wherein the first and third edges are opposite each other, and the second and fourth edges are opposite each other. An interface circuit 521 is disposed at the first edge, and an interconnect circuit is disposed at each of the second, third, and fourth edges. As another example, in addition to the interface circuit 521, an interconnect circuit may be further disposed at the first edge. Optionally, at least one of the first, second, third, and fourth edges may be provided with an interconnect circuit. Separating the interconnect circuit and the interface circuit on different edges helps to reduce the size of the circuit unit.

[0076] Optionally, the interface circuit 521 and the interconnect circuit may be located not only at the edge of the substrate 501, but also in other regions of the substrate 501, also referred to as non-edge regions, for example, the central region. For example, at least one of the interface circuit 521 and the interconnect circuit is located in the central region of the substrate 501, or for example, both the interface circuit 521 and the interconnect circuit are located in the non-edge regions of the substrate 501.

[0077] In this embodiment, placing the interface circuit and interconnect circuit at the edge of the substrate facilitates wiring connections between the interface circuit and interconnect circuit and the logic circuit, reduces wiring complexity and signal interference, improves the performance of the semiconductor structure and semiconductor device, and enhances the reliability of the semiconductor device. Furthermore, placing the interconnect circuit at the edge of the substrate facilitates the establishment of connections between interconnect circuits.

[0078] The number of interconnect circuits in the semiconductor structure shown in the above embodiments is merely an example. In some alternative embodiments, the semiconductor structure may include more or fewer interconnect circuits, and this application does not specifically limit the number. Furthermore, in the above embodiments, only one interface circuit is illustrated. In some alternative embodiments, the semiconductor structure may include two or more interface circuits, and this application does not specifically limit the number.

[0079] Furthermore, the embodiments of this application do not limit the number of semiconductor structures (circuit units) included in the semiconductor device. A semiconductor device may include one semiconductor structure, or a semiconductor device may include multiple semiconductor structures. For example, Figure 6 A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown.

[0080] like Figure 6As shown, the semiconductor device 600 may include: logic circuit 611, logic circuit 612, interface circuit 621, interconnect circuit 631, and interconnect circuit 632. Logic circuit 611 is coupled to interface circuit 621 and interconnect circuit 631, and logic circuit 612 is coupled to interconnect circuit 632. For ease of distinction, logic circuit 611 and logic circuit 612 may be referred to as the first logic circuit and the second logic circuit, and interconnect circuit 631 and interconnect circuit 632 may be referred to as the first interconnect circuit and the second interconnect circuit.

[0081] In the semiconductor device 600, interconnect circuits 631 and 632 can be connected to each other, and logic circuit 611 can be connected to logic circuit 612 through these two interconnect circuits. Through this embodiment, the semiconductor device 600 can include multiple logic circuits. The arrangement of multiple logic circuits can improve the specifications or computing power of the semiconductor device 600, meeting the needs of scenarios with higher specifications and computing power requirements.

[0082] Optionally, see Figure 6 As shown, in circuit unit 601 containing logic circuit 611, in addition to interconnect circuit 631, other interconnect circuits may be included, such as interconnect circuits 633 and 634 shown in the figure. The other interconnect circuits in circuit unit 601, except for interconnect circuit 631, can be in a non-connected state. Furthermore, in circuit unit 602 containing logic circuit 612, in addition to interconnect circuit 632, other interconnect circuits may be included, such as interconnect circuits 635 and 636 shown in the figure. The other interconnect circuits in circuit unit 602, except for interconnect circuit 632, can be in a non-connected state.

[0083] Optionally, see Figure 6 As shown, the semiconductor device 600 may further include an interface circuit 622 coupled to the logic circuit 612. At least one of the interface circuits 622 and 621 can be used to enable external connections of the semiconductor device 600. In some embodiments, one of the interface circuits 622 and 621 is used to enable external connections of the semiconductor device 600, while the other is in a non-connected state.

[0084] During the manufacturing process of semiconductor device 600, circuit unit 601 and circuit unit 602 can be arranged adjacently on the wafer to facilitate the interconnection circuit of the two circuit units via interconnect traces. Alternatively, in other alternative embodiments, circuit unit 601 and circuit unit 602 in semiconductor device 600 can be arranged non-adjacently.

[0085] The logic circuits in circuit units 601 and 602 may have the same or different functions or circuit structures. The physical locations of the interface circuits in circuit units 601 and 602 may be the same or different. The circuit structures of the interface circuits in circuit units 601 and 602 may be the same or different. The number and / or physical locations of the interconnect circuits in circuit units 601 and 602 may be the same or different. The structures of the interconnect circuits in circuit units 601 and 602 may be the same or different. This application embodiment does not specifically limit the number and physical locations of the interconnect circuits and interface circuits in the semiconductor device 600.

[0086] Figure 7 A schematic diagram of another semiconductor device according to an exemplary embodiment of this application is shown.

[0087] like Figure 7 As shown, the semiconductor device 700 may include logic circuits 711, 712, and 713. Logic circuit 711 is coupled to interconnect circuits 731 and 732, logic circuit 712 is coupled to interconnect circuit 734, and logic circuit 713 is coupled to interconnect circuit 738. Circuit unit 701 includes logic circuit 711 and interconnect circuits coupled thereto; circuit unit 702 includes logic circuit 712 and interconnect circuits coupled thereto; circuit unit 703 includes logic circuit 713 and interconnect circuits coupled thereto.

[0088] In this embodiment, interconnect circuit 731 coupled to logic circuit 711 and interconnect circuit 734 coupled to logic circuit 712 can be in a connected state. Interconnect circuit 731 and interconnect circuit 734 are interconnected to achieve the connection between logic circuit 711 and logic circuit 712. Additionally, interconnect circuit 732 coupled to logic circuit 711 and interconnect circuit 738 coupled to logic circuit 713 can also be in a connected state. Interconnect circuit 732 and interconnect circuit 738 are interconnected to achieve the connection between logic circuit 711 and logic circuit 713.

[0089] The technical solution of this embodiment can provide flexibility in expanding logic circuits in more than one direction, so that the semiconductor device 700 can include a greater number of logic circuits. The arrangement of logic circuits in more directions can further improve the flexibility of the specifications or computing power of the semiconductor device to meet the needs of scenarios with greater requirements for specifications and computing power.

[0090] Optionally, in circuit unit 701 where logic circuit 711 is located, interconnect circuit 731 is located near the edge of circuit unit 702 where logic circuit 712 is located. Similarly, in circuit unit 702, interconnect circuit 734 is located near the edge of circuit unit 701. Additionally, in circuit unit 701, interconnect circuit 732 is located near the edge of circuit unit 703 where logic circuit 713 is located. In circuit unit 703, interconnect circuit 738 is located near the edge of circuit unit 701.

[0091] Optionally, see [link to relevant documentation] Figure 7 As shown, logic circuit 712 can be further coupled to interconnect circuit 735, and logic circuit 713 can be further coupled to interconnect circuit 737. Through interconnect circuits 735 and 737, it is advantageous to further connect logic circuits 712 and 713 to other logic circuits. For example, logic circuits 712 and 713 can be connected to logic circuit 714, wherein logic circuit 714 is coupled to interconnect circuits 7310 and 7311, which are respectively connected to interconnect circuits 735 and 737. In this embodiment, semiconductor device 700 may include multiple logic circuits, which can be coupled to multiple interconnect circuits, thereby achieving a more flexible extended connection method between logic circuits.

[0092] Optionally, in Figure 7 In the semiconductor device 700 shown, the logic circuits may be further coupled to interface circuits, for example, logic circuits 711 to 714 shown in the figure are coupled to interface circuits 721 to 724 respectively. In some examples, the interface circuits 721 to 724 may be located at at least one edge of the semiconductor device 700, thereby facilitating external connections of the semiconductor device 700.

[0093] Furthermore, in some embodiments, the interconnect circuits coupled to the logic circuits may include, in addition to the interconnect circuits in the connected state described above, interconnect circuits in the non-connected state. For example, in Figure 7 In the example shown, logic circuit 711 is also coupled to interconnect circuit 733, logic circuit 712 is also coupled to interconnect circuit 736, logic circuit 713 is also coupled to interconnect circuit 739, and logic circuit 714 is also coupled to interconnect circuit 7312. Interconnect circuits 733, 736, 739, and 7312 are in a disconnected state. Optionally, these multiple interconnect circuits in a disconnected state may also be located at at least one edge of the semiconductor device 700.

[0094] Optionally, based on Figure 7In the illustrated embodiment, for the multiple interconnect circuits that are in a non-connected state, any one or more of them can also be in a connected state. In this case, the one or more interconnect circuits can be further connected to logic circuits, thereby further expanding the number of logic circuits in the semiconductor device.

[0095] The above text combined Figures 1 to 7 This application describes relevant embodiments of the semiconductor structure and semiconductor device provided. The following is a summary of these embodiments. Figures 8 to 10 This document describes embodiments of the manufacturing method and design flow of the semiconductor device provided in this application. In the following method embodiments, the relevant descriptions of the semiconductor structure and semiconductor device can be found in the above description; for the sake of brevity, they will not be repeated hereafter.

[0096] Figure 8 A schematic diagram of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown.

[0097] like Figure 8 As shown, the semiconductor device manufacturing method 800 may include the following steps.

[0098] S810: Forms a wafer structure.

[0099] S820: Determines the partitioning method of semiconductor devices within the wafer structure. The partitioned semiconductor devices include one or more logic circuits.

[0100] S830: According to the dicing method, the wafer structure is cut to obtain a semiconductor device.

[0101] In the embodiments of this application, the wafer structure can be referred to Figure 1 The wafer structure 100 shown is a related scheme. The wafer structure includes a wafer substrate and multiple semiconductor structures formed on the wafer substrate. The semiconductor structures may include logic circuits, interconnect circuits, and interface circuits.

[0102] Based on the application requirements of the semiconductor device to be manufactured, the number of logic circuits in the semiconductor device can be determined. If the semiconductor device includes multiple logic circuits, the interconnection method between these multiple logic circuits can be further determined. Based on this interconnection method, a connection structure can be further formed on the wafer structure. This connection structure is used to connect the interconnection circuits of the multiple logic circuits. Optionally, the connection structure may include at least one metal interconnect layer formed on the wafer substrate, which can be formed on the wafer substrate by semiconductor manufacturing processes. The metal interconnect layer may include metal structures connecting the interconnection circuits. The metal interconnect layer may also include metal structures with other connection functions.

[0103] Based on the interconnection method between multiple logic circuits in a semiconductor device, the wafer structure partitioning method can be determined, and the wafer structure can be cut and partitioned according to the partitioning method to obtain a semiconductor device, which may include one or more semiconductor structures (circuit units).

[0104] Through the technical solutions of this application, during the manufacturing process of semiconductor devices, interconnect design can be performed before wafer dicing, based on the computing power or specification requirements of different application scenarios. For example, the interconnect scheme can be determined, mask design performed, and the design of some metal layers adjusted during the Engineering Change Order (ECO) stage after chip development tape-out, thereby obtaining a chip structure including one or more circuit units. When multiple circuit units are included, interconnect circuits are used to connect different circuit units, achieving the effect of producing chips with different computing power or specifications with a single tape-out, enabling a single chip architecture design to simultaneously meet the needs of multiple scenarios. Compared to the traditional approach of developing independent chips for each scenario, the technical solutions of this application can reduce the number of architecture designs, and even reduce the number of verification and tape-out processes, thereby saving time, manpower, materials, and design costs in the chip development process, reducing R&D risks, and shortening the development cycle.

[0105] Figure 9 A schematic diagram of a chip development process according to an exemplary embodiment of this application is shown. Figure 9 As shown, in this chip development process, for different application scenarios (such as application scenario 1 and application scenario 2 shown in the figure), a variable-specification chip architecture can be designed during the architecture design phase based on the different application scenario requirements. In subsequent stages, namely chip development, tapeout, ECO, wafer fabrication, and dicing and packaging, different chips can be developed and designed for different application scenarios. In this embodiment, different chip versions can be derived from one chip architecture, designed and manufactured separately, and used for different product lines. This approach saves chip design manpower and simplifies software development and maintenance.

[0106] Figure 10 A schematic diagram of another chip development process according to an exemplary embodiment of this application is shown. Figure 10As shown, in this chip development process, the chip's functions are first determined based on the needs of different application scenarios. During the architecture design phase, the chip architecture is designed according to its functions, including the structural design of logic circuits, interconnect circuits, and interface circuits. However, the connection form of the interconnect circuits within the logic circuits is not determined at this stage. Then, chip development is executed, developing and verifying the functions of the logic circuits, interconnect circuits, and interface circuits. In the tapeout stage, the chip's design data is obtained. This design data is used to configure production equipment, set masks, etc., so that the produced chip meets the design requirements. At this stage, the design data includes data for manufacturing masks for layers other than certain metal interconnect layers. Furthermore, different interconnection methods for the logic circuits within the chip can be determined according to the needs of different application scenarios, and implemented by adjusting certain metal interconnect layers during the chip ECO stage. For example, masks for several metal interconnect layers can be manufactured during the ECO stage based on the determined interconnection methods. In the wafer fabrication stage, wafer structures with different interconnection forms can be produced based on the masks for layers other than certain metal interconnect layers determined by the tapeout and the masks for the metal interconnect layers determined by the ECO stage. Then, depending on the interconnection method corresponding to different application scenarios, the wafer structure can be diced and packaged in different ways to produce different types of chips.

[0107] In the above design flow, masks for several metal interconnect layers can be determined and fabricated during the ECO stage. These masks can be flexibly adjusted according to different application scenarios, thereby producing wafer structures and chips with different interconnect forms. This approach can reduce at least one design or verification process from architecture design to tape-out, thus obtaining chip designs applicable to multiple scenarios with reduced chip development costs, adapting to the chip manufacturing needs of different scenarios, and significantly reducing chip manufacturing costs and R&D cycles.

[0108] In other embodiments, design data for the chip can be obtained during the chip tape-out stage. This design data is used to configure production equipment, set masks, etc., so that the manufactured chip meets design requirements. In this stage, the design data includes some or all of the mask data, for example, data for masks that can fabricate several metal interconnect layers. If the application requirements change during or after the chip tape-out stage, the design data can be adjusted during the chip ECO stage. For example, different interconnection methods of the logic circuits within the chip can be modified according to the requirements of the new application scenario, and this can be implemented by adjusting several metal interconnect layers during the chip ECO stage. For example, masks for several metal interconnect layers can be fabricated during the ECO stage according to the modified interconnection method. In this way, only the masks for fabricating several metal interconnect layers need to be modified, reducing the cost caused by changes in requirements.

[0109] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0110] The following is combined Figures 11 to 14 This application describes several ways of dividing the wafer structure and the corresponding semiconductor device structure.

[0111] Figure 11 A schematic diagram of the partitioning of a wafer structure according to an exemplary embodiment of this application is shown.

[0112] like Figure 11 As shown, the wafer structure 1100 may include a wafer substrate 1110, a semiconductor structure 1120, and a semiconductor structure 1130. The semiconductor structure 1120 includes a first edge, a second edge, a third edge, and a fourth edge. The first edge and the third edge are opposite each other, the second edge and the fourth edge are opposite each other, and the first edge and the third edge intersect with the second edge and the fourth edge. The semiconductor structure 1130 includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge. The fifth edge and the seventh edge are opposite each other, the sixth edge and the eighth edge are opposite each other, and the fifth edge and the seventh edge intersect with the sixth edge and the eighth edge. Optionally, as... Figure 11 As shown, semiconductor structure 1120 and semiconductor structure 1130 are, but are not limited to, rectangular structures, and can also be square structures, parallelogram structures or other polygonal structures.

[0113] Optionally, interconnect circuits can be formed between two adjacent edges of semiconductor structure 1120 and semiconductor structure 1130. As an example, the third edge in semiconductor structure 1120 is adjacent to the seventh edge in semiconductor structure 1130, and interconnect circuits can be provided between the third and seventh edges. In some examples, the third and seventh edges can be adjacent in a direction perpendicular to the third and / or seventh edges in semiconductor structure 1120.

[0114] Optionally, interface circuits can be formed on two mutually distant edges of semiconductor structure 1120 and semiconductor structure 1130. As an example, the first edge of semiconductor structure 1120 opposite to the third edge and the fifth edge of semiconductor structure 1130 opposite to the seventh edge are mutually distant, and interface circuits can be provided on the first edge and the fifth edge.

[0115] In some embodiments, in addition to providing interface circuits and interconnect circuits at the opposing third and first edges, the semiconductor structure 1120 may further provide circuits at the opposing second and fourth edges; for example, interconnect circuits may be provided at both the second and fourth edges. In addition to providing interface circuits and interconnect circuits at the opposing seventh and fifth edges, the semiconductor structure 1130 may further provide interconnect circuits at the opposing sixth and eighth edges.

[0116] The technical solution of this embodiment can set interface circuits or interconnect circuits at multiple edges of the semiconductor structure to realize the expansion of the semiconductor structure in multiple directions, thereby enabling more flexible realization of wafer structures and semiconductor devices with various interconnection methods.

[0117] Optionally, semiconductor structures 1120 and 1130 may have one or more circuits disposed on the same edge. For example, semiconductor structure 1120 may have both interface circuits and interconnect circuits disposed on the first edge. Alternatively, semiconductor structure 1120 may have multiple interconnect circuits disposed on the third edge.

[0118] In some embodiments, the semiconductor structures 1120 and 1130 may be arranged in a mirror image. Based on this embodiment, it is convenient to manufacture the semiconductor structures 1120 and 1130 on the wafer substrate, and it is also convenient to arrange the same type of circuits in the semiconductor structures 1120 and 1130 adjacently, such as interconnect circuits, thereby facilitating the wiring design between the interconnect circuits of the two semiconductor structures.

[0119] In some examples, such as Figure 11 As shown, multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can be arranged in an array on the wafer substrate 1110. Optionally, the multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can be spaced apart in the row direction, and the multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can also be arranged in the column direction. Alternatively, the multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can be spaced apart in the column direction, and the multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can also be arranged in the row direction. Optionally, the multiple semiconductor structures 1120 and multiple semiconductor structures 1130 can be spaced apart in both the row and column directions.

[0120] exist Figure 11In the example shown, multiple semiconductor structures in the wafer structure 1100 can be cut and divided to obtain a semiconductor device 1121 including a semiconductor structure 1120, and a semiconductor device 1131 including a semiconductor structure 1130. In the semiconductor devices 1121 and 1131, the interface circuit can be in a connected state, while the interconnect circuit can be in a disconnected state. Figure 11 In the semiconductor devices 1121 and 1131 shown, the positions and quantities of interface circuits and interconnect circuits are for illustrative purposes only. The circuit structures in these two semiconductor devices can be found in any of the embodiments described above, and will not be elaborated upon here.

[0121] Figure 12 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0122] like Figure 12 As shown, the wafer structure 1200 may include a wafer substrate 1210, a semiconductor structure 1220, and a semiconductor structure 1230. (Above) Figure 11 The description of the wafer structure 1100 shown can be applied to the wafer structure 1200 in the embodiments of this application.

[0123] In this embodiment of the application, semiconductor devices 1221 and 1231 are formed by dicing and dividing a wafer structure 1200. Semiconductor device 1221 may include a plurality of adjacent semiconductor structures 1220, and semiconductor device 1231 may include a plurality of adjacent semiconductor structures 1230. As an example, Figure 12 The semiconductor device 1221 shown may include two semiconductor structures 1220, and the semiconductor device 1231 may include two semiconductor structures 1230. In other examples, semiconductor devices 1221 and 1231 may also include three or more semiconductor structures.

[0124] Within a semiconductor device, logic circuits of multiple semiconductor structures can be interconnected via interconnect circuits. A semiconductor structure may include one or more interconnect circuits; where a semiconductor structure includes multiple interconnect circuits, one interconnect circuit may be connected while the others may be disconnected. Additionally, a semiconductor structure may also include one or more interface circuits; one interface circuit within the semiconductor device may be connected while the others may be disconnected.

[0125] Figure 13 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0126] like Figure 13As shown, the wafer structure 1300 may include a wafer substrate 1310, a semiconductor structure 1320, and a semiconductor structure 1330. (Above) Figure 11 The description of the wafer structure 1100 shown can be applied to the wafer structure 1300 in the embodiments of this application.

[0127] In this embodiment, a semiconductor device 1301 can be formed by dicing and dividing the wafer structure 1300. The semiconductor device 1301 may include adjacent semiconductor structures 1320 and 1330. Within the semiconductor device 1301, logic circuits in semiconductor structures 1320 and 1330 can be interconnected via interconnect circuits. Optionally, semiconductor structure 1320 may include one or more interconnect circuits, and semiconductor structure 1330 may include one or more interconnect circuits. In the semiconductor structure, one interconnect circuit may be in a connected state, while other interconnect circuits may be in a disconnected state. Additionally, the semiconductor structure may also include one or more interface circuits, where one interface circuit within the semiconductor device may be in a connected state, while other interface circuits may be in a disconnected state.

[0128] for Figure 12 and Figure 13 The semiconductor device shown may include two or more semiconductor structures, compared to Figure 11 The semiconductor device shown can achieve an increase in computing power or specifications, such as doubling the computing power or specifications.

[0129] Figure 14 A schematic diagram of another wafer structure partitioning according to an exemplary embodiment of this application is shown.

[0130] like Figure 14 As shown, the wafer structure 1400 may include a wafer substrate 1410, a semiconductor structure 1420, and a semiconductor structure 1430. (Above) Figure 11 The description of the wafer structure 1100 shown can be applied to the wafer structure 1400 in the embodiments of this application.

[0131] In this embodiment of the application, a semiconductor device 1401 can be formed by cutting and dividing the wafer structure 1400. The semiconductor device 1401 may include a plurality of adjacent semiconductor structures 1420 and a plurality of semiconductor structures 1430. As an example, Figure 14 The semiconductor device 1401 shown may include two semiconductor structures 1420 and two semiconductor structures 1430. In other examples, the semiconductor device 1401 may also include more or fewer semiconductor structures 1420 and more or fewer semiconductor structures 1430.

[0132] In other embodiments, the expansion can also be carried out in a direction perpendicular to the substrate or base within the wafer structure or semiconductor device. For example, an interconnect circuit layer can be provided in this direction, and one or more interconnect circuits can be provided in the interconnect circuit layer within the semiconductor structure for inward expansion of the semiconductor device in the vertical direction, i.e., expansion of the logic circuit within the semiconductor device.

[0133] The location of interconnect circuits within the semiconductor structure can also be configured in other ways, for example, it may include interconnect circuits located in the central region, and optionally, it may also include interconnect circuits located at the edges. Interconnect circuits located in the central region can enable the expansion of logic circuits in at least one direction. The location of interface circuits within the semiconductor structure can also be configured in other ways, for example, it may include interface circuits located in the central region. For Figure 14 The semiconductor device shown may include four or more semiconductor structures, compared to Figure 12 and Figure 13 The semiconductor device shown can further enhance computing power and specifications.

[0134] This application also provides an electronic device, which can be found in [reference 1]. Figure 15 . Figure 15 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown.

[0135] like Figure 15 As shown, the electronic device 1500 may include a semiconductor device 1510. The semiconductor device 1510 may include the semiconductor device in any of the embodiments described above. In some embodiments, the semiconductor device 1510 may include, for example, a storage device or a memory computing device.

[0136] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0137] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first logic circuit is formed on the substrate; An interface circuit is formed on the substrate and coupled to the first logic circuit to provide an external connection interface for the semiconductor device. Interconnect circuitry, formed on the substrate, coupled to the first logic circuitry, is used to provide an internal expansion interface for the semiconductor device.

2. The semiconductor device according to claim 1, characterized in that, The state of the interconnect circuit includes a connected state or a disconnected state.

3. The semiconductor device according to claim 1, characterized in that, The interconnect circuit is asynchronous with the clock of the first logic circuit.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes a plurality of interconnect circuits, the plurality of interconnect circuits including a first interconnect circuit and a second interconnect circuit.

5. The semiconductor device according to claim 4, characterized in that, The first interconnect circuit and the second interconnect circuit are in a non-connected state.

6. The semiconductor device according to claim 4, characterized in that, The first interconnect circuit is used to provide in-line expansion of the semiconductor device in a first direction; the second interconnect circuit is used to provide in-line expansion of the semiconductor device in a second direction.

7. The semiconductor device according to claim 4, characterized in that, The first interconnect circuit is in a non-connected state, the second interconnect circuit is in a connected state, and the semiconductor device further includes a second logic circuit. The plurality of interconnect circuits further include a third interconnect circuit, which is coupled to the second logic circuit and is in a connected state. The first logic circuit is connected to the second logic circuit through the second interconnect circuit and the third interconnect circuit.

8. The semiconductor device according to claim 7, characterized in that, The plurality of interconnect circuits further includes a fourth interconnect circuit coupled to the first logic circuit.

9. The semiconductor device according to claim 8, characterized in that, The fourth interconnection circuit is in a non-connected state; or... The fourth interconnect circuit is in a connected state, and the semiconductor device further includes a third logic circuit. The plurality of interconnect circuits further include a fifth interconnect circuit, which is coupled to the third logic circuit and is in a connected state. The first logic circuit is connected to the third logic circuit through the fourth interconnection circuit and the fifth interconnection circuit.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that, The interface circuit and the interconnect circuit are located at at least one edge of the substrate.

11. The semiconductor device according to claim 10, characterized in that, The substrate includes a first edge, a second edge, a third edge, and a fourth edge. The third edge is opposite to the first edge, and the fourth edge is opposite to the second edge. The interface circuit is disposed at the first edge, and at least one of the first edge, the second edge, the third edge, and the fourth edge is provided with an interconnect circuit.

12. A wafer structure, characterized in that, include: wafer substrate; Multiple semiconductor structures are formed in an array on the wafer substrate. Each semiconductor structure includes logic circuits, interface circuits, and interconnect circuits. The interface circuits are coupled to the logic circuits and are used to provide external connection interfaces for the semiconductor structures. The interconnect circuit, coupled to the logic circuit, is used to provide an internal expansion interface for the semiconductor structure.

13. The wafer structure according to claim 12, characterized in that, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; The first semiconductor structure includes a first edge, a second edge, a third edge, and a fourth edge. The first edge is opposite to the third edge, the second edge is opposite to the fourth edge, and the first edge and the third edge intersect with the second edge and the fourth edge. The second semiconductor structure includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge, wherein the fifth edge is opposite to the seventh edge, the sixth edge is opposite to the eighth edge, the fifth edge and the seventh edge intersect with the sixth edge, and also intersect with the eighth edge; Interface circuits are formed at the first edge and the fifth edge; The third edge and the seventh edge are adjacent to each other, and an interconnecting circuit is formed at the third edge and the seventh edge.

14. The wafer structure according to claim 13, characterized in that, Interconnect circuits are formed at the second edge and the fourth edge; and / or, interconnect circuits are formed at the sixth edge and the eighth edge.

15. An electronic device, characterized in that, include: The semiconductor device as claimed in any one of claims 1 to 11.

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