CAN bus data recording device circuit

Abstract

The utility model discloses a CAN (Controller Area Network) bus data recording device circuit, which comprises a microprocessor circuit, a power supply circuit and a CAN bus circuit, and is characterized in that the microprocessor circuit is connected with the CAN bus circuit; the microprocessor circuit comprises a processor chip U1, a crystal oscillator Y1, a crystal oscillator Y2, a capacitor C10, a capacitor C11, a capacitor C9 and a capacitor C22. The two ends of the crystal oscillator Y1 are connected with the eighth pin and the ninth pin of the processor chip U1 respectively. The utility model belongs to the technical field of CAN bus data recording, and aims at solving the problems that in the prior art, the function of automatically recording communication data is not achieved, inconvenience is brought to analysis and searching of the communication data afterwards, and meanwhile the analysis and diagnosis capacity of remote CAN equipment is weakened. The technical effects are that communication data can be automatically captured and recorded after power-on, continuous tracking can be realized, time recording can be kept, and the analysis and diagnosis capability of remote CAN equipment is greatly improved.

Description

Technical Field

[0001] This application relates to the field of CAN bus data recording technology, and specifically to a CAN bus data recording device circuit. Background Technology

[0002] With the rapid development of technology and the deepening of industrial automation, CAN (Controller Area Network), as an efficient and stable communication method, is widely used for data transmission and information exchange between various devices. As more and more devices adopt CAN networks as their primary communication method, the need for debugging and recording CAN bus data logging circuits is becoming increasingly prominent. Debugging is a crucial step in ensuring the normal operation of the CAN network, helping engineers to promptly identify and resolve potential problems, ensuring the accuracy and stability of data transmission. Data logging, on the other hand, is for the long-term preservation and analysis of communication data in the CAN network, facilitating subsequent optimization and troubleshooting.

[0003] However, most CAN bus data recording circuits currently lack the function of automatically recording communication data, which makes it inconvenient to analyze and search for communication data afterward, and also weakens the analysis and diagnosis capabilities of remote CAN devices. Utility Model Content

[0004] Therefore, this application provides a CAN bus data recording device circuit to solve the problem that the existing circuits do not have the function of automatically recording communication data, which brings inconvenience to the subsequent analysis and retrieval of communication data, and also weakens the analysis and diagnosis capabilities of remote CAN devices.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A CAN bus data recording device circuit includes a microprocessor circuit, a power supply circuit, and a CAN bus circuit, wherein the microprocessor circuit is connected to the CAN bus circuit.

[0007] The microprocessor circuit includes a processor chip U1, a crystal oscillator Y1, a crystal oscillator Y2, capacitors C10, C11, C9, and C22. The two ends of the crystal oscillator Y1 are connected to pins 8 and 9 of the processor chip U1, respectively, and the two ends of the crystal oscillator Y2 are connected to pins 12 and 13 of the processor chip U1, respectively.

[0008] The CAN bus circuit includes processor chip U4, processor chip U2, TVS diode NUP2105, gas discharge tube 3R090A, resistor R, capacitor C8 and connector JP8.

[0009] The first and second pins of the processor chip U4 are connected to the 81st and 82nd pins of the processor chip U1 respectively, and the 6th and 7th pins of the processor chip U4 are connected to the first and second pins of the connector JP8 respectively.

[0010] Further, the power supply circuit comprises a gas discharge tube TV1, a fuse F3, a voltage-dependent resistor R27, a diode D8, a diode D7, capacitors C24, C26, C23, C25, C1, C2, C3, C4, an inductor L1, a chip P2 and a processor chip U3.

[0011] Further, the first pins of the capacitors C10 and C11 are connected to the first and second pins of the crystal oscillator Y1 respectively, and the second pins of the capacitors C10 and C11 are connected to GND.

[0012] Further, the first pins of the capacitors C9 and C22 are connected to the first and third pins of the crystal oscillator Y2 respectively, and the second pins of the capacitors C9 and C22 are connected to GND.

[0013] Further, the 72nd pin of the processor chip U1 is connected to the second pin of the connector JP4, and the third pin of the connector JP4 is connected to the 76th pin of the processor chip U1.

[0014] Further, the resistor R comprises resistors R1, R2, R3, R4, R5, R6, R21 and R22, for limiting the amount of current passing through the circuit.

[0015] Further, the first pin of the chip P2 is connected to the diode D8 and the fuse F3 in sequence and connected to the power input port, and the second pin of the chip P2 is connected to the inductor L1 while connecting the diode D7.

[0016] Further, the first pin of the processor chip U3 is connected to the first pins of the capacitors C1 and C2, and the 5th pin of the processor chip U3 is connected to the first pins of the capacitors C3 and C4 and outputs the VCC power supply.

[0017] Further, the third pin of the TVS diode NUP2105 is connected to the first pin of the resistor R21 and the capacitor C8, the second pins of the resistor R21 and the capacitor C8 are connected to the third pin of the gas discharge tube 3R090A, the 5th pin of the processor chip U4 is connected to the 3rd pin of the UP2105, and the third pin of the gas discharge tube 3R090A is connected to the third pin of the connector JP8.

[0018] Compared with the prior art, the application has at least the following beneficial effects:

[0019] 1. The entire circuit can be connected to the CAN bus via a microprocessor circuit, power supply circuit, and CAN bus circuit. After configuring the bus communication rate, it automatically begins capturing and recording communication data upon power-up. Furthermore, the recorder is equipped with an RTC (Real-Time Clock) circuit, enabling continuous tracking and time recording. For convenient post-event analysis and retrieval, the circuit also uses an SD card to store data, greatly enhancing the analysis and diagnostic capabilities of remote CAN devices. The optimized data recording function also makes troubleshooting remote devices more efficient and convenient. Attached Figure Description

[0020] To more intuitively illustrate the prior art and this application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing this application; for example, based on the technical concept disclosed in this application and the exemplary drawings, those skilled in the art are able to easily make conventional adjustments or further optimizations to the addition / reduction / classification, specific shapes, positional relationships, connection methods, size ratios, etc. of certain units (components).

[0021] Fig. 1 A microprocessor circuit schematic diagram of a CAN bus data recording device circuit provided in one embodiment of this application;

[0022] Fig. 2 A power supply circuit schematic diagram of a CAN bus data recording device circuit provided in one embodiment of this application;

[0023] Fig. 3 This application provides a CAN bus circuit for a CAN bus data recording device circuit as one embodiment. Detailed Implementation

[0024] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] like Figs. 1 to 3 As shown, a CAN bus data recording device circuit according to the first aspect embodiment of this application includes: a microprocessor circuit, a power supply circuit, and a CAN bus circuit, wherein the microprocessor circuit is connected to the CAN bus circuit.

[0026] The microprocessor circuit includes a processor chip U1, crystal oscillator Y1, crystal oscillator Y2, capacitors C10, C11, C9 and C22. The two ends of crystal oscillator Y1 are connected to pins 8 and 9 of processor chip U1, respectively, and the two ends of crystal oscillator Y2 are connected to pins 12 and 13 of processor chip U1, respectively.

[0027] The processor chip U1 is a high-performance microcontroller of STMicroelectronics, responsible for the data acquisition of the entire circuit, and connected with PC through USB communication. The crystal oscillator Y1 provides low-speed clock, and the crystal oscillator Y1 provides high-speed clock. The capacitors C10, C11, C9 and C22 are resonance circuits. Meanwhile, the microprocessor circuit is also provided with a battery CR1 for providing continuous power.

[0028] The microprocessor circuit further comprises the connector JP6, resistors R13, R15 and R16, diodes D3, D4, D5 and D6, resistors R26, R23, R24 and R25, and capacitors C12-C21. The resistor R25 is connected to the pins 70 and 71 of the processor chip U1 through the circuits R13 and R15, and the resistor R16 is used to pull up the DEVDP network.

[0029] The diodes D3, D4, D5, resistors R26, R23 and R24 constitute a pilot lamp circuit. The capacitors C12-C21 are filter capacitors for filtering the chip. The first pin of the resistor R25 is connected to the pin 82 of the processor chip U1, the second pin of the resistor R25 is connected to the second pin of the diode D6, the first pin of the diode D6 is connected to the VCC-3.3 power supply network, and the USB interface is connected to the pins 70 and 71 of the processor chip through the resistors R13 and R15.

[0030] The first pins of the capacitors C10 and C11 are respectively connected to the first and second pins of the crystal oscillator Y1, and the second pins of the capacitors C10 and C11 are both connected to GND. The first pins of the capacitors C9 and C22 are respectively connected to the first and third pins of the crystal oscillator Y2, and the second pins of the capacitors C9 and C22 are both connected to GND.

[0031] The pin 72 of the processor chip U1 is connected to the second pin of the connector JP4, the first pin of the connector JP4 is connected to the VCC3.3 power supply, the third pin of the connector JP4 is connected to the pin 76 of the processor chip U1, and the fourth pin of the connector JP4 is connected to GND, for transmitting data.

[0032] The power supply circuit comprises a gas discharge tube TV1, a fuse F3, a voltage-dependent resistor R27, diodes D8 and D7, capacitors C24, C26, C23, C25, C1, C2, C3, C4, an inductor L1, a chip P2 and a processor chip U3.

[0033] The first pin of the chip P2 is connected with the fuse F3 and connected to the power input port, and the second pin of the fuse F3 is connected with the voltage-dependent resistor R27, the diode D1 and the first pin of the diode D8 respectively, the second pin of the voltage-dependent resistor R27 and the diode D1 are connected to the GND network, the second pin of the diode D8 is connected to the first pin of the capacitor C24 and the capacitor C26 respectively, and finally connected to the first pin of the chip P2, the second pin of the chip P2 is connected to the inductor L1 for voltage stabilization and simultaneously connected to the diode D7 for freewheeling.

[0034] The fourth pin of the chip P2 is connected to the output end of the inductor L1 as an output feedback, which plays a role in voltage stabilization. Capacitors C23, C24, C25 and C26 are used for output voltage stabilization. The processor chip U3 is a voltage reduction chip, and the first pin thereof is an input. The output of the fifth pin of the processor chip U3 is 3.3V, which is used by other devices.

[0035] The first pin of the processor chip U3 is connected to the first pins of the capacitors C1 and C2, and the fifth pin of the processor chip U3 is connected to the first pins of the capacitors C3 and C4 and outputs a VCC power supply. The second pins of the capacitors C1, C2, C3 and C4 and the second pin of the processor chip U3 are connected to the GND network.

[0036] The CAN bus circuit includes the processor chip U4, the processor chip U2, the TVS diode NUP2105, the gas discharge tube 3R090A, the resistor R, the capacitor C8 and the connector JP8. The processor chip U2 is a board-mounted memory interface, and the first, second, fifth and sixth pins of the processor chip U2 are connected with the twenty-ninth, thirtieth, thirty-first and thirty-second pins of the processor chip U1, which are used as temporary storage when the SDK card is missing.

[0037] The first and second pins of the processor chip U4 are connected with the eighty-first and eighty-second pins of the processor chip U1 respectively, and the sixth and seventh pins of the processor chip U4 are connected with the first and second pins of the connector JP8 respectively. The resistor R includes the resistors R1, R2, R3, R4, R5, R6, R21 and R22, which are used for limiting the amount of current passing through the circuit.

[0038] The third pin of the TVS diode NUP2105 is connected with the first pin of the resistor R21 and the capacitor C8, the second pins of the resistor R21 and the capacitor C8 are connected to the third pin of the gas discharge tube 3R090A, the fifth pin of the processor chip U4 is connected to the third pin of the UP2105, and the third pin of the gas discharge tube 3R090A is connected to the third pin of the connector JP8.

[0039] TF1 is an SD card interface, the 7th, 8th, 1st, 2nd, 5th, 3rd, 9th of which are connected with the 65th, 66th, 78th, 79th, 80th pin of the processor chip U1 respectively, each pin is connected with a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 respectively, the current through the circuit is limited by the resistor R, which is used for master control of reading and writing of the SD card.

[0040] The circuit is mounted on the CAN bus, and the communication rate of the bus is configured. After power-on, it automatically starts capturing and recording communication data. In addition, the recorder is equipped with an RTC (Real Time Clock) circuit, which can continuously track and keep time records. To facilitate subsequent analysis and search, the circuit also uses an SD card to store data, greatly improving the analysis and diagnosis capabilities of off-site CAN equipment. The optimized data recording function also makes the troubleshooting of remote equipment more efficient and convenient.

[0041] The technical features of the above embodiments can be combined in any manner (as long as the combination of the technical features does not exist contradictory). In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described. These embodiments which are not explicitly written should also be considered as the scope of the present disclosure.

Claims

1. A CAN bus data logger device circuit comprising a microprocessor circuit, a power supply circuit and a CAN bus circuit, characterised in that, The microprocessor circuit is connected with the CAN bus circuit; The microprocessor circuit comprises a processor chip U1, a crystal oscillator Y1, a crystal oscillator Y2, a capacitor C10, a capacitor C11, a capacitor C9 and a capacitor C22, two ends of the crystal oscillator Y1 are connected with the 8th and 9th pins of the processor chip U1 respectively, two ends of the crystal oscillator Y2 are connected with the 12th and 13th pins of the processor chip U1 respectively; The CAN bus circuit comprises a processor chip U4, a processor chip U2, a TVS diode NUP2105, a gas discharge tube 3R090A, a resistor R, a capacitor C8 and a connector JP8; The 1st and 2nd pins of the processor chip U4 are connected with the 81st and 82nd pins of the processor chip U1 respectively, the 6th and 7th pins of the processor chip U4 are connected with the 1st and 2nd pins of the connector JP8 respectively.

2. A CAN bus data logger device circuit according to claim 1, characterised in that, The power supply circuit comprises a gas discharge tube TV1, a fuse F3, a pressure-sensitive resistor R27, a diode D8, a diode D7, a capacitor C24, a capacitor C26, a capacitor C23, a capacitor C25, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an inductor L1, a chip P2 and a processor chip U3.

3. A CAN bus data logger device circuit according to claim 1, characterised in that, The 1st pins of the capacitor C10 and the capacitor C11 are connected with the 1st and 2nd pins of the crystal oscillator Y1 respectively, the 2nd pins of the capacitor C10 and the capacitor C11 are connected with GND.

4. A CAN bus data logger device circuit according to claim 1, characterised in that, The 1st pins of the capacitor C9 and the capacitor C22 are connected with the 1st and 3rd pins of the crystal oscillator Y2 respectively, the 2nd pins of the capacitor C9 and the capacitor C22 are connected with GND.

5. A CAN bus data logger device circuit according to claim 1, characterised in that, The 72nd pin of the processor chip U1 is connected with the 2nd pin of the connector JP4, the 3rd pin of the connector JP4 is connected with the 76th pin of the processor chip U1.

6. A CAN bus data logger device circuit according to claim 1, characterised in that, The resistor R comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R21 and a resistor R22, which are used for limiting the current flowing through the circuit.

7. A CAN bus data logger device circuit according to claim 2, characterised in that, The 1st pin of the chip P2 is connected with the diode D8 and the fuse F3 in sequence and connected with a power input port, and the 2nd pin of the chip P2 is connected with the inductor L1 and the diode D7 at the same time.

8. A CAN bus data logger device circuit according to claim 2, characterised in that, The 1st pin of the processor chip U3 is connected with the 1st pins of the capacitor C1 and the capacitor C2, the 5th pin of the processor chip U3 is connected with the 1st pins of the capacitor C3 and the capacitor C4 and outputs a VCC power supply.

9. A CAN bus data logger device circuit according to claim 1, characterised in that, The 3rd pin of the TVS diode NUP2105 is connected with the 1st pin of the resistor R21 and the capacitor C8 at the same time, the 2nd pins of the resistor R21 and the capacitor C8 are connected with the 3rd pin of the gas discharge tube 3R090A, the 5th pin of the processor chip U4 is connected with the 3rd pin of the UP2105, and the 3rd pin of the gas discharge tube 3R090A is connected with the 3rd pin of the connector JP8.

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