Signal jitter elimination circuit, control chip and electronic equipment
By using a combination of a first debouncing circuit, a second debouncing circuit, and a counter in the reset signal, the problem of simultaneous high and low level jitter in the reset signal is solved, achieving stable debouncing of the reset signal throughout its entire range and preventing erroneous operation.
Patent Information
- Application Number
- CN202522517869.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2035-11-27
AI Technical Summary
In existing technologies, when both high and low level jitter exist in the reset signal, it is impossible to completely eliminate the jitter.
A signal debouncing circuit including a first debouncing circuit, a second debouncing circuit, and a counter is adopted. Through multi-level delay and logic operation, different types of glitches are filtered out in the reset and reset states respectively, preventing false resets and misinterpretations.
It achieves comprehensive debouncing of the reset signal throughout its entire reset lifecycle, preventing false resets and misinterpretations, and ensuring signal stability.
Smart Images
Figure CN223809760U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of power electronics, especially to a signal dithering elimination circuit, a control chip and electronic equipment. BACKGROUND
[0002] In a SoC (System on Chip) chip, due to the influence of external factors, the reset signal received by the GPIO (General Purpose Input / Output) interface usually has a series of rapid and unstable dithers. Therefore, the reset signal needs to be dithered.
[0003] In the prior art, only the dither on a single level can be eliminated, that is, only the dither on the low level or the dither on the high level is eliminated. However, when the high level and the low level exist in the reset signal at the same time, and the dithers exist on the high level and the low level at the same time, the dithers cannot be completely eliminated. SUMMARY
[0004] The utility model provides a signal dithering elimination circuit, a control chip and electronic equipment to solve the defect that the dithers cannot be completely eliminated when the high level and the low level exist in the reset signal at the same time, and the dithers exist on the high level and the low level at the same time in the prior art.
[0005] The utility model provides a signal dithering elimination circuit, which comprises a first dithering elimination circuit, a second dithering elimination circuit and a counter connected in series.
[0006] The first dithering elimination circuit is used to perform multi-stage delay on the received original reset signal to obtain a logic OR signal maintaining a first level state, so as to filter out a first glitch in the original reset signal with a duration less than a first preset duration when the control chip is in a reset release state.
[0007] The second dithering elimination circuit is used to perform multi-stage delay on the logic OR signal to obtain a logic AND signal maintaining a second level state, so as to filter out a second glitch in the original reset signal with a duration less than the first preset duration when the control chip is in a reset state.
[0008] The counter is used to determine the count value of the logic AND signal in the second level state, and the count value is used to filter out a third glitch in the original reset signal with a duration greater than the first preset duration when the control chip is in the reset state.
[0009] The first glitch is in the second level state, and the second glitch and the third glitch are in the first level state.
[0010] The utility model provides a signal dithering circuit, the first dithering circuit includes no reset register group and or gate, wherein:
[0011] The input end of the no reset register group is used for receiving the original reset signal, at least two clock ends of the no reset register group are used for receiving the clock signal, at least two output ends of the no reset register group are connected with at least two input ends of the or gate correspondingly, and the output end of the or gate is connected with the input end and all reset ends of the second dithering circuit.
[0012] The no reset register group is used for carrying out multistage delay to the original reset signal to obtain multistage first delay reset signals.
[0013] The or gate is used for carrying out logic or operation to multistage first delay reset signals to obtain logic or signals maintaining the first level state.
[0014] The utility model provides a signal dithering circuit, the no reset register group includes at least two no reset registers connected in series, and the output end of each no reset register is connected with the input end of the or gate.
[0015] The first no reset register is used for receiving the original reset signal and filtering out the fourth glitch with the continuous time length less than the second preset time length in the original reset signal, and the second preset time length is less than the first preset time length.
[0016] The utility model provides a signal dithering circuit, the second dithering circuit includes reset register group and and gate, wherein:
[0017] The input end and all reset ends of the reset register group are connected with the output end of the or gate, at least two clock ends of the reset register group are used for receiving the clock signal, at least two output ends of the reset register group are connected with at least two input ends of the and gate correspondingly, and the output end of the and gate is connected with the reading end of the counter.
[0018] The reset register group is used for carrying out multistage delay to the logic or signal to obtain multistage second delay reset signals.
[0019] The and gate is used for carrying out logic and operation to multistage second delay reset signals to obtain logic and signals maintaining the second level state.
[0020] The utility model provides a signal dithering circuit, the reset register group includes at least two reset registers connected in series, and the output end of each reset register is connected with the input end of the and gate, and the clock end of each reset register is used for receiving the clock signal.
[0021] The utility model also provides a control chip, including the signal dithering circuit of any one of above.
[0022] The utility model also provides an electronic equipment, including the control chip of above.
[0023] The utility model provides a signal dithering circuit, control chip and electronic equipment, through the first dithering circuit is under the reset state and carries out the dithering, namely eliminates the first burr under the reset state, prevents the false reset, through the second dithering circuit and the counter is under the reset state and carries out the dithering, namely eliminates the second burr and the third burr under the reset state, prevents the false reset, thereby realizes the comprehensive dithering of the whole reset life cycle of original reset signal. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical scheme in the utility model or prior art, below will to the drawing needed to be used in the embodiment or prior art description a simple introduction, obviously, the drawing in the following description is some embodiments of the utility model, for those skilled in the art, under the premise of not paying creative labor, can also obtain other drawings according to these drawings.
[0025] Figure 1 It is the structural schematic diagram of signal dithering circuit provided by the utility model embodiment.
[0026] Figure 2 It is one of the structural schematic diagram of first dithering circuit provided by the utility model embodiment.
[0027] Figure 3 It is one of the structural schematic diagram of second dithering circuit provided by the utility model embodiment.
[0028] Figure 4 It is the second structural schematic diagram of first dithering circuit provided by the utility model embodiment.
[0029] Figure 5 It is the second structural schematic diagram of second dithering circuit provided by the utility model embodiment.
[0030] Reference signs:
[0031] 100: first dithering circuit;110: resetless register group;111: resetless register;120: or gate;200: second dithering circuit;210: reset register group;211: reset register;220: and gate;300: counter. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical scheme and advantages of the utility model clearer, the technical scheme in the utility model will be clearly and completely described in combination with the drawings in the utility model below. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the ordinary skilled in the art without creative labor belong to the protection scope of the utility model.
[0033] In view of the problem that in the prior art, high level and low level exist in the reset signal simultaneously, and when high level and low level exist simultaneously, the jitter cannot be eliminated completely, the utility model embodiment provides a signal jitter elimination circuit, Figure 1 It is the structure diagram of the signal jitter elimination circuit provided by the utility model embodiment, as Figure 1 The signal jitter elimination circuit includes first jitter elimination circuit 100, second jitter elimination circuit 200 and counter 300 connected in series, wherein:
[0034] The first jitter elimination circuit 100 is used for multistage delay to the received original reset signal, and obtains the logic or signal maintaining the first level state, so as to filter out the first glitch in the original reset signal with the duration less than the first preset duration when the control chip is in the reset state.
[0035] The second jitter elimination circuit 200 is used for multistage delay to the logic or signal, and obtains the logic and signal maintaining the second level state, so as to filter out the second glitch in the original reset signal with the duration less than the first preset duration when the control chip is in the reset state.
[0036] The counter 300 is used for determining the count value of the logic and signal in the second level state, and the count value is used for filtering out the third glitch in the original reset signal with the duration greater than the first preset duration when the control chip is in the reset state.
[0037] The first glitch is in the second level state, and the second glitch and the third glitch are in the first level state.
[0038] It should be noted that when the control chip is in the reset state, the original reset signal is continuously high level signal, and when the control chip is in the reset state, the original reset signal is continuously low level signal. The first level state is high level state, and the second level state is low level state. Based on this, the first glitch is low level glitch on the high level signal, and the second glitch and the third glitch are high level glitch on the low level signal, and the duration corresponding to the third glitch is greater than the duration corresponding to the second glitch.
[0039] In addition, the first preset time length can be an upper limit value of a delay time length of the first debounce circuit 100 for performing multi-stage delay on the original reset signal, or an upper limit value of a delay time length of the second debounce circuit 200 for performing multi-stage delay on the logic or signal. For example, a signal value output by the last stage in the first debounce circuit 100 within the first preset time length is always the signal value of the original reset signal sampled by the first debounce circuit 100 at the initial time. The upper limit values of the delay time lengths corresponding to the stages in the first debounce circuit 100 or the second debounce circuit 200 are different, and the upper limit values of the delay time lengths increase stage by stage.
[0040] Specifically, the first debounce circuit 100, the second debounce circuit 200, and the counter 300 are connected in series in sequence, the input end of the first debounce circuit 100 is connected to the GPIO interface of the control chip and is used to receive the original reset signal sent by the GPIO interface. The first debounce circuit 100 can perform stage-by-stage delay on the original reset signal, and perform logic or operation on the signals after stage-by-stage delay to obtain a logic or signal. Then, the logic or signal is output to the second debounce circuit 200, the second debounce circuit 200 performs stage-by-stage delay on the logic or signal, and performs logic and operation on the signals after stage-by-stage delay to obtain a logic and signal. Then, the logic and signal is output to the counter 300. The level state of the logic and signal is used to control whether the counter 300 is in a counting state based on the working state of the control chip. For example, when the control chip is in a reset state, if the logic and signal is a high-level signal, the counter 300 is in the counting state and starts counting, and if the logic and signal is a low-level signal, the counter 300 is in a forwarding state, at this time, no counting is performed, and the logic and signal is directly forwarded to the next stage circuit. When the control chip is in a reset state, the counter 300 is in a forwarding state, at this time, no counting is performed, and the logic and signal is directly forwarded to the next stage circuit. The output end of the counter 300 is connected to the next stage circuit, and is used to control the next stage circuit to be in a reset state or a reset state.
[0041] In the case that the control chip is in the reset state, the original reset signal is a low-level signal. When a high-level glitch (i.e., the second glitch) exists on the original reset signal and the duration of the high-level glitch is less than the first preset duration, the output signal of the last stage of the first debounce circuit 100 is always a low-level signal, but at least one of the output signals of the other stages of the first debounce circuit 100 is a high-level signal. After the logical OR operation of the output signals of the stages of the first debounce circuit 100, the obtained logical OR signal is a high-level signal, and the duration of the high-level signal is less than the first preset duration. After the logical OR signal output to the second debounce circuit 200, the output signal of the last stage of the second debounce circuit 200 is always a high-level signal, but at least one of the output signals of the other stages of the second debounce circuit 200 is a low-level signal. After the logical AND operation of the output signals of the stages of the second debounce circuit 200, the obtained logical AND signal is a low-level signal. After the counter 300 receives the logical AND signal which is a low-level signal, the counter 300 forwards the logical AND signal to the subsequent circuit, and the logical AND signal which is a low-level signal can keep the subsequent circuit in the reset state and avoid being misreset.
[0042] In the case that the control chip is in the reset state, the original reset signal is a low-level signal. When a high-level glitch (i.e., the second glitch) exists on the original reset signal and the duration of the high-level glitch is less than the first preset duration, the output signal of the last stage of the first debounce circuit 100 is always a low-level signal, but at least one of the output signals of the other stages of the first debounce circuit 100 is a high-level signal. After the logical OR operation of the output signals of the stages of the first debounce circuit 100, the obtained logical OR signal is a high-level signal, and the duration of the high-level signal is less than the first preset duration. After the logical OR signal output to the second debounce circuit 200, the output signal of the last stage of the second debounce circuit 200 is always a high-level signal, but at least one of the output signals of the other stages of the second debounce circuit 200 is a low-level signal. After the logical AND operation of the output signals of the stages of the second debounce circuit 200, the obtained logical AND signal is a low-level signal. After the counter 300 receives the logical AND signal which is a low-level signal, the counter 300 forwards the logical AND signal to the subsequent circuit, and the logical AND signal which is a low-level signal can keep the subsequent circuit in the reset state and avoid being misreset.
[0043] In the case that the control chip is in the reset state, if the duration of the high-level glitch (i.e., the third glitch) is greater than the first preset duration, the output signals of the stages of the second debounce circuit 200 are all high-level signals. After the logical AND operation of the output signals of the stages of the second debounce circuit 200, the obtained logical AND signal is a high-level signal. After the counter 300 receives the logical AND signal which is a high-level signal, the counter 300 starts counting, and compares the count value with a preset threshold. By designing the preset threshold, the count value is always less than the preset threshold. At this time, the count value of the counter 300 is reset, avoiding the transmission of the logical AND signal which is a high-level signal to the subsequent circuit, i.e., avoiding the misreset of the subsequent circuit.
[0044] Optionally, the preset threshold in the counter 300 can be 256 or 512, and the like, and the embodiments of the present application do not limit this.
[0045] The signal de-bouncing circuit provided by the embodiments of the present application eliminates the low-level burr in the de-reset state through the first de-bouncing circuit 100, prevents false reset, eliminates the high-level burr in the reset state through the second de-bouncing circuit 200 and the counter 300, prevents false de-reset, and thus realizes comprehensive de-bouncing of the entire reset life cycle of the original reset signal.
[0046] In one embodiment, Figure 2 is one of the structural schematic diagrams of the first de-bouncing circuit 100 provided by the embodiments of the present application, as Figure 2 indicated, the first de-bouncing circuit 100 includes a non-reset register group 110 and an or gate 120, wherein:
[0047] The input end of the non-reset register group 110 is used for receiving the original reset signal, at least two clock ends CK of the non-reset register group 110 are used for receiving a clock signal, at least two output ends of the non-reset register group 110 are correspondingly connected with at least two input ends of the or gate 120, and the output end of the or gate 120 is connected with the input end and all reset ends RD of the second de-bouncing circuit 200;
[0048] The non-reset register group 110 is used for performing multi-stage delay on the original reset signal to obtain multi-stage first delay reset signals;
[0049] The or gate 120 is used for performing logic or operation on the multi-stage first delay reset signals to obtain a logic or signal maintaining the first level state.
[0050] Specifically, in the first debouncing circuit 100, all clock terminals CK of the reset-free register group 110 synchronously receive clock signals, each stage in the reset-free register group 110 samples signals based on the clock signals, and each stage delays the sampled signal value by one clock cycle, so that the entire reset-free register group 110 realizes multi-stage delay on the original reset signal, and each stage outputs a corresponding first delayed reset signal to a corresponding input terminal of the OR gate 120, all first delayed reset signals are logically ORed in the OR gate 120 to obtain a logical OR signal. When the control chip is in the reset state, the original reset signal is continuously a high-level signal. If there is no glitch on the original reset signal, the first delayed reset signal output by each stage in the reset-free register group 110 is a high-level signal, so that the logical OR signal output by the OR gate 120 is a high-level signal. If there is a low-level glitch on the original reset signal, and the duration of the low-level glitch is less than the first preset duration, the first delayed reset signal output by the last stage in the reset-free register group 110 is always a high-level signal, and at least one of the first delayed reset signals output by the other stages is a low-level signal. Therefore, there is always at least one high-level signal in all first delayed reset signals, so that the logical OR signal output by the OR gate 120 remains a high-level signal, so that the subsequent circuit remains in the reset state and is not misreset.
[0051] In one embodiment, the reset-free register group 110 includes at least two reset-free registers 111 connected in series, and the output terminal of each reset-free register 111 is connected to the input terminal of the OR gate 120;
[0052] The first reset-free register 111 is used to receive the original reset signal and filter out a fourth glitch in the original reset signal with a duration less than a second preset duration; the second preset duration is less than the first preset duration.
[0053] It should be noted that the resetless register 111 is a D flip-flop without reset end, when the rising edge or falling edge of the clock signal arrives, the input end (i.e. D end) of the resetless register 111 samples the signal, and outputs through the output end (i.e. Q end), and the value of the output end remains unchanged in the clock period of the resetless register 111, until the next rising edge or falling edge arrives to resample. Therefore, in the resetless register group 110, after the first-stage resetless register 111 samples the original reset signal at the initial time, the output end keeps the signal value sampled at the initial time for a second preset time length. The second preset time length is the clock period of the first-stage resetless register 111, and is determined according to the reference clock of the first-stage resetless register 111. For example, taking 25MHz as the reference clock of the first-stage resetless register 111 as an example, the clock period or the second preset time length of the first-stage resetless register 111 can be determined as 40ns. The falling edge of the clock signal arrives at t=0ns, the first-stage resetless register 111 samples the original reset signal at t=0ns, and outputs the sampled signal value, and the output end of the first-stage resetless register 111 keeps the signal value in the period from t=0ns to t=40ns. If there is a fourth glitch in the original reset signal in the period from t=0ns to t=40ns, the output end of the first-stage resetless register 111 keeps the sampling value at t=0ns, and the fourth glitch is filtered out. The fourth glitch can be a low-level glitch or a high-level glitch.
[0054] It should be noted that when the control chip is in the reset state, the duration of the filterable low-level glitch depends on the total number of stages of the resetless registers 111 in the resetless register group 110 and the clock period of each resetless register 111, i.e. the first preset time length depends on the total number of stages of the resetless registers 111 in the resetless register group 110 and the clock period of each resetless register 111. For example, when the clock period of each resetless register 111 is 40ns, and the resetless register group 110 includes four-stage resetless registers, the duration of the filterable low-level glitch or the first preset time length is 160ns.
[0055] In one embodiment, Figure 3 is one of the structure diagrams of the second de-bouncing circuit 200 provided by the embodiments of the present application, as shown in Figure 3 The second de-bouncing circuit 200 includes a reset register group 210 and an AND gate 220, wherein:
[0056] The input end of the reset register group 210 and all reset ends RD are connected to the output end of the OR gate 120, at least two clock ends CK of the reset register group 210 are used to receive the clock signal, at least two output ends of the reset register group 210 are connected to at least two input ends of the AND gate 220 in correspondence, and the output end of the AND gate 220 is connected to the reading end of the counter 300;
[0057] The reset register group 210 is used to delay the logic OR signal for multiple stages to obtain multiple second delay reset signals.
[0058] The AND gate 220 is used to perform a logic AND operation on the multiple second delay reset signals to obtain a logic AND signal maintaining the second level state.
[0059] Specifically, in the second de-bouncing circuit 200, all clock ends CK of the reset register group 210 synchronously receive the clock signal, each stage in the reset register group 210 samples the signal based on the clock signal, and each stage delays the sampled signal value by one clock period, so that the entire reset register group 210 realizes multi-stage delay on the logic OR signal, and each stage outputs a corresponding second delay reset signal to the corresponding input end of the AND gate 220, and all second delay reset signals perform a logic AND operation in the AND gate 220 to obtain a logic AND signal. When the control chip is in a reset state, the original reset signal is continuously a low-level signal. If there is no high-level glitch on the original reset signal, the first delay reset signal output by each stage in the reset-free register group 110 is a low-level signal, so that the logic OR signal output by the OR gate 120 is a low-level signal. Then, the second delay reset signal output by each stage in the reset register 211 is a low-level signal, so that the logic AND signal output by the AND gate 220 is a low-level signal. If there is a high-level glitch on the original reset signal, and the duration of the high-level glitch is less than the first preset duration, there is at least one and at most N-1 first delay reset signals being high-level signals in the reset-free register 111, N represents the total number of stages of the reset-free register 111 in the reset-free register group 110, and there is at least one first delay reset signal being a low-level signal. At this time, the logic OR signal output by the OR gate 120 is a high-level signal, and the duration of the high-level signal is less than the first preset duration. Then, the second delay reset signal output by the last stage in the reset register group 210 is always a low-level signal, and there is at least one second delay reset signal being a high-level signal among the second delay reset signals output by the other stages except the last stage. Therefore, there is always at least one low-level signal among all second delay reset signals, so that the logic AND signal output by the AND gate 220 remains a low-level signal, so that the subsequent stage circuit is in a reset state and will not be misreset.
[0060] In one embodiment, the reset register group 210 includes at least two reset registers 211 connected in series, and the output of each reset register 211 is connected to the input of the AND gate 220; the clock terminal CK of each reset register 211 is used to receive the clock signal.
[0061] It should be noted that each level of the reset register 211 is a D flip-flop with a reset terminal, and the logic AND signal is input to the reset terminal RD of each level of the reset register 211 and the D terminal of the first level reset register 211.
[0062] It should be noted that when the control chip is in reset state, the duration of the high-level glitches that can be filtered out depends on the total number of reset registers 211 in the reset register group 210 and the clock period of each reset register 211. For example, when the clock period of each reset register 211 is 40ns and the reset register group 210 includes four reset registers 211, the duration of the high-level glitches that can be filtered out is 160ns.
[0063] For example, taking a no-reset register group 110 that includes four levels of no-reset registers 111, where the clock period of each level of no-reset register 111 is 40ns, the duration of a low-level glitches is 60ns, and the occurrence period is from t=10ns to 70ns, as an example... Figure 4 This is a second schematic diagram of the structure of the first debounce circuit 100 provided in this embodiment of the present invention, as shown below. Figure 4 As shown, when the control chip is in the de-reset state, the falling edge arrives at t=0ns. In this no-reset register group 110, the first-level no-reset register 111 (i.e. Figure 4 The leftmost no-reset register shown receives the original reset signal at its D terminal and samples it at t=0ns. At this time, there is no low-level glitches. Therefore, the first delayed reset signal output by the Q terminal of each of the four no-reset registers 111 is a high-level signal. After performing a logical OR operation on the four high-level signals in the OR gate 120, the resulting logical OR signal is a high-level signal.
[0064] The falling edge arrives at t=40ns, the D end of the first non-reset register 111 is sampled, and since there is a low level glitch at this time, the first delay reset signal output by the Q end of the first non-reset register 111 at t=40ns is a low level signal. The D end of the other three non-reset registers 111 is still sampled by the first delay reset signal output by the previous non-reset register 111 at t=0ns, so the first delay reset signal output by the corresponding Q end of the other three non-reset registers 111 is still a high level signal. Then, the logic or signal obtained by performing logic or operation on one low level signal and three high level signals in the or gate 120 still maintains a high level signal.
[0065] The falling edge arrives at t=80ns, and since there is no low level glitch at this time, the first delay reset signal output by the first non-reset register 111 at t=80ns is a high level signal, the second non-reset register 111 samples the first delay reset signal output by the first non-reset register 111 at t=40ns, so the first delay reset signal output by the second non-reset register 111 at t=80ns is a low level signal, and the D end of the other two non-reset registers 111 still samples the first delay reset signal output by the previous non-reset register 111 at t=40ns, so the first delay reset signal output by the corresponding Q end of the other two non-reset registers 111 is still a high level signal. Then, the logic or signal obtained by performing logic or operation on one low level signal and three high level signals in the or gate 120 still maintains a high level signal. Therefore, in the case that the control chip is in the reset state, the low level glitch appearing in the period of t=10ns to 70ns in the original reset signal does not affect the level of the logic or signal, thereby achieving the effect of filtering out the low level glitch.
[0066] For example, the non-reset register group 110 includes four non-reset registers 111, the clock period of each non-reset register 111 is 40ns, the reset register group 210 includes four reset registers 211, the clock period of each reset register 211 is 40ns, the high level glitch corresponds to a duration of 60ns, and appears in the period of t=10ns to 70ns. Figure 5 is a second structure schematic view of the second de-bouncing circuit 200 provided by the embodiment of the present application, like Figure 5As shown, at t=0ns, the rising edge arrives at the control chip, and since there is no high-level glitch at this time, the first delay reset signals output by the Q terminals of the four-stage non-reset register 111 in the non-reset register group 110 are all low-level signals, and the logic OR signal obtained is a low-level signal. Then, the second delay reset signals output by the Q terminals of the four-stage reset register 211 in the reset register group 210 are all low-level signals, and the logic AND signal obtained is a low-level signal.
[0067] At t=40ns, the rising edge arrives, and since there is a high-level glitch at this time, the first delay reset signal output by the Q terminal of the first-stage non-reset register 111 at t=40ns is a high-level signal. The D terminals of the other three-stage non-reset registers 111 still sample the first delay reset signal output by the previous-stage non-reset register 111 at t=0ns, so the first delay reset signals output by the corresponding Q terminals of the other three-stage non-reset registers 111 are still low-level signals. Then, the logic OR operation is performed on one high-level signal and three low-level signals in the OR gate 120, and the logic OR signal obtained is a high-level signal. Then, the first-stage reset register 211 (i.e. Figure 5 the leftmost reset register) in the reset register group 210 samples the high-level signal at t=40ns, and outputs a high-level second delay reset signal. The D terminals of the other three-stage reset registers 211 still sample the second delay reset signal output by the previous-stage reset register 211 at t=0ns, so the second delay reset signals output by the Q terminals of the other three-stage reset registers 211 are still low-level signals. Then, the logic AND operation is performed on one high-level signal and three low-level signals in the AND gate 220, and the logic AND signal obtained remains a low-level signal.
[0068] At the rising edge at t=80ns, since there is no high level glitch at this time, the second delay reset signal output by the first level reset register 211 at t=80ns is a low level signal, and the second delay reset signal sampled by the second level reset register 211 is the second delay reset signal output by the first level reset register 211 at t=40ns. Therefore, the first delay reset signal output by the second level reset register 211 at t=80ns is a high level signal, and the D end of the other two level reset registers 211 still samples the second delay reset signal output by the previous level reset register 211 at t=40ns. Therefore, the second delay reset signal output by the Q end of the other two level reset registers 211 is still a low level signal. Then, the logic and signal in the AND gate 220 is still a logic and operation of one high level signal and three low level signals, and the logic and signal still remains a low level signal. Therefore, in the reset state of the control chip, the high level glitch in the original reset signal in the period from t=10ns to t=70ns does not affect the level of the logic and signal, thereby achieving the effect of filtering the high level glitch.
[0069] For example, taking the preset threshold value of 256 corresponding to the counter 300 as an example, in the reset state of the control chip, if there is a high level glitch with a duration of 240ns in the original reset signal, in the first 160ns, the logic or signal and the logic and signal are both high level signals, the counter 300 starts counting, and the count value of the counter 300 switches from 0 to 1. In the same rising edge in the last 80ns, at most two first delay reset signals output from the reset register group 110 are high level signals, and the other two first delay reset signals are low level signals, so that the logic or signal is a high level signal in the 80ns. Then, at most two second delay reset signals output from the reset register group 210 are high level signals, and the other two second delay reset signals are low level signals, so that the logic and signal remains a low level signal. Therefore, the final count value of the counter 300 is 1, and 1<256, so that the count value is cleared, the counter 300 still forwards the low level signal to the rear stage circuit, and the rear stage circuit remains in the reset state and is not mistaken as reset. The high level glitch with a duration of 240ns does not affect the level of the logic and signal, thereby achieving the effect of filtering the high level glitch.
[0070] The embodiment of the utility model further provides a control chip, the control chip includes the signal dithering circuit as any one of above-mentioned embodiment.
[0071] Optionally, the control chip can be a SoC (System on Chip, System on Chip) chip or an MCU (MicroController Unit, Microcontroller Unit) and the like. The embodiment of the utility model does not make limitation to this.
[0072] The utility model embodiment further provides an electronic equipment, the electronic equipment includes the control chip that above described embodiment has described.
[0073] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the utility model, but not to limit them; although the utility model has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the utility model.
Claims
1. A signal debouncing circuit, characterized by, The signal debounce circuit comprises a first debounce circuit, a second debounce circuit and a counter connected in series. The first debounce circuit is configured to perform multi-stage delay on the received original reset signal to obtain a logic OR signal maintaining a first level state, so as to filter out a first glitch in the original reset signal with a duration less than a first preset duration when the control chip is in a reset state. The second debounce circuit is configured to perform multi-stage delay on the logic OR signal to obtain a logic AND signal maintaining a second level state, so as to filter out a second glitch in the original reset signal with a duration less than the first preset duration when the control chip is in a reset state. The counter is configured to determine a count value of the logic AND signal in the second level state, and the count value is used to filter out a third glitch in the original reset signal with a duration greater than the first preset duration when the control chip is in a reset state. The first glitch is in the second level state, and the second glitch and the third glitch are in the first level state. The first debounce circuit comprises a resetless register group and an OR gate. The resetless register group is configured to receive the original reset signal, and at least two clock terminals of the resetless register group are configured to receive a clock signal. The resetless register group is configured to perform multi-stage delay on the original reset signal to obtain a plurality of first delay reset signals. The OR gate is configured to perform logic OR operation on the plurality of first delay reset signals to obtain the logic OR signal maintaining the first level state.
2. The signal debouncing circuit of claim 1, wherein, The resetless register group comprises at least two resetless registers connected in series, and the output terminal of each resetless register is connected to the input terminal of the OR gate. The first resetless register is configured to receive the original reset signal and filter out a fourth glitch in the original reset signal with a duration less than a second preset duration.
3. The signal debouncing circuit of claim 1, wherein, The second debounce circuit comprises a reset register group and an AND gate. The reset register group is configured to receive the logic OR signal, and at least two clock terminals of the reset register group are configured to receive the clock signal. The reset register group is configured to perform multi-stage delay on the logic OR signal to obtain a plurality of second delay reset signals. The AND gate is configured to perform logic AND operation on the plurality of second delay reset signals to obtain the logic AND signal maintaining the second level state.
4. The signal debouncing circuit of claim 3, wherein, The reset register group comprises at least two reset registers connected in series, and the output terminal of each reset register is connected to the input terminal of the AND gate.
5. A control chip, characterized by The signal debounce circuit comprises the signal debounce circuit of any one of claims 1-4.
6. An electronic device, comprising: The control chip of claim 5 is included.