Solar cell

Abstract

The utility model discloses a solar cell, which is applied to the field of photovoltaic technology. A laminated structure in which two tunneling layers and two doped polycrystalline silicon layers are alternately arranged along the thickness direction is arranged in a grid line area, and a thicker doped polycrystalline silicon layer is designed by controlling the thickness of a first doped polycrystalline silicon layer and the thickness ratio of the first doped polycrystalline silicon layer to a second doped polycrystalline silicon layer; the doped polycrystalline silicon layer can be effectively prevented from being burnt through by a grid line to realize tunneling transmission, the damage caused by laser etching of a non-grid line region is reduced, the doping amount is improved to realize better ohmic contact, so that the recombination of carriers in the grid line region is effectively reduced, the filling factor and the open-circuit voltage of the cell are improved, and the series resistance is reduced; and meanwhile, a tunneling layer and a doped polycrystalline silicon layer are not arranged in a non-grid line region, so that parasitic absorption can be greatly reduced, and the cell efficiency can be further improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to photovoltaic technology field, especially a solar cell. BACKGROUND

[0002] TOPCon (Tunnel Oxide Passivating Contact, tunnel oxide passivating contact) is a kind of tunnel oxide passivating contact solar cell technology based on selective carrier principle, its core feature is to prepare a layer of tunnel oxide layer and a layer of doped polysilicon layer on the back of cell, form passivation contact structure.Design thicker doped polysilicon layer can reduce the recombination of carrier in grid line area, reach the purpose of improving cell efficiency.However, doped polysilicon layer is too thick to increase parasitic absorption to light simultaneously, resulting in the reduction of cell efficiency.The current solution is the passivation contact structure of local tunnel layer and doped polysilicon layer, for example: CN110752261A discloses two kinds of local passivation contact structures, wherein grid line area adopts the passivation contact structure of a layer of tunnel oxide layer and a layer of doped polysilicon layer, due to the doped polysilicon layer in grid line area is too thin, the effect of reducing carrier recombination in grid line area is poor, non-grid line area adopts the passivation contact structure of a layer of tunnel oxide layer and a layer of doped polysilicon layer, due to the doped polysilicon layer in grid line area is too thick, the effect of reducing parasitic absorption to light is poor;CN117012839A discloses a kind of local passivation contact structure, non-grid line area also adopts the passivation contact structure of a layer of tunnel oxide layer and a layer of doped polysilicon layer, the effect of reducing parasitic absorption to light is also poor. CONTENT OF UTILITY MODEL

[0003] Therefore, the utility model aims at providing a kind of solar cell for improving cell efficiency.

[0004] To solve the above technical problems, the utility model provides a kind of solar cell, comprising: substrate;The back of the substrate includes grid line area and non-grid line area;

[0005] The grid line area is provided with back grid line and first tunnel layer, first doped polysilicon layer, second tunnel layer and second doped polysilicon layer arranged in thickness direction in sequence;The back grid line penetrates the second doped polysilicon layer and the second tunnel layer in sequence along the thickness direction, and contacts the first doped polysilicon layer;

[0006] The ratio of the thickness of the second doped polysilicon layer to the thickness of the first doped polysilicon layer is 2-6.5, and includes both ends of the value;The thickness of the first doped polysilicon layer is 20nm-40nm, and includes both ends of the value;

[0007] The non-grid line area is not provided with tunnel layer and doped polysilicon layer.

[0008] Optionally, the thickness of the second doped polysilicon layer is 90-130 nm, inclusive of the endpoints.

[0009] Optionally, the ratio of the thickness of the first tunneling layer to the thickness of the second tunneling layer is 1.25-4.5, inclusive of the endpoints.

[0010] Optionally, the sum of the thickness of the second tunneling layer and the thickness of the first tunneling layer is 2-3.4 nm, inclusive of the endpoints.

[0011] Optionally, the thickness of the first tunneling layer is 1.5-2.2 nm, inclusive of the endpoints.

[0012] Optionally, the thickness of the second tunneling layer is 0.5-1.2 nm, inclusive of the endpoints.

[0013] Optionally, the surface of the second doped polysilicon layer facing away from the second tunneling layer and the non-gate line area are both provided with a back passivation layer; the surface of the back passivation layer facing away from the substrate is provided with a back anti-reflection layer.

[0014] Optionally, the ratio of the thickness of the back anti-reflection layer to the thickness of the back passivation layer is 10-30, inclusive of the endpoints.

[0015] Optionally, the thickness of the back passivation layer is 3-7 nm, inclusive of the endpoints.

[0016] Optionally, the thickness of the back anti-reflection layer is 70-90 nm, inclusive of the endpoints.

[0017] Optionally, the back gate line sequentially penetrates the back anti-reflection layer, the back passivation layer, the second doped polysilicon layer and the second tunneling layer along the thickness direction, and contacts the first doped polysilicon layer.

[0018] Optionally, the front surface of the substrate is sequentially provided with an emitter and a front gate line along the thickness direction; the surface of the emitter facing away from the substrate is provided with a front passivation layer; the surface of the front passivation layer facing away from the emitter is provided with a front anti-reflection layer; the front gate line sequentially penetrates the front anti-reflection layer and the front passivation layer along the thickness direction, and contacts the emitter.

[0019] The utility model provides a solar cell, include: substrate, the substrate back includes grid line area and non grid line area, grid line area is provided with back grid line and along thickness direction sequentially arranged first tunneling layer, first doped polysilicon layer, second tunneling layer and second doped polysilicon layer, back grid line along thickness direction sequentially penetrates second doped polysilicon layer and second tunneling layer with first doped polysilicon layer contact, the ratio of the thickness of second doped polysilicon layer and the thickness of first doped polysilicon layer is 2-6.5, and including both ends value, the thickness of first doped polysilicon layer is 20nm-40nm, and including both ends value, non grid line area is not provided with tunneling layer and doped polysilicon layer.

[0020] The utility model discloses a solar cell, include: substrate, the substrate back includes grid line area and non grid line area, grid line area is provided with back grid line and along thickness direction sequentially arranged first tunneling layer, first doped polysilicon layer, second tunneling layer and second doped polysilicon layer, back grid line along thickness direction sequentially penetrates second doped polysilicon layer and second tunneling layer with first doped polysilicon layer contact, the ratio of the thickness of second doped polysilicon layer and the thickness of first doped polysilicon layer is 2-6.5, and including both ends value, the thickness of first doped polysilicon layer is 20nm-40nm, and including both ends value, non grid line area is not provided with tunneling layer and doped polysilicon layer. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, below will to the drawing needed to use in the embodiment or prior art description simple introduction, obviously, below description's drawing only the embodiment of the utility model, for the ordinary skilled person in the art comes, under the premise of not paying the creative labor, still can obtain other's drawing according to the provided drawing.

[0022] Figure 1 The utility model provides a solar cell's structural schematic diagram.

[0023] The signs in the drawings are explained as follows:

[0024] 11 - substrate; 12 - emitter; 13 - front passivation layer; 14 - front antireflection layer; 15 - front grid line; 161 - first tunneling layer; 162 - second tunneling layer; 171 - first doped polysilicon layer; 172 - second doped polysilicon layer; 18 - back passivation layer; 19 - back antireflection layer; 20 - back grid line. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0026] Please refer to Figure 1 , Figure 1 A structural schematic diagram of a solar cell is provided in the embodiments of the present application. The solar cell can include: a substrate 11; the back of the substrate 11 includes a grid line area and a non-grid line area;

[0027] The grid line area is provided with a back grid line 20 and a first tunneling layer 161, a first doped polysilicon layer 171, a second tunneling layer 162 and a second doped polysilicon layer 172 arranged in sequence along the thickness direction; the back grid line 20 penetrates the second doped polysilicon layer 172 and the second tunneling layer 162 in sequence along the thickness direction, and is in contact with the first doped polysilicon layer 171;

[0028] The ratio of the thickness of the second doped polysilicon layer 172 to the thickness of the first doped polysilicon layer 171 is 2-6.5, and includes the values at both ends; the thickness of the first doped polysilicon layer 171 is 20-40 nm, and includes the values at both ends;

[0029] The non-grid line area is not provided with a tunneling layer and a doped polysilicon layer.

[0030] The embodiment is not limited to the specific thickness of the second doped polysilicon layer 172. For example, the thickness of the second doped polysilicon layer 172 can be 90-130 nm, and the values at both ends are included. It should be noted that the thickness of the first doped polysilicon layer 171 and the thickness of the second doped polysilicon layer 172 in the embodiment affect the overall thickness of the doped polysilicon layer. The thicker the overall thickness of the doped polysilicon layer, the less likely the gate line is to burn through the doped polysilicon layer, thereby ensuring that tunneling transmission can be achieved. The thicker the overall thickness of the doped polysilicon layer, the less damage caused by laser etching in the non-gate line area. The thicker the overall thickness of the doped polysilicon layer, the more doping, the better the ohmic contact, and the lower the recombination of carriers in the corresponding gate line area. The thinner the overall thickness of the doped polysilicon layer, the less parasitic absorption of light. In the embodiment, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 with the above thickness can effectively reduce the recombination of carriers in the gate line area while ensuring that the parasitic absorption of light in the gate line area is not too high. The preferred thickness of the first doped polysilicon layer 171 in the embodiment can be 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 38 nm, 39 nm, or 40 nm. The preferred thickness of the second doped polysilicon layer 172 in the embodiment can be 90 nm, 91 nm, 92 nm, 93 nm, 94 nm, 128 nm, 129 nm, or 130 nm.

[0031] The embodiment is not limited to the specific type of the substrate 11. The substrate 11 can be, but is not limited to, an N-type substrate or a P-type substrate. The embodiment is not limited to the specific type of the substrate 11. The substrate 11 can be, but is not limited to, a silicon substrate. It should be noted that silicon is a common material in the prior art. The embodiment does not limit the internal components of the substrate 11, but directly uses a silicon substrate made of existing materials. The embodiment is not limited to the specific thickness of the substrate 11. For example, the thickness of the substrate 11 can be 100-200 μm, and the values at both ends are included.

[0032] Further, in order to improve the light trapping effect of the front surface of the substrate 11, the front surface of the substrate 11 can have a pyramid surface in the embodiment.

[0033] The embodiment is not limited to the specific type of the first tunneling layer 161 and the second tunneling layer 162. The first tunneling layer 161 and the second tunneling layer 162 can include, but are not limited to, a silicon oxide layer. It should be noted that the silicon oxide layer is a common material in the prior art. The embodiment does not limit the internal components of the first tunneling layer 161 and the second tunneling layer 162, but directly uses a film layer made of existing materials as the first tunneling layer 161 and the second tunneling layer 162

[0034] The embodiment is not limited to the specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172, and the specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be N-type doped polysilicon layers; when the substrate 11 is a P-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be P-type doped polysilicon layers. The N-type doped polysilicon layer is doped with N-type impurities, and the P-type doped polysilicon layer is doped with P-type impurities.

[0035] The embodiment is not limited to the specific ratio of the thickness of the first tunneling layer 161 to the thickness of the second tunneling layer 162. For example, the ratio of the thickness of the first tunneling layer 161 to the thickness of the second tunneling layer 162 can be 1.25-4.5, and the values at both ends are included. The embodiment is not limited to the sum of the thickness of the second tunneling layer 162 and the thickness of the first tunneling layer 161. For example, the sum of the thickness of the second tunneling layer 162 and the thickness of the first tunneling layer 161 can be 2 nm-3.4 nm, and the values at both ends are included. The embodiment is not limited to the specific thickness of the first tunneling layer 161. For example, the thickness of the first tunneling layer 161 can be 1.5 nm-2.2 nm, and the values at both ends are included. The embodiment is not limited to the specific thickness of the second tunneling layer 162. For example, the thickness of the second tunneling layer 162 can be 0.5 nm-1.2 nm, and the values at both ends are included. It should be noted that the thicker the thickness of the first tunneling layer 161 and the second tunneling layer 162 in the embodiment can reduce the recombination of minority carriers, and at the same time, the gate line is less likely to burn through the doped polysilicon layer. The preferred thickness of the first tunneling layer 161 in the embodiment can be 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 3.2 nm, 3.3 nm, or 3.4 nm. The preferred thickness of the second tunneling layer 162 in the embodiment can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, or 1.2 nm.

[0036] The embodiment is not limited to the specific type of the back gate line 20. The back gate line 20 can be, but is not limited to, a metal gate line. It should be noted that metal is a common material in the prior art. The embodiment is not limited to the internal components of the back gate line 20, but directly uses a metal gate line made of an existing material as the back gate line 20.

[0037] Further, in order to improve the passivation effect, the surface of the second doped polysilicon layer 172 away from the second tunneling layer 162 and the non-gate line area can be provided with a back passivation layer 18. The specific type of the back passivation layer 18 is not limited in the embodiment, and the back passivation layer 18 can include, but is not limited to, an aluminum oxide layer. It should be noted that the aluminum oxide layer is a common material in the prior art, and the embodiment does not limit the internal components of the back passivation layer 18, but directly uses the film layer made of the existing material as the back passivation layer 18.

[0038] Further, in order to reduce light reflection, the surface of the back passivation layer 18 away from the substrate 11 is provided with a back anti-reflection layer 19. It should be noted that the back anti-reflection layer 19 can also provide a passivation effect. It should be noted that in this structure, the gate line area in the embodiment is sequentially provided with the first tunneling layer 161, the first doped polysilicon layer 171, the second tunneling layer 162, the second doped polysilicon layer 172, the back passivation layer 18, the back anti-reflection layer 19, and the back gate line 20 along the thickness direction; and the non-gate line area is sequentially provided with the back passivation layer 18 and the back anti-reflection layer 19 along the thickness direction. The specific type of the back anti-reflection layer 19 is not limited in the embodiment, and the back anti-reflection layer 19 can include, but is not limited to, a silicon nitride layer. It should be noted that the silicon nitride layer is a common material in the prior art, and the embodiment does not limit the internal components of the back anti-reflection layer 19, but directly uses the film layer made of the existing material as the back anti-reflection layer 19.

[0039] The specific ratio of the thickness of the back anti-reflection layer 19 to the thickness of the back passivation layer 18 is not limited in the embodiment, for example, the ratio of the thickness of the back anti-reflection layer 19 to the thickness of the back passivation layer 18 can be 10-30, and the values at both ends are included. The specific thickness of the back passivation layer 18 is not limited in the embodiment, for example, the thickness of the back passivation layer 18 can be 3nm-7nm, and the values at both ends are included. The specific thickness of the back anti-reflection layer 19 is not limited in the embodiment, for example, the thickness of the back anti-reflection layer 19 can be 70nm-90nm, and the values at both ends are included. In order to achieve the best passivation effect, the preferred thickness of the back passivation layer 18 in the embodiment can be 3nm, 4nm, 5nm, 6nm or 7nm. In order to achieve the best anti-reflection effect, it should be noted that the preferred thickness of the back anti-reflection layer 19 in the embodiment can be 70nm, 71nm, 72nm, 73nm, 74nm…88nm, 89nm or 90nm.

[0040] Further, the back gate line 20 in the embodiment can sequentially penetrate the back anti-reflection layer 19, the back passivation layer 18, the second doped polysilicon layer 172, and the second tunneling layer 162 along the thickness direction, and contact the first doped polysilicon layer 171.

[0041] The embodiment is not limited to the specific structure of the front surface of the substrate 11, and the specific structure of the front surface of the substrate 11 can be determined according to the specific type of the solar cell. For example, when the solar cell is a TOPCon cell, the front surface of the substrate 11 can be sequentially provided with an emitter 12 and a front grid line 15 in the thickness direction. The embodiment is not limited to the specific type of the emitter 12, and the specific type of the emitter 12 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the emitter 12 can be a P-type emitter; when the substrate 11 is a P-type substrate, the emitter 12 can be an N-type emitter. The P-type emitter is doped with P-type impurities, and the N-type emitter is doped with N-type impurities. The embodiment is not limited to the specific type of the front grid line 15, and the front grid line 15 can be but is not limited to a metal grid line. It should be noted that metal is a common material in the prior art, and the embodiment is not limited to the internal components of the front grid line 15, but directly uses a metal grid line made of an existing material as the front grid line 15.

[0042] Further, in order to improve the passivation effect, the surface of the emitter 12 away from the substrate 11 can be provided with a front passivation layer 13 in the embodiment, and the front grid line penetrates the front passivation layer 13 in the thickness direction and contacts the emitter 12. The embodiment is not limited to the specific type of the front passivation layer 13, and the front passivation layer 13 can be but is not limited to including an aluminum oxide layer. It should be noted that the aluminum oxide layer is a common material in the prior art, and the embodiment is not limited to the internal components of the front passivation layer 13, but directly uses a film layer made of an existing material as the front passivation layer 13. The embodiment is not limited to the specific thickness of the front passivation layer 13, for example, the thickness of the front passivation layer 13 can be 3nm-7nm, and the values at both ends are included. In order to achieve the best passivation effect, the preferred thickness of the front passivation layer 13 in the embodiment can be 3nm, 4nm, 5nm, 6nm or 7nm.

[0043] Further, in order to reduce light reflection, the surface of the front passivation layer 13 away from the emitter 12 in the embodiment can be provided with a front anti-reflection layer 14; the front gate line 15 penetrates the front anti-reflection layer 14 and the front passivation layer 13 in the thickness direction in turn and is in contact with the emitter 12. It should be noted that the front anti-reflection layer 14 can also provide passivation effect. The embodiment does not limit the specific type of the front anti-reflection layer 14, and the front anti-reflection layer 14 can include, but is not limited to, a silicon nitride layer. It should be noted that the silicon nitride layer is a common material in the prior art, and the embodiment does not limit the internal components of the front anti-reflection layer 14, but directly uses the film layer made of the existing material as the front anti-reflection layer 14. The embodiment does not limit the specific thickness of the front anti-reflection layer 14, for example, the thickness of the front anti-reflection layer 14 can be 70nm-90nm, and the values at both ends are included. In order to achieve the best anti-reflection effect, the preferred thickness of the front anti-reflection layer 14 in the embodiment can be 70nm, 71nm, 72nm, 73nm, 74nm…88nm, 89nm or 90nm.

[0044] Based on the above embodiment, the utility model discloses a two-layer tunneling layer and two-layer doped polysilicon layer along the thickness direction alternate arrangement of the laminated structure are arranged in the gate line area, and by controlling the thickness of the first doped polysilicon layer, and the thickness ratio of the first doped polysilicon layer and the second doped polysilicon layer, the design thicker doped polysilicon layer can effectively block the gate line burn-through doped polysilicon layer to realize tunneling transmission, reduce the damage caused by laser etching in the non-gate line area, improve the doping amount to realize better ohmic contact, thereby effectively reducing the recombination of the carrier in the gate line area, and further improving the fill factor and open-circuit voltage of the battery and reducing the series resistance; At the same time, by not setting the tunneling layer and the doped polysilicon layer in the non-gate line area, the parasitic absorption can be greatly reduced, and the battery efficiency can be improved. In addition, the two-layer tunneling layer and the two-layer doped polysilicon layer along the thickness direction alternate arrangement of the laminated structure can also increase the process window of the screen sintering to form the gate line, so that even if there is a large fluctuation in the process parameters, the doped polysilicon layer can still be avoided to be burned through.

[0045] In order to make the utility model more convenient for understanding, the utility model embodiment provides Figure 1 The comparative experiment of the solar cell shown in the figure and the conventional TOPCon cell, and Figure 1 The comparative experiment of the solar cell shown in the figure under different structure parameters, and the specific process includes:

[0046] 1. A 150nm tandem tunneling cell (where the thickness of the first tunneling layer 161 is between 1.5nm and 2.2nm, and the thickness of the first doped polysilicon layer 171 is between 20nm and 40nm; the thickness of the second tunneling layer 162 is between 0.5nm and 1.2nm, and the thickness of the second doped polysilicon layer 172 is between 110nm and 130nm) and a 150nm monolayer tunneling cell (where the thickness of the tunneling layer is between 1.5nm and 2.2nm, and the thickness of the doped polysilicon layer is between 140nm and 170nm) are respectively used to form locally doped polysilicon layers, and a power factor (PF) is constructed. The finger (polycrystalline silicon finger) structure was verified to obtain the battery's electrical performance parameters. These parameters included conversion efficiency (Eta), open-circuit voltage (Voc), short-circuit current (Isc), fill factor (FF), series resistance (Rs), parallel resistance (Rsh), and reverse current at -10V (Irev10), which were then compared. The results of the PF structure verification of the 150nm single-layer tunneling cell are shown in Table 1, and the results of the PF structure verification of the 150nm stacked tunneling cell are shown in Table 2.

[0047] Table 1 Results of PF structure verification using 150nm monolayer tunneling cells.

[0048]

[0049] Table 2 Results of PF structure verification using 150nm tandem tunneling cells.

[0050]

[0051] Tables 1 and 2 show the control group (cells without a locally doped polysilicon layer, i.e., the tunneling layer and the doped polysilicon layer covering the entire back side of substrate 11) and the experimental group (cells with a locally doped polysilicon layer). Comparing Tables 1 and 2, it can be seen that for 150nm monolayer tunneling cells with a PF structure, compared to cells without a PF structure, Isc increases by 0.108A, FF decreases by 0.64%, RS increases by 0.14mΩ, and the gate line contact is poor. For 150nm tandem tunneling cells with a PF structure, compared to cells without a PF structure, Isc increases by 0.11A, FF decreases by only 0.29%, RS increases by 0.05mΩ, and the gate line contact is better. The data indicate that the tandem tunneling structure has a larger process window for the gate lines, resulting in better gains in Isc, FF, and RS. Therefore, for PF cells, the tandem tunneling structure is superior to the monolayer tunneling structure.

[0052] 2. Forming local doped polysilicon layer respectively in 150nm stack tunneling cell (wherein the thickness of the first tunneling layer 161 is between 1.5nm-2.2nm, the thickness of the first doped polysilicon layer 171 is between 20nm-40nm; the thickness of the second tunneling layer 162 is between 0.5nm-1.2nm, the thickness of the second doped polysilicon layer 172 is between 110nm-130nm) and 120nm stack tunneling cell (wherein the thickness of the first tunneling layer 161 is between 1.5nm-2.2nm, the thickness of the first doped polysilicon layer 171 is between 20nm-40nm; the thickness of the second tunneling layer 162 is between 0.5nm-1.2nm, the thickness of the second doped polysilicon layer 172 is between 80nm-100nm), verifying PF structure to obtain the electrical performance parameters of the cell, and comparing; the results of 120nm stack tunneling cell verifying PF structure are shown in Table 3, and the results of 150nm stack tunneling cell verifying PF structure are shown in Table 4.

[0053] Table 3 Results of 120nm stack tunneling cell verifying PF structure

[0054]

[0055] Table 4 Results of 150nm stack tunneling cell verifying PF structure

[0056]

[0057] The control group in Table 3 and Table 4 is the cell without forming local doped polysilicon layer (i.e. the tunneling layer and the doped polysilicon layer cover the entire back of the substrate 11), and the experimental group is the cell with forming local doped polysilicon layer. It can be seen from the comparison of Table 3 and Table 4 that compared with the cell without PF structure, the cell with 120nm stack tunneling cell PF structure has an increase of 0.061A in Isc, a decrease of 0.62% in FF, an increase of 0.22mΩ in RS, and poor contact in the grid line area; compared with the cell without PF structure, the cell with 150nm stack tunneling cell PF structure has an increase of 0.08A in Isc, a decrease of only 0.31% in FF, an increase of 0.11mΩ in RS, and good contact in the grid line area. According to the data, the process window of the 150nm stack tunneling structure is larger, and the Isc, FF and RS have better benefits, and the 150nm stack tunneling structure is superior to the 120nm stack tunneling structure on the PF cell.

[0058] On the PF structure, the current gain of the 150nm doped polysilicon layer with stack tunneling and single layer tunneling is 80mA-110mA, and the current gain of the 120nm doped polysilicon layer with stack tunneling and single layer tunneling is 50mA-70mA. On the PF structure of the 150nm doped polysilicon layer, the parasitic absorption is reduced more, and the current gain is more obvious.

[0059] The solar cell provided by the utility model is introduced in detail above, and for the general technical personnel in the field, the specific implementation manner and application range will be changed according to the thought of the utility model embodiment, and the above, the content of the specification should not be understood as the limitation of the utility model.

Claims

1. A solar cell, characterized by, The application relates to a substrate, which comprises a back surface provided with a gate line area and a non-gate line area. The gate line area is provided with a back surface gate line and a first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer arranged in sequence along a thickness direction; the back surface gate line penetrates the second doped polysilicon layer and the second tunneling layer in sequence along the thickness direction and is in contact with the first doped polysilicon layer. The ratio of the thickness of the second doped polysilicon layer to the thickness of the first doped polysilicon layer is 2-6.5, including the two ends; the thickness of the first doped polysilicon layer is 20-40 nm, including the two ends. The non-gate line area is not provided with a tunneling layer and a doped polysilicon layer. The thickness of the second doped polysilicon layer is 90-130 nm, including the two ends.

2. The solar cell according to claim 1, characterized in that, The ratio of the thickness of the first tunneling layer to the thickness of the second tunneling layer is 1.25-4.5, including the two ends.

3. The solar cell according to claim 1, characterized in that, The sum of the thickness of the second tunneling layer and the thickness of the first tunneling layer is 2-3.4 nm, including the two ends.

4. The solar cell of claim 1, wherein The thickness of the first tunneling layer is 1.5-2.2 nm, including the two ends.

5. The solar cell of claim 1, wherein The surface of the second doped polysilicon layer away from the second tunneling layer and the non-gate line area are both provided with a back surface passivation layer; the surface of the back surface passivation layer away from the substrate is provided with a back surface anti-reflection layer. The ratio of the thickness of the back surface anti-reflection layer to the thickness of the back surface passivation layer is 10-30, including the two ends.

6. The solar cell according to any one of claims 1 to 5, wherein The thickness of the back surface passivation layer is 3-7 nm, including the two ends.

7. The solar cell according to claim 6, characterized in that The surface of the second doped polysilicon layer away from the second tunneling layer and the non-gate line area are both provided with a back surface passivation layer; the surface of the back surface passivation layer away from the substrate is provided with a back surface anti-reflection layer.

8. The solar cell of claim 6, wherein, The back surface gate line penetrates the back surface anti-reflection layer, the back surface passivation layer, the second doped polysilicon layer and the second tunneling layer in sequence along the thickness direction and is in contact with the first doped polysilicon layer. The front surface of the substrate is provided with an emitter and a front surface gate line in sequence along the thickness direction; the surface of the emitter away from the substrate is provided with a front surface passivation layer; the surface of the front surface passivation layer away from the emitter is provided with a front surface anti-reflection layer; the front surface gate line penetrates the front surface anti-reflection layer and the front surface passivation layer in sequence along the thickness direction and is in contact with the emitter.

9. The solar cell of claim 6, wherein, ​ 10. The solar cell according to any one of claims 1 to 5, wherein ​

Images