Packaged electronic device

Abstract

The utility model relates to a packaged electronic device. A packaged electronic device has a C-type lead frame including a base member and a lateral member extending laterally to the base member. A first die and a second die having a first contact region at the first major surface and a second contact region at the second major surface; first main surfaces of the first die and the second die are attached to a first face of the base portion of the lead frame. The first lead is coupled to the second contact region of the first die and has a first external contact portion. A second lead is coupled to a second contact region of the second die and has a second external contact portion. A package mass extends around the lead frame, the first lead and the second lead, embedded in the first die and the second die, and flush with the base member, a lateral member of the lead frame, and an external contact portion of the leads. Surface mount source-source configurations or drain-drain configurations are formed in a simple and efficient manner using embodiments of the present disclosure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to electronic devices with high heat dissipation comprising a plurality of power transistors. BACKGROUND

[0002] High voltage and / or high current power semiconductor devices are known to be widely used in applications, such as power conversion applications, in which these devices are subjected to high or very high voltage bias, with values even up to 1000-2000 V, and to currents that can be rapidly switched.

[0003] In these devices, specific measures are required for forming the package in order to provide high electrical insulation, suitable separation distances between the leads associated with the gate, source and drain terminals, and high heat dissipation to the outside.

[0004] A longitudinal power semiconductor device (in the case of silicon substrates, a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated-gate bipolar transistor (IGBT)) is formed in a die of semiconductor material (typically silicon, silicon carbide, silicon and gallium nitride (GaN) or gallium nitride only), having a first main surface and a second main surface, opposite to the first main surface, a drain pad extending at the first main surface, a source pad or a gate pad extending at the second main surface.

[0005] The die is attached to an electrically conductive support, called a lead frame, having a drain, a source and a gate for the external connection of the device. To this end, the drain pad is generally attached to a bearing portion of the lead frame, which also has a heat dissipation function; the gate lead and the source lead are coupled to the gate pad and to the source pad, respectively, by means of a bonding wire or a terminal or a clamp. The assembled die / lead frame is encapsulated in a mass of resin or other encapsulation insulating material. The encapsulation insulating material can be molded or laminated.

[0006] The conventional package of a power semiconductor device is generally arranged vertically and comprises pins protruding downward from a single bottom side of the package structure, generally parallelepiped-shaped, to be electrically coupled to a printed circuit board (PCB). A suitable heat sink, typically a metal sheet, is coupled to the package structure, which is also arranged vertically with respect to the printed circuit board.

[0007] In order to obtain a more compact thickness dimension, horizontal packages have been developed, such as surface-mountable devices (SDM), which also allow for double-sided cooling (DSC).

[0008] For example, Italian patent 102018000004782 (corresponding to U.S. Patent No. 10,910,302) describes a dual island package for MOSFET transistors with silicon carbide SiC or silicon Si substrates in a source-source configuration (e.g. with coupling of source regions) or for gallium nitride GaN-based MOSFET transistors in a drain-drain configuration (e.g. with coupling of drain regions).

[0009] The object of the present disclosure is to provide a solution which allows to obtain a single dual island package for MOSFET transistors with silicon carbide SiC or silicon Si substrates in a drain-drain configuration or for gallium nitride GaN-based MOSFET transistors in a source-source configuration. Utility model content

[0010] The object of the present disclosure is to provide a packaged electronic device to at least partially solve the above-mentioned problems existing in the prior art.

[0011] An aspect of the present disclosure provides a packaged electronic device, comprising: a C-leadframe including a base member and a pair of lateral members, the base member having a first face and a second face and the lateral members extending laterally to the base member; a first die and a second die, the first die and the second die each having a first major surface and a second major surface, a first contact region at the first major surface of the first die and the first major surface of the second die, a second contact region at the second major surface of the first die and the second major surface of the second die, the first major surface of the first die and the first major surface of the second die being attached to the first face of the base member; a first lead coupled to the second contact region of the first die and having a first external contact portion; a second lead coupled to the second contact region of the second die and having a second external contact portion; and a package mass surrounding the leadframe, the first lead and the second lead and embedding the first die and the second die, wherein the package mass extends flush with the base member, with the lateral members of the leadframe, and with the first external contact portion of the first lead and the second external contact portion of the second lead, respectively.

[0012] According to one or more embodiments, the second lead is spaced apart from the first lead.

[0013] According to one or more embodiments, the first die is spaced apart from the second die.

[0014] According to one or more embodiments, the package mass forms a first major surface and a second major surface opposite each other, and a first lateral surface, a second lateral surface, a third lateral surface, and a fourth lateral surface, the first lateral surface and the third lateral surface being opposite each other, and the second lateral surface and the fourth lateral surface being opposite each other, the second face of the leadframe is flush with the first major surface of the package mass, the lateral members are respectively flush with the first lateral surface and the third lateral surface of the package mass, and the first external contact portion of the first lead and the second external contact portion of the second lead are respectively flush with the second major surface of the package mass.

[0015] According to one or more embodiments, the first external contact portion of the first lead and the second external contact portion of the second lead are respectively flush with the second lateral surface and the fourth lateral surface of the package mass.

[0016] According to one or more embodiments, the first die and the second die each include a respective third contact region disposed on the second major surface of the first die and the second major surface of the second die, respectively, the apparatus further includes a third lead and a fourth lead, the third lead being coupled to the third contact region of the first die and having a third external contact portion that is flush with the package mass, and the fourth lead being coupled to the third contact region of the second die and having a fourth external contact portion that is flush with the package mass.

[0017] According to one or more embodiments, the first die and the second die are vertical metal-oxide-semiconductor field-effect transistor apparatuses, the first contact regions of the first die and the second die are drain contact regions, the second contact regions of the first die and the second die are source contact regions, and the third contact regions of the first die and the second die are gate contact regions.

[0018] According to one or more embodiments, the first die and the second die are silicon-based metal-oxide-semiconductor field-effect transistor apparatuses or silicon carbide-based metal-oxide-semiconductor field-effect transistor apparatuses.

[0019] According to one or more embodiments, the first die and the second die are planar metal-oxide-semiconductor field-effect transistor apparatuses having respective source contact regions that extend at the second surfaces of the first die and the second die, the first contact regions of the first die and the second die are substrate contact regions, the second contact regions of the first die and the second die are drain contact regions, and the third contact regions of the first die and the second die are gate contact regions, the apparatus further includes a source contact plate coupled to the source contact regions and in electrical contact with the lateral members of the leadframe.

[0020] According to one or more embodiments, the lateral members of the leadframe have recesses facing the first die and the second die and coupled to respective edges of the source contact plate.

[0021] According to one or more embodiments, the first die and the second die are gallium nitride based metal oxide semiconductor field effect transistor devices.

[0022] According to one or more embodiments, the package mass includes a first major surface that is flush with the second face of the leadframe and a second major surface that is flush with the first external contact portion and the second external contact portion, the device further including a C- fin and the fin is in contact with the second face of the leadframe.

[0023] According to one or more embodiments, the packaged electronic device further includes a support having a heat dissipation hole, the support in contact with the package mass.

[0024] Another aspect of the disclosure provides a packaged electronic device, comprising: a C-leadframe including a first extension opposite a second extension, a first surface of the leadframe extending between the first extension and the second extension, the first extension and the second extension each having the first surface transverse to a second surface of the leadframe, the second surface opposite the first surface of the leadframe; a first die coupled to the first surface of the leadframe; a first lead coupled to the first die, the first lead including a first external contact region; a second die coupled to the first surface of the leadframe, the second die spaced apart from the first die; a second lead coupled to the second die, the second lead including a second external contact region; and a package mass on the leadframe, the first external contact region and the second external contact region exposed from the package mass.

[0025] According to one or more embodiments, the leadframe is a drain terminal or a source terminal.

[0026] According to one or more embodiments, the leadframe includes a plurality of recesses, the first extension includes a second surface opposite the first surface, the second extension includes a second surface opposite the first surface, and wherein the plurality of recesses are in the second surfaces of the first extension and the second extension.

[0027] According to one or more embodiments, the first die has a first source plate and the second die has a second source plate, the first source plate and the second source plate in respective recesses of the plurality of recesses of the leadframe.

[0028] Another aspect of the present disclosure provides a packaged electronic device, comprising: a C-type leadframe, comprising: a first recess having a first surface, the leadframe having a second surface opposite the first surface; a first extension transverse to the second surface; and a second extension opposite the first extension and transverse to the second surface, the recess between the first extension and the second extension; a plurality of dies in the first recess and coupled to the first surface of the first recess, each of the plurality of dies being spaced apart from one another; a plurality of leads in the first recess and having external contact regions, each die having a respective lead coupled to the respective die; and a package mass on the leadframe, the external contact regions being exposed from the package mass.

[0029] According to one or more embodiments, each die is a vertical metal oxide semiconductor field effect transistor.

[0030] According to one or more embodiments, each die has an L-shaped gate terminal.

[0031] A surface mount source-source configuration or drain-drain configuration is formed in a simple and efficient manner with embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] For a better understanding of the present disclosure, some embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which:

[0033] FIG. 1A is a simplified circuit diagram of MOSFET transistors connected using a common source topology;

[0034] FIG. 1B is a simplified circuit diagram of MOSFET transistors connected using a common drain topology;

[0035] FIG. 2A is a simplified circuit diagram of n MOSFET transistors connected in parallel by external connections in a common drain topology;

[0036] FIG. 2B is a simplified circuit diagram of n MOSFET transistors connected in parallel by internal connections (islands in the package) in a common drain topology;

[0037] FIG. 3A is a simplified circuit diagram of n MOSFET transistors connected in parallel by external connections in a common source topology;

[0038] FIG. 3B is a simplified circuit diagram of n MOSFET transistors connected in parallel by internal connections (islands in the package) in a common source topology;

[0039] FIG. 4is a simplified cross-sectional view of an example of a MOS transistor that can be used in a common-drain topology;

[0040] FIG. 5 is a top view over the packages of two MOSFET transistors coupled to each other using a common-drain topology.

[0041] FIG. 6 is a bottom view of the package of FIG. 5 ;

[0042] FIG. 7 is a cross-sectional view of the package of FIG. 5 and FIG. 6 ;

[0043] FIG. 8 is a cross-sectional view of the package of FIG. 7 connected to a support and a heat sink after the package of

[0044] FIG. 9 is a simplified cross-sectional view of an example of a MOS transistor that can be used in a common-source topology.

[0045] FIG. 10 is a top view over the packages of two MOSFET transistors coupled to each other using a common-source topology;

[0046] FIG. 11 is a bottom view of the package of FIG. 10 ;

[0047] FIG. 12 is a cross-sectional view of the package of FIG. 10 and FIG. 11 ; and

[0048] FIG. 13 is a cross-sectional view of the package of FIG. 12 connected to a support and a heat sink after the package of DETAILED DESCRIPTION

[0049] The following description refers to the arrangement shown in the drawings; therefore, the terms "above", "below", "upper", "lower", "right", "left", etc., relate to the drawings and are not to be construed as limiting.

[0050] It is known that semiconductor switches need to comply with two requirements:

[0051] be able to block voltage in both directions (voltage blocking bidirectionality); and

[0052] allow current to flow in both directions (current bidirectionality).

[0053] MOSFET transistors meet the second requirement, as they are able to pass current from the drain terminal to the source terminal and vice versa, but only partially meet the first requirement, as they block the forward voltage (BV DSS ) from the drain terminal to the source terminal, but have very little blocking capability in the opposite direction.

[0054] In practical operation, there are generally two topologies for MOSFET transistors: the common-source topology (shown in "back-to-back" in FIG. 1A ) and the common-drain topology (shown in FIG. 1B ).

[0055] The common-source topology is generally preferred for the advantage of simpler gate drive, but the common-drain topology is preferred in some applications, such as in the case of solar micro-inverters using gallium nitride-based transistors or silicon-based devices, where it is necessary to reduce noise and electromagnetic emission, EMI.

[0056] Such a topology can be used, for example, in full-bridge converters or in board-bridge converters, where the MOSFET transistors have low conduction losses. In the full-bridge configuration, in the on state there are two drain-source resistors R DS(on) connected in series with very low voltage drop.

[0057] In particular, for the common-source topology, the main advantages are:

[0058] There is no lower limit to the conduction losses, as it is sufficient to connect in parallel an appropriate number of transistors;

[0059] The number of components is minimal; and

[0060] The high-frequency switching capability in the charge / discharge phase.

[0061] For the common-drain topology, some limitations can be due to:

[0062] The number of dies connected in parallel to obtain the required conduction power loss value;

[0063] The type of technology affects the value of the on-state drain-source resistance R DS(on) ;

[0064] The less favorable form factor; and

[0065] The charge Qrr linked to the intrinsic body-drain diode, which enables the current to also flow in the antiparallel-connected diode when the MOSFET transistor has very high current levels and in reverse conduction.

[0066] When n MOSFETs are connected in parallel, as in FIG. 2AAs shown in the above mentioned, for MOSFET transistors connectable in a common-drain topology, the drain-source R DS(on) decreases linearly to reduce the conduction losses ideally to 0, but the single package makes the arrangement and parallelization process more complex.

[0067] When n MOSFETs are connected in parallel by the double island in each package, as FIG. 2B As shown in the above mentioned, for MOSFET transistors connectable in a common-drain topology, the drain-source R DS(on) decreases linearly to reduce the conduction losses ideally to 0, but the user performs the parallelization very simply.

[0068] In practical operation, by the coupling, the single electronic device 10 comprises two MOSFET transistors 11A, 11B having a single common-drain terminal D, two source terminals S1, S2 and two gate terminals G1, G2.

[0069] In the case of the common-source topology shown in FIG. 3A and FIG. 3B Similar assumptions apply in the case of the common-source topology shown in

[0070] In practical operation, FIG. 3B is shown the parallel coupling by the double island in each packaged device 20. Here, the single single-sub device 20 comprises two MOSFETs 21A, 21B having a single common-source terminal S, two drain terminals D1, D2 and two gate terminals G1, G2.

[0071] For a better understanding of the scope of the present disclosure, FIG. 4 is shown an example of a MOSFET transistor 24 having vertical conduction (for example a N-channel MOSFET transistor, here a charge balance transistor (also known as "superjunction" transistor), usable in a common-drain topology.

[0072] In detail, FIG. 4 The transistor 24 of comprises a substrate 25 having an upper or first surface 25A and a lower or second surface 25B.

[0073] The substrate 25 forms a drain region 26 and is electrically contacted by a drain metal layer 27, which extends onto the bottom surface 25B of the substrate 25 and is coupled to the drain terminal D.

[0074] A source region 28 is formed in the body region 23 and faces the upper surface 25A of the substrate 25. The source region 28 is contacted by a source metal layer 29, which extends onto the upper surface 25A and is coupled to the source terminal S.

[0075] An insulated gate region 30 extends over the upper surface 25A of the substrate 25 and has a respective gate conductive portion 31 coupled to the gate terminal G.

[0076] Other implementation methods are possible, such as in vertical silicon carbide technology, which all have a drain metal layer 27 disposed on a surface (e.g., the lower surface 25B of the substrate 25), a source metal layer 29 disposed on another surface (e.g., the upper surface 25A of the substrate 25), and a gate pad (forming a gate terminal G).

[0077] FIG. 5 to FIG. 7 It shows FIG. 2B The implementation method of the electronic device 10, wherein, for example FIG. 4 MOSFET transistor 24 forms MOSFET transistor 11A and MOSFET transistor 11B. For the sake of simplicity and non-limiting description, the term "for" will be used hereinafter. FIG. 4 The reference numerals in the attached diagram of MOSFET transistor 24 indicate portions of MOSFET transistor 11A and MOSFET transistor 11B.

[0078] Specifically, FIG. 5 to FIG. 7 A surface-mount package device 50 is shown, which includes two MOSFET transistors 11A and 11B. FIG. 7 Only the substrate 25, drain metal layer 27 and source metal layer 29 are shown.

[0079] The structure formed by each substrate 25, a corresponding drain metal layer 27, a corresponding source metal layer 29 and a corresponding gate metallization (not shown) is a die 60.

[0080] As will be described in detail below, the packaging device 50 is embedded in the packaging mass block 51, which is made of resin or other insulating material and completely surrounds the MOSFET transistors 11A and MOSFET transistors 11B except for the external terminals of the packaging device 50. The external terminals extend flush with the packaging mass block 51.

[0081] Generally, the packaging device 50 has a parallelepiped shape, which is formed by two main surfaces 50A and 50B (first main surface 50A and second main surface 50B) with rectangular shapes facing each other, and four lateral surfaces 50C to 50F (first lateral surface 50C, second lateral surface 50D, third lateral surface 50E and fourth lateral surface 50F).

[0082] Two lateral surfaces (first lateral surface 50C and third lateral surface 50E) correspond to the short sides of the rectangular shapes of the main surfaces 50A and 50B, and two transverse surfaces (second lateral surface 50D and fourth lateral surface 50F) correspond to the long sides of the rectangular shapes of the main surfaces 50A and 50B.

[0083] The packaging device 50 comprises a metal support structure (hereinafter also referred to as a leadframe) 52 which is FIG. 2B the drain terminal D; two metal source leads 53 which are FIG. 2B the source terminal S1 and the source terminal S2; and two metal gate leads 54 which are FIG. 2B the gate terminal G1 and the gate terminal G2.

[0084] The leadframe 52 has a C-shaped form with a base side 52A FIG. 5 and two lateral sides or extensions 52B. The two extensions 52B are opposite to each other. The leadframe 52 has a recess between the two extensions 52B.

[0085] The base side 52A of the leadframe 52 has an inner face 58 facing the inner side of the packaging device 50 and an outer face 59 which is flush with the first main surface 50A of the packaging device 50. The two extensions 52B each have an inner surface facing each other. The inner surfaces of the two extensions 52B are transversal to the inner face 58 of the leadframe 52.

[0086] As shown in FIG. 7 , the base side 52A of the leadframe 52 on its inner face 58, the base side 52A is in direct contact with the drain metal layer 27 of the MOSFET transistors 11A, 11B, electrically coupling it. It thus forms a double, unique and common island for connecting the drain regions FIG. 4 of the MOSFET transistors 11A, 11B.

[0087] The lateral sides 52B of the leadframe 52 extend upwardly from the base side 52A to the second main surface 50B, being flush with the first lateral surface 50C and the third lateral surface 50E, at a distance from the MOSFET transistors or first and second dies 11A, 11B.

[0088] In the side view, the source leads 53 have an inverted L-shape and each comprise a source base plate 53A in electrical contact with the respective source metal layer 29 FIG. 4 and a respective source pin 53B monolithically integrated with the respective source base plate 53A. Each source pin 53B extends between the respective source base plate 53A and the second main surface 50B, being flush with the latter.

[0089] Furthermore, each source pin 53B has a lateral end portion FIG. 6 extending flush with the second lateral surface 50D.

[0090] The gate leads 54 have a similar shape as the source leads 53, in the side view an inverted L-shape, and each comprise a gate plate (not visible) and a gate pin 54B.

[0091] The gate plate (not visible) of the gate leads 54 is in electrical contact with a gate pad (not shown) forming a gate terminal G of the MOSFET transistor 24 and arranged on the same side of the MOSFET transistor 24 as the source metal layer 29 laterally. FIG. 2B

[0092] As shown in FIG. 6 , the gate pins 54B, having for example the same (or similar) shape as the source pins 53B, protrude flush with the second main surface 50B of the packaging device 50, next to but spaced apart from the source pins 53B.

[0093] Furthermore, each gate pin 54B has a lateral end portion (not visible) extending flush with the fourth lateral surface 50F. FIG. 5

[0094] In this way, the packaging device 50 implements a surface mount drain-drain configuration in a simple and effective way.

[0095] The packaging device 50 has a wide dissipation surface, as dissipation can occur on both the main surface 50A and the main surface 50B and thus can be used in high power applications.

[0096] By arranging the C-shaped heat sink 55 in contact with the first main surface 50A of the packaging device 50 and with at least the first lateral surface 50C and the third lateral surface 50E, the dissipation capacity of the packaging device 50 can be increased in the way shown in FIG. 8 .

[0097] Furthermore, the packaging device 50 can also dissipate heat at its second main surface 50B.

[0098] In particular, as shown in FIG. 8 , a high heat flow is obtained by forming thermal vias 56 in a support 57 having the same packaging device 50 (e.g. printed circuit board) attached thereto.

[0099] FIG. 9 An example of a MOSFET transistor 70 that can be used in a common source topology is shown, here a planar power MOSFET transistor made by using gallium nitride (GaN) based technology.

[0100] In detail, the MOSFET transistor 70 comprises a semiconductor body 71 having an upper surface 71 A and a lower surface 71 B.

[0101] ​​The semiconductor body 71 includes a substrate 72 (e.g., silicon) defining a lower surface 71B; a gallium nitride (GaN) buffer layer 73 stacked on the substrate 72; a channel layer 74, for example, gallium nitride (GaN), stacked on the buffer layer 73; and a barrier layer 75, for example, aluminum gallium nitride (AlGaN), stacked on the channel layer 74 and defining an upper surface 71A of the semiconductor body 71.

[0102] A gate region 76 of a P-type conductive semiconductor material (e.g., gallium nitride) (p-GaN) extends over a barrier layer 75; a gate contact region 77 of a metal (e.g., TiN / AlCu / TiN) extends over the gate region 76 and is in direct electrical contact with the gate region 76; a source contact region 80 of a metal (e.g., Ti / AlCu / TiN) extends over the barrier layer 75 on a first side of the gate region 76 and is in direct electrical contact with the barrier layer 75; a drain contact region 81 of a metal (e.g., TiN / AlCu / TiN) extends over the barrier layer 75 on a second side of the gate region 76 opposite to the first side and is in direct electrical contact with the barrier layer 75; and an insulating layer 83, such as silicon oxide, extends over the upper surface 71A of the semiconductor body 71 between the gate region 76, the gate contact region 77, the source contact region 80, and the drain contact region 81.

[0103] FIG. 10 to FIG. 12 It shows FIG. 3B The method of implementing the packaging device 20, wherein the MSOFET transistor 21A and the MOSFET transistor 21B are, for example, similar to FIG. 9 A MOSFET transistor 70 is formed. For the sake of simplicity and non-limiting illustration, the following uses [the term] for [the purpose of]... FIG. 9 The reference numerals on the MOSFET transistor 70 indicate portions of MOSFET transistors 21A and 21B.

[0104] Specifically, FIG. 12 A surface mount type package device 90 is shown, including two MOSFET transistors 21A and 21B, wherein only their semiconductor body 71, source contact region 80, drain contact region 81, and post-metallization 85 in contact with the lower surface 71B of the semiconductor body 71 are shown.

[0105] A die 86 is formed by a structure consisting of each semiconductor body 71, a corresponding source contact region 80, a corresponding drain contact region 81, and a corresponding post-metallization 85.

[0106] As will be described in detail below, the packaging device 90 is embedded in a packaging mass 91 of resin or other insulating material, which completely surrounds the MOSFET transistors 21A, 21B, except for the external terminals of the packaging device 90, which extend flush with the packaging mass 91.

[0107] In summary, the packaging device 90 has a parallelepiped shape formed by two main surfaces 90A, 90B opposite each other, has a rectangular shape (first main surface 90A and second main surface 90B) and four lateral surfaces 90C-90F (first lateral surface 90C, second lateral surface 90D, third lateral surface 90E and fourth lateral surface 90F).

[0108] Two lateral surfaces (first lateral surface 90C and third lateral surface 90E) correspond to the short sides of the rectangular shape of the main surfaces 90A, 90B, and two lateral surfaces (second lateral surface 90D and fourth lateral surface 90F) correspond to the long sides of the rectangular shape of the main surfaces 90A, 90B.

[0109] The packaging device 90 comprises a support structure (also referred to herein as a lead frame) 92 of metal, which is FIG. 3B the source terminal S; two drain leads 93 of metal, which are FIG. 3B the drain terminals D1 and D2; and two gate leads of metal, which are FIG. 3B the gate terminals G1, G2.

[0110] The lead frame 92 has a C-shaped form, with a base side 92A and two lateral sides 92B.

[0111] The base side 92A of the lead frame 92 has an inner face 88, which faces the inner side of the packaging device 90, and an outer face 89, which is flush with the first main surface 90A of the packaging device 90.

[0112] As can be seen in FIG. 12 the base side 92A of the lead frame 92 directly contacts, on its inner face 88, the back metallization 85 of the MOSFET transistors 21A and 21B, electrically coupling them.

[0113] The lateral sides 92B of the lead frame 92 extend upward from the base side 92A, flush with the first lateral surface 90C and the third lateral surface 90E, to the second main surface 90B, at a distance from the MOSFET transistors 21A, 21B.

[0114] The lateral sides 92B of the lead frame 92 extend upwards to the second main surface 90B of the packaging device 90 and have respective recesses 98 facing the inner side of the packaging device 90.

[0115] In the side view, the drain leads 93 have an inverted L-shape and each comprise a drain base plate 93A in electrical contact with a respective drain base region 81 FIG. 9 ), and a respective drain pin 93B monolithically integrated with the respective drain base plate 93A. Each drain pin 93B extends flush with the respective drain base plate 93A between the respective drain base plate 93A and the second main surface 90B.

[0116] Furthermore, each drain pin 93B has a lateral end portion FIG. 11 ) which is flush with the second lateral surface 90D.

[0117] The gate leads 94 have a similar shape as the drain leads 93 and each comprise a gate plate (not visible) and a gate pin 94B FIG. 11 ).

[0118] The gate plate (not visible) of the gate leads 94 is in electrical contact with the gate contact region 77 of FIG. 9 and is arranged on the same side of the MOSFET transistor 90 as the drain contact region 81 of FIG. 9 .

[0119] As can be seen in FIG. 11 , the gate pins 94B, which have e.g. the same shape (or a similar shape) as the source pins 93B, protrude flush with the second main surface 90B of the packaging device 90 next to, but spaced apart from, the drain pins 93B.

[0120] Furthermore, each gate pin 94B has a lateral end portion FIG. 10 ) which extends flush with the fourth lateral surface 90F.

[0121] The connection structure of the die 86 further comprises a pair of source plates 99.

[0122] Each source plate 99 is in electrical contact with a respective source contact region 80, protrudes laterally with respect to the respective die 86 and extends with its protruding end into the respective recess 98 of the lateral side 92B of the lead structure 92. The source plate 99 is blocked (e.g. fitted or soldered / brazed) in the respective recess 98.

[0123] In this way, the lead frame 92 and the source plates 99 create a direct electrical connection between the MOSFET transistors 21A, 21B and the substrate 72 and between the substrate 72. The base side 92A of the lead frame 92 is thus the FIG. 3Bthe source terminal S of the packaging device 20 and thus represents a double, unique and common island for connecting the source contact areas 80 of the MOSFET transistors 21A, 21B FIG. 9 ) of the MOSFET transistors 21A, 21B.

[0124] In this way, the packaging device 90 forms a surface mount source-source configuration in a simple and effective way.

[0125] FIG. 10 to FIG. 12 The packaging device 90 also has a high dissipation surface and the dissipation capacity can be increased in the way shown in FIG. 13 by arranging the C-shaped heat sink 95 in contact with the first main surface 90A of the packaging device 90 and with at least the first lateral surface 90C, the third lateral surface 90E.

[0126] Furthermore, FIG. 10 to FIG. 12 The packaging device can also dissipate heat at its second main surface 90B.

[0127] In particular, as shown in FIG. 13 , a high heat flow is obtained by forming heat dissipation holes 96 (e.g. metal pass-through areas) in the support 97, which has the same packaging device 90 (e.g. printed circuit board) attached to it.

[0128] Finally, it is clear that modifications and variants can be made to the packaging electronic devices described and illustrated herein, without thereby departing from the scope of the present disclosure.

[0129] A packaged electronic device (50; 70) includes a C-type leadframe (52; 92) including a base member (52A; 92A) having a first and second face (58, 59; 88, 89) and a pair of lateral members (52B; 92B) extending laterally to the base member; a first die (11A, 60; 21A, 86) and a second die (11B, 60; 21B, 86), the first and second dies each having a first and second major surface, a first contact region (27; 85) at the first major surface of the first and second dies (11A, 11B, 60; 21A, 21B, 86), a second contact region (29; 81) at the second major surface of the first and second dies, the first major surface of the first and second dies attached to the first face (58; 88) of the base member (52A; 92A); a first lead (53; 93) coupled to the second contact region (29; 81) of the first die (11A, 60; 21A, 86) and having a first external contact portion (53B; 93B); a second lead (53; 93) coupled to the second contact region (29; 81) of the second die and having a second external contact portion (53B; 93B); and a package mass (52; 92) surrounding the leadframe (52; 92), the first and second leads (53; 93) and embedded the first and second dies (11A, 11B, 60; 21A, 21B, 86), wherein the package mass (52; 92) extends flush with the base member (52A; 92A) and flush with the lateral members (52B; 92B) of the leadframe (52; 92), with the first external contact portion (53B) of the respective first lead (53) and the second external contact portion (93B) of the second lead (93).

[0130] The second lead (53; 93) is spaced apart from the first lead (53; 93).

[0131] The first die (11A, 60; 21A, 86) is spaced apart from the second die.

[0132] The package mass (52; 92) forms first and second major surfaces (50A, 50B; 90A, 90B) opposite each other and first, second, third, and fourth lateral surfaces (50C-50F; 90C-90F), the first and third lateral surfaces (50C, 50E; 90C; 90E) being opposite each other and the second and fourth lateral surfaces (50D, 50F; 90D, 90F) being opposite each other, the second face (59; 89) of the leadframe (52; 92) is flush with the first major surface (50A; 90A) of the package mass (52; 92), the transverse part (52B; 92B) is flush with the first and third lateral surfaces (50C, 50E; 90C, 90E) of the package mass, respectively, and the first and second external contact portions (53B) of the respective first and second leads (53, 93) are flush with the second major surface (50B; 90B) of the package mass.

[0133] The first and second external contact portions (53B) of the respective first and second leads (53, 93) are also flush with the second and fourth lateral surfaces (50D, 50F; 90D, 90F) of the package mass (52; 92), respectively.

[0134] The first and second dies (11A, 11B, 60; 21A, 21B, 86) each comprise a respective third contact area (G; 77) arranged on the second major surface of the respective first and second dies, the device further comprising third and fourth leads (54; 84), the third lead (54) being coupled to the third contact area (G; 77) of the first die (11A, 60) and having a third external contact portion (54B; 84B) that is flush with the package mass (52; 92), and the fourth lead (54; 84) being coupled to the third contact area (G; 77) of the second die (11B, 60; 21B, 86) and having a fourth external contact portion (54B; 84B) that is flush with the package mass.

[0135] The first and second dies (11A, 11B, 60; 21A, 21N, 86) are vertical MOSFET devices, the first contact areas (27) of the first and second dies are drain contact areas, the second contact areas (29) of the first and second dies are source contact areas, and the third contact areas (G) of the first and second dies are gate contact areas.

[0136] The first and second dies (11A, 11B, 60) are silicon-based or silicon carbide-based MOSFET devices.

[0137] The first and second dies (21A, 21B, 84) are planar MOSFET devices having respective source contact regions (80) extending at the second face of the first and second dies, the first contact regions (72) of the first and second dies are substrate contact regions, the second contact regions (81) of the first and second dies are drain contact regions, the third contact regions (77) of the first and third dies are gate contact regions, the device further comprising a source contact plate (99) coupled to the source contact regions (80) and in electrical contact with the lateral members (52B; 2B) of the leadframe (52; 92).

[0138] The lateral members (52B; 92B) of the leadframe (52; 92) have recesses (98) facing the first and second dies and coupled to respective edges of the source contact plate (99).

[0139] The first and second dies are gallium nitride based MOSFET devices.

[0140] The package mass (52; 92) comprises a first main surface (50A; 90A) flush with the second face (59; 89) of the leadframe (52; 92) and a second main surface (50B; 90B) flush with the first and second external contact portions (53B; 93B), the device further comprising a C-heat sink (55; 95) and the heat sink (55; 95) is in contact with the second face (59; 89) of the leadframe (52; 92).

[0141] The device further comprises a support (57; 97) provided with heat dissipation holes (56; 96), the support (57; 97) being in contact with the package mass.

[0142] According to the present disclosure, a packaged electronic device is provided. In particular, the present disclosure relates to high voltage and / or high power semiconductor devices, including vertical MOSFET transistors (e.g. with silicon carbide (SiC) or silicon (Si) substrate in a drain-drain (i.e. with drain region coupling) configuration or planar MOSFET transistors (e.g. based on gallium nitride (GaN)) in a source-source (i.e. with source region coupling) configuration, configured as surface mount and having dual side cooling.

[0143] A packaged electronic device includes a C-type leadframe including a base member having a first face and a second face and a pair of lateral members extending laterally to the base member, a first die and a second die each having a first major surface and a second major surface, a first contact region at the first major surface of the first die and the first major surface of the second die, a second contact region at the second major surface of the first die and the second major surface of the second die, the first major surface of the first die and the second die attached to the first face of the base member, a first lead coupled to the second contact region of the first die and having a first external contact portion, a second lead coupled to the second contact region of the second die and having a second external contact portion, and a package mass surrounding the leadframe, the first lead, and the second lead and embedded in the first die and the second die, wherein the package mass extends flush with the base member, with the lateral members of the leadframe, and with the first external contact portion of the first lead and the second external contact portion of the second lead, respectively. A method of manufacturing the same is also provided.

[0144] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to adopt concepts of the various patents, applications, and publications to provide yet further embodiments.

[0145] These or other changes can be made to the embodiments in light of the above detailed description. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited to the disclosure.

Claims

1. A packaged electronic device, characterized by including: a C-type leadframe including a base member and a pair of lateral members, the base member having a first face and a second face and the lateral members extending laterally to the base member; first and second dies each having first and second major surfaces, first contact regions at the first major surfaces of the first and second dies, second contact regions at the second major surfaces of the first and second dies, the first major surfaces of the first and second dies being attached to the first face of the base member; a first lead coupled to the second contact region of the first die and having a first external contact portion; a second lead coupled to the second contact region of the second die and having a second external contact portion; and a package mass surrounding the leadframe, the first and second leads, and embedded in the first and second dies, wherein the package mass extends flush with the base member, with the lateral members of the leadframe, and with the first and second external contact portions of the first and second leads, respectively. the second lead is spaced apart from the first lead.

2. The packaged electronic device of claim 1, wherein, the first die is spaced apart from the second die.

3. The packaged electronic device of claim 1, wherein, 4. The packaged electronic device of claim 1, wherein: the package mass forms first and second major surfaces opposite each other, and first, second, third, and fourth lateral surfaces, the first and third lateral surfaces being opposite each other and the second and fourth lateral surfaces being opposite each other, the second face of the leadframe is flush with the first major surface of the package mass, the lateral members are flush with the first and third lateral surfaces of the package mass, respectively, and the first and second external contact portions of the first and second leads are flush with the second major surface of the package mass, respectively. the first and second external contact portions of the first and second leads are flush with the second and fourth lateral surfaces of the package mass, respectively.

5. The packaged electronic device of claim 4, wherein, the first and second dies each include respective third contact regions disposed on the second major surfaces of the first and second dies, respectively, the device further including third and fourth leads, the third lead being coupled to the third contact region of the first die and having a third external contact portion flush with the package mass, and the fourth lead being coupled to the third contact region of the second die and having a fourth external contact portion flush with the package mass.

6. The packaged electronic device of claim 4, wherein, ​ 7. The packaged electronic device of claim 6, wherein, The first and second dies are vertical metal oxide semiconductor field effect transistor devices, the first and second contacts of the first and second dies are drain contacts, the second and third contacts of the first and second dies are source contacts, and the fourth and fifth contacts of the first and second dies are gate contacts.

8. The packaged electronic device of claim 7, wherein, The first and second dies are silicon-based metal oxide semiconductor field effect transistor devices or silicon carbide-based metal oxide semiconductor field effect transistor devices.

9. The packaged electronic device of claim 6, wherein, The first and second dies are planar metal oxide semiconductor field effect transistor devices having respective source contacts extending at the second major surfaces of the first and second dies, the first and second contacts of the first and second dies are substrate contacts, the second and third contacts of the first and second dies are drain contacts, the fourth and fifth contacts of the first and second dies are gate contacts, and the devices further comprise a source contact plate coupled to the source contacts and in electrical contact with the lateral members of the leadframe.

10. The packaged electronic device of claim 9, wherein, The lateral members of the leadframe have recesses facing the first and second dies and coupled to respective edges of the source contact plate.

11. The packaged electronic device of claim 9, wherein, The first and second dies are gallium nitride-based metal oxide semiconductor field effect transistor devices.

12. The packaged electronic device of claim 1, wherein, The package mass comprises a first major surface flush with the second face of the leadframe and a second major surface flush with the first and second external contact portions, the devices further comprising a C-type heat sink and the heat sink is in contact with the second face of the leadframe.

13. The packaged electronic device of claim 12, wherein, Further comprising a support having heat dissipation holes, the support is in contact with the package mass.

14. A packaged electronic device, characterized by Comprising: A C-type leadframe comprising a first extension opposite a second extension, a first surface of the leadframe extending between the first and second extensions, the first and second extensions each having a first surface transverse to a second surface of the leadframe, the second surface opposite the first surface of the leadframe; A first die coupled to the first surface of the leadframe; A first lead coupled to the first die, the first lead comprising a first external contact region; A second die coupled to the first surface of the leadframe, the second die spaced apart from the first die; A second lead coupled to the second die, the second lead comprising a second external contact region; and A package mass on the leadframe, the first and second external contact regions being exposed from the package mass. The leadframe is a drain terminal or a source terminal.

15. The packaged electronic device of claim 14, wherein, ​ 16. The packaged electronic device of claim 14, wherein, The leadframe includes a plurality of recesses, the first extension includes a second surface opposite the first surface, the second extension includes a second surface opposite the first surface, and wherein the plurality of recesses are in the second surfaces of the first extension and the second extension.

17. The packaged electronic device of claim 16, wherein, The first die has a first source plate and the second die has a second source plate, the first source plate and the second source plate being in respective recesses of the plurality of recesses of the leadframe.

18. A packaged electronic device, characterized by Comprising: A C-type leadframe including: A first recess having a first surface, the leadframe having a second surface opposite the first surface; A first extension transverse to the second surface; and A second extension opposite the first extension and transverse to the second surface, the recess between the first extension and the second extension; A plurality of dies in the first recess and coupled to the first surface of the first recess, each of the plurality of dies being spaced apart from one another; A plurality of leads in the first recess and having external contact regions, each die having respective leads coupled to the respective die; and A package mass on the leadframe, the external contact regions being exposed from the package mass.

19. The packaged electronic device of claim 18, wherein, Each die is a vertical metal oxide semiconductor field effect transistor.

20. The packaged electronic device of claim 18, wherein, Each die has an L-type gate terminal.

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