Integrated circuit and hearing aid

Abstract

The present application relates to an integrated circuit and a hearing aid wherein the integrated circuit comprises: a first chip having a first clock source; a second chip having a second clock source; the clock signal frequency provided by the second clock source is different from the clock signal frequency provided by the first clock source; and a first clock switching circuit; the first input end of the first clock switching circuit is connected with a first clock source, and the second input end of the first clock switching circuit is connected with a second clock source. According to the invention, the problem of high power consumption of an integrated circuit is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic communication, and in particular, to integrated circuits and hearing aids. BACKGROUND

[0002] In the design of integrated circuits, as systems become larger and more complex, the application scenarios that need to be faced also become complex. For example, in a system-on-chip designed to access an off-chip Bluetooth communication device, in the related art, the on-chip main chip is usually provided with a built-in oscillator to provide a clock signal, and the Bluetooth chip is externally connected to a passive crystal oscillator to provide another frequency clock signal. The use of different clock systems by different chips will result in large power consumption of the integrated circuit in application scenarios such as the introduction of Bluetooth functionality.

[0003] At present, there is no effective solution to the problem of large power consumption of integrated circuits in the related art. CONTENT OF THE INVENTION

[0004] Embodiments of the present application provide an integrated circuit and a hearing aid to at least solve the problem of large power consumption of integrated circuits in the related art.

[0005] In a first aspect, embodiments of the present application provide an integrated circuit, comprising:

[0006] a first chip having a first clock source;

[0007] a second chip having a second clock source;

[0008] and a first clock switching circuit; a first input end of the first clock switching circuit is connected to the first clock source, a second input end of the first clock switching circuit is connected to the second clock source, and an output end of the first clock switching circuit is connected to a control circuit on the first chip.

[0009] In some embodiments, the integrated circuit further comprises:

[0010] a clock gating circuit; a first end of the clock gating circuit is connected to the second clock source, and a second end of the clock gating circuit is connected to the second input end of the first clock switching circuit.

[0011] In some embodiments, the first chip and the second chip communicate through a general-purpose input / output port.

[0012] In some embodiments, the first chip further comprises a first signal processing circuit;

[0013] a first end of the first signal processing circuit is connected to the output end of the first clock switching circuit, and a second end of the first signal processing circuit is connected to the control circuit.

[0014] In some embodiments, the second chip further comprises a second clock switching circuit;

[0015] The first input end of the second clock switching circuit is connected with the second clock source, the second input end of the second clock switching circuit is connected with the second signal processing circuit on the second chip, and the output end of the second clock switching circuit is connected with the second input end of the first clock switching circuit.

[0016] In some embodiments, the second signal processing circuit comprises a frequency multiplier and a frequency divider;

[0017] The second clock source is further connected with the first end of the frequency multiplier, the second end of the frequency multiplier is connected with the first end of the frequency divider, and the second end of the frequency divider is connected with the second input end of the second clock switching circuit.

[0018] In some embodiments, the first clock switching circuit further comprises a deburring sub-circuit;

[0019] The output end of the first clock switching circuit is connected with the first end of the deburring sub-circuit, and the second end of the deburring sub-circuit is connected with the control circuit.

[0020] In some embodiments, the first clock source is provided by a built-in oscillator on the first chip; and / or, the second clock source is provided by an external crystal oscillator connected with the second chip.

[0021] In some embodiments, the first chip is a system-on-chip; and / or, the second chip is an off-chip Bluetooth chip.

[0022] In a second aspect, the embodiments of the present application provide a hearing aid, which comprises the integrated circuit of the first aspect.

[0023] Compared with the related art, the integrated circuit and the hearing aid provided by the embodiments of the present application comprise: a first chip with a first clock source; a second chip with a second clock source; a clock signal frequency provided by the second clock source is different from a clock signal frequency provided by the first clock source; and a first clock switching circuit; the first input end of the first clock switching circuit is connected with the first clock source, the second input end of the first clock switching circuit is connected with the second clock source, and the output end of the first clock switching circuit is connected with a control circuit on the first chip.

[0024] Based on this, by adding a first clock switching circuit between the first chip and the second chip with different clock sources, clock sharing between multiple chips in the integrated circuit is realized, so that multiple chips can share the same clock in the application scenario of accessing a Bluetooth chip, the integrated circuit power consumption in the application scenario is effectively saved, and the problem of large integrated circuit power consumption is solved.

[0025] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the application. In the drawings:

[0027] Figure 1 is a structural block diagram of an integrated circuit according to an embodiment of the application;

[0028] Figure 2 is a structural block diagram of another integrated circuit according to an embodiment of the application;

[0029] Figure 3 is a circuit schematic diagram of a hearing aid according to an embodiment of the application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0031] It should be noted that the terms "first", "second", "third" involved in the embodiments of the application are only to distinguish similar objects, and do not represent a specific order of the objects. The "first", "second", "third" can be interchanged in a specific order or sequence as appropriate. It can be understood that the objects distinguished by "first", "second", "third" can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The terms "first", "second", "third" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0033] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items. The term "multiple" used herein refers to two or more.

[0035] As described in the background, the prior art has problems such as large chip power consumption when providing a clock signal for an integrated circuit chip, which is not conducive to mass production product design. In many system-on-chip, there is usually one or more fixed frequency clock sources inside the chip to ensure that the system can start normally. When the system-on-chip is connected to an external chip, both have two sets of clock sources with different frequencies, which makes the integrated circuit have large power consumption. Therefore, the integrated circuit in the prior art has room for optimization.

[0036] Based on the above problems, the present embodiment provides an integrated circuit, Figure 1 is a structural block diagram of an integrated circuit according to an embodiment of the present application, like Figure 1As shown, the integrated circuit comprises a first chip 11 having a first clock source 111; a second chip 12 having a second clock source 121; the second clock source 121 provides a clock signal with a frequency different from that of the first clock source 111; and a first clock switching circuit 13; the first input end of the first clock switching circuit 13 is connected to the first clock source 111, the second input end of the first clock switching circuit 13 is connected to the second clock source 121, and the output end of the first clock switching circuit 13 is connected to the control circuit 112 on the first chip 11. Generally, the control circuit 112 on the first chip 11 can be a microcontroller unit (MCU).

[0037] In the embodiment, the controlled end of the first multiplexer, i.e., the selection control end, is set to the first chip 11, for receiving the control signal to determine which input signal will be selected and transmitted to the output end. After the circuit is powered on or reset, the first clock switching circuit 13 is in an initial state, and the multiplexer selects a default clock source as the output. Generally, the first clock source 111 of the first chip 11 is selected as the default clock source, because the first chip 11 is in a normal working state by default. Then, the first clock switching circuit 13 can automatically switch the selection signal to another clock source in response to the control signal of the first chip 11.

[0038] Specifically, when the second chip 12 is connected to the first chip 11, the first clock switching circuit 13 can be controlled by the first chip 11 to perform the switching operation. In this way, the input end signal of the first clock switching circuit 13 is switched from the first clock source 111 to the second clock source 121, so that the clock signal provided to the control circuit 112 on the first chip 11 can be automatically switched from the clock signal of the first clock source 111 to the clock signal of the second clock source 121, thereby completing the clock sharing between the first chip 11 and the second chip 12. It should be understood that, at this time, since the first chip 11 and the second chip 12 share the same set of clock signals of the second clock source 121, the first chip 11 can control the first clock source 111 to stop working, thereby effectively reducing the power consumption of the integrated circuit.

[0039] Similarly, when the first chip 11 detects that the second chip 12 stops working, the input end signal of the first clock switching circuit 13 can be switched from the second clock source 121 back to the first clock source 111, and at this time, the clock signal provided to the control circuit 112 on the first chip 11 can be automatically switched from the clock signal of the second clock source 121 to the clock signal of the first clock source 111.

[0040] The integrated circuit provided by the embodiment of the utility model, through adding the first clock switching circuit 13 between the first chip 11 and the second chip 12 with different clock sources, clock sharing between multiple chips in the integrated circuit is realized, so that multiple chips can share the same clock in the application scene of accessing the Bluetooth chip, the integrated circuit power consumption in the application scene is effectively saved, and the problem of large integrated circuit power consumption is solved.

[0041] In some embodiments, the first chip and the second chip communicate through a General Purpose Input Output (GPIO) port. The first chip can send a clock switching request instruction to the second chip through the GPIO port, and receive a response signal sent by the second chip through the GPIO port in response to the clock switching request instruction. The first clock switching circuit is configured to switch the first clock source or the second clock source in response to the response signal.

[0042] The communication is realized based on the GPIO port to realize clock source switching and sharing between the first chip and the second chip, which can adapt to different application scenarios and changing requirements.

[0043] In some embodiments, please refer to Figure 2 The integrated circuit further includes a clock gating circuit 21, a first end of the clock gating circuit 21 is connected to the second clock source 121, and a second end of the clock gating circuit 21 is connected to a second input end of the first clock switching circuit 13. The clock gating circuit 21 uses a logic unit such as an AND gate or a latch to control the on-off of the clock signal according to an enable signal (EN signal). When the enable signal is valid, the clock signal is allowed to pass through; when the enable signal is invalid, the clock signal is blocked.

[0044] When the clock gating circuit 21 is in the off state, the first clock source 111 is connected to the control circuit 112 through the first clock switching circuit 13; when the clock gating circuit 21 is in the on state, the second clock source 121 is connected to the control circuit 112 through the first clock switching circuit 13.

[0045] For example, when the first chip 11 sends a request for switching clock through the GPIO port, the second chip 12, in response to the received request for switching clock, prepares the second clock source 121 and controls the clock gating circuit 21 connected thereto to be in the on state, and sends a response signal to the first chip 11 through the GPIO port. The first chip 11, in response to the response signal, controls the first clock switching circuit 13 to switch the input signal from the first clock source 111 to the second clock source 121. At this time, the first chip 11 can turn off the first clock source 111. Alternatively, the clock gating circuit 21 can also be controlled by the first chip 11; for example, when the first chip 11 sends a request for switching clock, the clock gating circuit 21 is controlled to be in the on state at the same time, and the second chip 12, in response to the request for switching clock, prepares the second clock source 121.

[0046] Similarly, when the clock of the first chip 11 needs to be switched from the second clock source 121 on the second chip 12 side back to the first clock source 111, the first clock source 111 is turned on by the first chip 11, and the first chip 11 controls the first clock switching circuit 13 to switch the input signal to the clock signal of the first clock source 111, and sends a request for switching clock to the second chip 12 through the GPIO port. The second chip 12, in response to the received request for switching clock, turns off the clock gating circuit 21 so that the clock gating circuit 21 is in the off state; or the first chip 11 turns off the clock gating circuit 21 at the same time as sending the request for switching clock.

[0047] Through the above embodiment, the clock gating circuit 21 is used to adaptively control the on or off of the second clock source 121, so that the second clock source 121 can be dynamically turned on or off as needed, unnecessary clock signal transmission and clock tree switching behavior can be avoided, dynamic power consumption of the integrated circuit can be effectively reduced, and signal quality and stability can be improved.

[0048] In some embodiments, the first chip further comprises a first signal processing circuit; a first end of the first signal processing circuit is connected to an output end of the first clock switching circuit, and a second end of the first signal processing circuit is connected to the control circuit. The first signal processing circuit is used for signal processing of the clock signal transmitted to the control of the first chip.

[0049] The first signal processing circuit can include a first frequency divider. The working principle of the frequency divider is mainly based on the synchronization mechanism of the counter and the clock signal. It receives an input clock signal and uses a counter to count the received input clock pulses. When the counter reaches a predetermined count value, the output signal will change (flip), thereby achieving the function of reducing the input signal frequency to the required frequency. The frequency divider can divide the input signal into a predetermined frequency range and separate it into multiple frequency bands such as low frequency, intermediate frequency, and high frequency. This frequency division function allows signals of different frequency bands to be processed or applied separately to meet the needs of different circuits for signals.

[0050] It can be seen that by the above manner, the clock signal provided and transmitted by the first clock source or the second clock source is subjected to signal processing such as frequency division, and the processed signal is finally transmitted to the control circuit of the first chip, so that the clock signals of the first clock source and the second clock source can adapt to different needs, which is beneficial to improve the signal transmission quality.

[0051] In some embodiments, the second chip further includes a second clock switching circuit.

[0052] In some embodiments, the second chip further includes a second clock switching circuit. Figure 3 is a specific circuit schematic diagram of a hearing aid according to an embodiment of the present application. For better understanding of the present application, please refer to Figure 3 The first input end of the second clock switching circuit is connected to the second clock source, the second input end of the second clock switching circuit is connected to the second signal processing circuit on the second chip, and the output end of the second clock switching circuit is connected to the second input end of the first clock switching circuit. The second signal processing circuit is configured to perform signal processing on the clock signal provided by the second clock source.

[0053] More specifically, the second clock switching circuit includes a second multiplexer. The controlled end of the second multiplexer is set to the second chip. In this embodiment, the input ends of the second multiplexer are respectively connected to the second clock source and the second signal processing circuit of the second clock source, so that the clock signal of the second clock source or the signal output after processing such as frequency adjustment and phase adjustment of the clock signal of the second clock source can be adaptively selected to be shared with the first chip.

[0054] Through the above embodiment, the flexibility and adaptability of the system are improved, so that the system can select the most suitable clock signal according to different needs or conditions.

[0055] In some embodiments, the second signal processing circuit includes a frequency multiplier and a second frequency divider; please refer to Figure 3The second clock source is also connected to the first end of the frequency multiplier, the second end of the frequency multiplier is connected to the first end of the second frequency divider, and the second end of the second frequency divider is connected to the second input end of the second clock switching circuit. Through frequency multiplication and frequency division technology, the frequency of the clock signal can be flexibly adjusted, and the influence of external interference on the system clock signal is reduced to a certain extent because the frequency multiplication and frequency division process can smoothly filter out some high-frequency noise.

[0056] In some embodiments, the first clock switching circuit further comprises a deburring sub-circuit; wherein the output end of the first clock switching circuit is connected to the first end of the deburring sub-circuit, and the second end of the deburring sub-circuit is connected to the control circuit.

[0057] In the clock switching process, due to the asynchronization of switching time or the delay of signal transmission, a short and unstable signal, i.e. burr, may be generated at the output end. These burr signals may have a negative impact on the stability and reliability of the system. Therefore, the deburring sub-circuit is used to eliminate these burr signals and ensure the stability and reliability of the output clock signal.

[0058] In some embodiments, the first clock source is provided by a built-in oscillator on the first chip; wherein the built-in oscillator is usually integrated inside the chip without external connection, improving the integration and reliability of the system, and the generated clock signal is stable and accurate, which can meet the needs of most digital circuits.

[0059] And / or, the second clock source is provided by an external crystal oscillator connected to the second chip. The crystal oscillator uses the piezoelectric effect of quartz crystal to generate a clock signal with stable frequency, which has very high stability and accuracy, and can provide clock signals of various frequencies to meet the needs of different systems. Since it is externally connected outside the chip, it has high flexibility and can be replaced or adjusted as needed.

[0060] In some embodiments, the first chip is a system-on-chip; and / or, the second chip is an off-chip Bluetooth chip. The off-chip Bluetooth chip refers to a Bluetooth functional module chip independent of the main processor (such as a system-on-chip); it integrates all circuits and functions required for Bluetooth communication, and is used to realize short-range wireless communication between devices.

[0061] Optionally, the system-on-chip can be an audio processing system-on-chip. The audio processing system-on-chip, as a chip specially used for audio processing, its functions and components can be completely integrated into a system-on-chip to meet the needs of products such as hearing aids, mobile devices, smart homes or other products that require audio processing capabilities.

[0062] The embodiment also provides a hearing aid, which comprises an integrated circuit as described in any of the above embodiments.

[0063] Specifically, refer to Figure 3 The hearing aid includes a system chip and a Bluetooth chip. The system chip includes a built-in oscillator OSC for providing a first clock source; a first clock signal CLK_A of the first clock source is connected to a first input end of a first clock switching circuit. The Bluetooth chip includes an external crystal oscillator for providing a second clock source; a second clock signal CLK_B of the second clock source is connected to a second input end of the first clock switching circuit through a clock gating circuit on the second chip.

[0064] An output end of the first clock switching circuit is connected to a first frequency divider DIV1, and the first clock signal CLK_A of the first clock source or the second clock signal CLK_B of the second clock source is transmitted to an on-chip peripheral and control circuit MCU1 on the first chip by the first frequency divider DIV1.

[0065] The second chip further includes a frequency multiplier PLL and a second frequency divider DIV2. The second clock signal CLK_B of the second clock source is transmitted to an off-chip peripheral and control circuit MCU2 on the second chip through the frequency multiplier PLL and the second frequency divider DIV2. The second clock source and the second frequency divider DIV2 are further connected to a first input end and a second input end of a second clock switching circuit, respectively, to adaptively select to directly share the second clock source provided by the external crystal of the Bluetooth chip to the system chip or to share the second clock source to the system chip after processing such as frequency multiplication.

[0066] The following will be described in detail Figure 3 The clock sharing process between the hearing aid and the multiple chips of the present application will be described in detail. Taking the Bluetooth scenario as an example, the process includes the following steps:

[0067] Step S1, after the system is powered on, the system chip and the Bluetooth chip are started respectively, and each loads a firmware.

[0068] Step S2, in the case of detecting that the Bluetooth chip is accessed and the firmware is loaded, the system chip sends a clock switching demand through a GPIO port.

[0069] Step S3, after the second clock source of the Bluetooth chip is ready, the clock gating circuit is opened through a BT_CLKO_EN signal, and a response signal is sent to the system chip through the GPIO port.

[0070] Step S4, after receiving the response, the system chip uses the first clock switching circuit to switch the clock source signal provided to the MCU on the system chip from the CLK_A signal to the CLK_B signal.

[0071] Step S5, the system chip turns off the first clock source through the Power Down signal.

[0072] When the system chip needs to switch back to the first clock source from the second clock source on the Bluetooth chip side, the operation steps are as follows:

[0073] Step S6, the system chip turns on the first clock source.

[0074] Step S7, the system chip controls the first clock switching circuit to switch the clock source signal provided to the MCU on the system chip from the CLK_B signal back to the CLK_A signal.

[0075] Step S8, the system chip sends a clock switching instruction through the GPIO port.

[0076] Step S9, after the Bluetooth chip receives the clock switching instruction, the clock gating circuit is turned off.

[0077] Through the above embodiment, the clock sharing design between multiple chips in the hearing aid is realized, and the power consumption of the hearing aid in the Bluetooth scene can be reduced by 100uA.

[0078] It should be further pointed out that the structure shown in the above-mentioned drawings is only an example. Figure 2 For example, the first clock switching circuit can be arranged on the first chip 11 or outside the first chip 11 and the second chip 12; or, Figure 2 The clock gating circuit 21 in the first chip 11 or the second chip 12 can be arranged on the first chip 11 or the second chip 12, or outside the first chip 11 and the second chip 12; or, the first clock switching circuit 13 and the clock gating circuit 21 can be arranged on the same chip.

[0079] Those skilled in the art should understand that the technical features of the above-mentioned embodiments can be combined in any way, and in order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the description.

[0080] The above-mentioned embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the utility model patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An integrated circuit, characterized in that, include: A first chip (11) having a first clock source (111); A second chip (12) having a second clock source (121); And a first clock switching circuit (13); the first input terminal of the first clock switching circuit (13) is connected to the first clock source (111), the second input terminal of the first clock switching circuit (13) is connected to the second clock source (121), and the output terminal of the first clock switching circuit (13) is connected to the control circuit (112) on the first chip (11).

2. The integrated circuit according to claim 1, characterized in that, The integrated circuit also includes: Clock gate circuit (21); the first end of the clock gate circuit (21) is connected to the second clock source (121), and the second end of the clock gate circuit (21) is connected to the second input end of the first clock switching circuit (13).

3. The integrated circuit according to claim 1, characterized in that, The first chip (11) and the second chip (12) communicate with each other through a general-purpose input / output port.

4. The integrated circuit according to claim 1, characterized in that, The first chip (11) also includes a first signal processing circuit; The first end of the first signal processing circuit is connected to the output end of the first clock switching circuit (13), and the second end of the first signal processing circuit is connected to the control circuit (112).

5. The integrated circuit according to claim 1, characterized in that, The second chip (12) also includes a second clock switching circuit; The first input terminal of the second clock switching circuit is connected to the second clock source (121), the second input terminal of the second clock switching circuit is connected to the second signal processing circuit on the second chip (12), and the output terminal of the second clock switching circuit is connected to the second input terminal of the first clock switching circuit (13).

6. The integrated circuit according to claim 5, characterized in that, The second signal processing circuit includes a frequency multiplier and a frequency divider; The second clock source (121) is also connected to the first end of the frequency multiplier, the second end of the frequency multiplier is connected to the first end of the frequency divider, and the second end of the frequency divider is connected to the second input end of the second clock switching circuit.

7. The integrated circuit according to claim 1, characterized in that, The first clock switching circuit (13) also includes a deburring circuit; The output of the first clock switching circuit (13) is connected to the first end of the deburring circuit, and the second end of the deburring circuit is connected to the control circuit (112).

8. The integrated circuit according to any one of claims 1 to 7, characterized in that, The first clock source (111) is provided by a built-in oscillator on the first chip (11); and / or, the second clock source (121) is provided by an external crystal oscillator connected to the second chip (12).

9. The integrated circuit according to any one of claims 1 to 7, characterized in that, The first chip (11) is a system-on-a-chip; and / or, the second chip (12) is an off-chip Bluetooth chip.

10. A hearing aid, characterized in that, The hearing aid includes an integrated circuit as described in any one of claims 1 to 9.

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