Semiconductor device

Abstract

A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending from a substrate, a first gate structure extending across the first semiconductor fin, a second gate structure extending across the second semiconductor fin, and a semiconductor isolation structure. A semiconductor isolation structure is between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin. The semiconductor isolation structure extends parallel to the first and second gate structures from a top view.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Technological advancements in IC materials and design have led to generations of integrated circuits, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. Utility Model Content

[0003] In some embodiments, a semiconductor device includes a first semiconductor fin and a second semiconductor fin extending from a substrate; a first gate structure extending across the first semiconductor fin; a second gate structure extending across the second semiconductor fin; and a semiconductor isolation structure between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin, wherein, in a top view, the semiconductor isolation structure extends parallel to the first and second gate structures.

[0004] In some embodiments, a semiconductor device includes a first semiconductor fin; a second semiconductor fin aligned with the first semiconductor fin; a first gate structure located on the first semiconductor fin; a second gate structure located on the second semiconductor fin; and a semiconductor isolation structure located between the first semiconductor fin and the second semiconductor fin, perpendicular to the first semiconductor fin and the second semiconductor fin.

[0005] In some embodiments, a semiconductor device includes a first semiconductor fin; a second semiconductor fin, a longitudinal axis of which is parallel to a longitudinal axis of the first semiconductor fin; a semiconductor isolation structure located between the first semiconductor fin and the second semiconductor fin, a longitudinal axis of which is perpendicular to the longitudinal axis of the first semiconductor fin; a first gate across the first semiconductor fin; and a second gate across the second semiconductor fin. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure One The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 An example of FinFET is shown in a 3D view;

[0008] Figure 2 , Figure 4A , Figure 5A ,and Figure 10A A cross-sectional view illustrating intermediate stages in the fabrication of a FinFET according to some exemplary embodiments is shown, corresponding to... Figure 1 The reference section AA shown;

[0009] Figure 3 A perspective view illustrating intermediate stages of manufacturing a FinFET according to some exemplary embodiments;

[0010] Figure 4B , Figure 5B , Figures 6-9 ,and Figure 10B A cross-sectional view illustrating intermediate stages in the fabrication of a FinFET according to some exemplary embodiments is shown, corresponding to... Figure 1 The reference section BB shown;

[0011] Figure 5C and Figure 10C A top view illustrating an intermediate stage in the fabrication of a FinFET according to some exemplary embodiments;

[0012] Figures 11-16A A cross-sectional view illustrating intermediate stages in the fabrication of a FinFET according to some exemplary embodiments is shown, corresponding to... Figure 1 The reference section AA shown;

[0013] Figure 16B A top view illustrating an intermediate stage in the fabrication of a FinFET according to some exemplary embodiments is shown.

[0014] [Symbol Explanation]

[0015] 10:Substrate

[0016] 12: Fins

[0017] 14: Quarantine Zone

[0018] 16: Gate dielectric layer

[0019] 18: Gate electrode

[0020] 20 / 22: Source / Drain Region

[0021] 100:Substrate

[0022] 102a: Fin

[0023] 102b: Fin

[0024] 103a: Longitudinal end

[0025] 103b: Longitudinal end

[0026] 104a: fin

[0027] 104b: fin

[0028] 105a: longitudinal end

[0029] 105b: longitudinal end

[0030] 106: isolation region

[0031] 108: sacrificial gate structure

[0032] 108l: lower portion

[0033] 108u: upper portion

[0034] 110: patterned mask

[0035] 112: CPODE isolation structure

[0036] 112l: lower portion

[0037] 112u: upper portion

[0038] 113l: lower sidewall

[0039] 113u: upper sidewall

[0040] 114: gate spacer

[0041] 114l: lower portion

[0042] 114u: upper portion

[0043] 116: source / drain epitaxial structure

[0044] 117: ILD layer

[0045] 118: CESL

[0046] 120: gate structure

[0047] 120l: lower portion

[0048] 120u: upper portion

[0049] 121l: lower sidewall

[0050] 121u: upper sidewall

[0051] 122: gate dielectric layer

[0052] 124: work function metal layer

[0053] 126: fill metal

[0054] 132: protective cap

[0055] GT1-GT2: gate trench

[0056] M1-M2: patterned mask

[0057] O1-O2: opening

[0058] R1: CPODE recess DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present disclosure. For example, in the following description, formation of a first feature over or on a second feature can include embodiments where the first feature is formed directly on the second feature, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be directly in contact. Furthermore, the present disclosure can make reference to a number of units and / or components. As used herein, these terms are intended to refer to structures which perform a given function whether or not such structures are combined into a single component or separated into multiple components. In this sense, reference to structure A combining structure B to form a structure C is meant that structure A and structure B can be combined to form a single structure C, or that structure A and structure B can be separate components which together form structure C.

[0060] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 230 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, "about", "approximately", "substantially", or "essentially" can generally mean within 20% of a given value or range, or within 10% of a given value or range, or within 5% of a given value or range. The numbers given herein are approximations, so that the term "about", "approximately", "substantially", or "essentially" can be inferred even when not explicitly stated. However, those skilled in the art will recognize that the values or ranges mentioned throughout the specification are merely examples and can be reduced as the scale of integrated circuits is reduced.

[0061] As the size scales down, semiconductor devices are placed in closer proximity and at higher densities, resulting in increased coupling effects between adjacent semiconductor devices in adjacent active regions. Adjacent active regions can be adjacent well regions or adjacent standard cells. The increased coupling effects can result in significant noise increase, signal delay, logic errors, and even integrated circuit (IC) failure. Isolating adjacent semiconductor devices (e.g., FinFETs) in adjacent active regions can help prevent the coupling effects, thereby improving IC performance.

[0062] Adjacent semiconductor devices in adjacent active regions can be isolated by an isolation structure aligned with a centerline between the adjacent active regions to reduce coupling effects. In some embodiments, a continuous poly on oxide definition edge (CPODE) region can be used to form the isolation structure. The term "oxide definition" can define an active region located adjacent to the isolation structure. In some embodiments, the isolation structure can include a dummy metal gate structure formed along with a metal gate structure in a subsequent gate replacement process. However, this isolation structure can present certain challenges. The dummy metal gate structure of the isolation structure is in close proximity to a source / drain (S / D) region of an adjacent semiconductor device. During the gate replacement process, particularly during an etch step to remove a sacrificial poly gate, there is a risk of over-etching. This over-etching can cause the dummy metal gate structure to extrude into the S / D region. The risk is increased in the CPODE region at the interface between a shallow trench isolation (STI) region and a gate spacer, increasing the likelihood of dummy metal gate extrusion.

[0063] To address this issue, the disclosure provides, in various embodiments, an additional photolithography step to prevent removal of the dummy poly material in the CPODE region during the gate replacement process. By preserving the dummy poly material in the CPODE region, the problem of dummy metal gate extrusion over the CPODE region is mitigated, thereby improving yield.

[0064] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is illustrated. The FinFET includes fins 12 on a substrate 10 (e.g., a semiconductor substrate). Isolation regions 14 are disposed in the substrate 10, and the fins 12 protrude over and between adjacent isolation regions 14. Although the isolation regions 14 are described / illustrated as separate from the substrate 10, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although the fins 12 are illustrated as being of the same single continuous material as the substrate 10, the fins 12 and / or the substrate 10 may comprise a single material or multiple materials. In this context, fins 12 refer to the portion extending between adjacent isolation regions 14.

[0065] The gate dielectric layer 16 runs along the sidewall of the fin 12 and is above the top surface of the fin 12, and the gate electrode 18 is above the gate dielectric layer 16. The source / drain regions 20 or 22 are disposed on opposite sides of the fin 12 relative to the gate dielectric layer 16 and the gate electrode 18. Figure 1 Further reference cross-sections are illustrated for use in subsequent figures. Cross-section AA is along the longitudinal axis of the gate electrode 18 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 20 / 22 of the FinFET. Cross-section BB is perpendicular to cross-section AA and along the longitudinal axis of the fin 12, and in a direction, for example, between the source / drain regions 20 / 22 of the FinFET. For clarity, these reference cross-sections are referenced in subsequent figures.

[0066] Some of the embodiments discussed herein are described in the context of forming FinFETs using a post-gate process. In other embodiments, a pre-gate process may be used. Similarly, some embodiments are envisioned for use in planar devices, such as planar FETs, nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs), or the like.

[0067] Figures 2-10C Cross-sectional views, perspective views, and top views are shown of intermediate stages in the fabrication of a FinFET according to some exemplary embodiments. Figure 2 , Figure 4A , Figure 5A ,and Figure 10A Draw Figure 1 The reference section AA is shown, except for several fins. Figure 3 A three-dimensional diagram showing multiple fins. Figure 4B , Figure 5B , Figures 6-9 ,and Figure 10B Draw Figure 1 The reference cross-section BB shown is an exception, except for the multiple FinFETs in the adjacent active regions. Figure 5C andFigure 10C A top view of a plurality of FinFETs is depicted. Throughout the various drawings and illustrative embodiments, like reference numerals are used to refer to like elements. It should be understood that additional embodiments for the method can be practiced with Figures 2-10C Additional operations can be provided before, during, and after the illustrated processes and some of the operations described below can be replaced or eliminated. The order of the operations / processes can be interchanged.

[0068] Figure 2 A perspective view of an initial structure is depicted. The initial structure includes a substrate 100. The substrate 100 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 100 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multi-layer substrate or a graded substrate, can also be used. In some embodiments, the semiconductor material of the substrate 100 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0069] Figure 3 is a perspective view depicting the formation of fins 102a, 102b, 104a, 104b and isolation regions 106 between adjacent fins. Figure 4A is a cross-sectional view taken along the A-A section of Figure 3 is a cross-sectional view taken along the B-B section of Figure 4B is a cross-sectional view taken along the B-B section of Figure 3 is a cross-sectional view taken along the B-B section of Figures 3-4B In, fins 102a, 102b, 104a, 104b are formed in substrate 100. In some embodiments, fins 102a, 102b, 104a, 104b can be formed in substrate 100 by etching trenches in substrate 100. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching can be anisotropic.

[0070] The fins can be patterned by any suitable method. For example, the fins 102a, 102b, 104a, and 104b can be patterned using one or more optical lithography processes, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines optical lithography with a self-alignment process, allowing a pattern to be created with, for example, a smaller pitch than is obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) can remain on the fins 102a, 102b, 104a, and 104b.

[0071] In some embodiments, the longitudinal axis of the fin 102a is aligned with the longitudinal axis of the fin 102b, and the longitudinal axis of the fin 104a is aligned with the longitudinal axis of the fin 104b. In some embodiments, the fins 102a and 104a are included in a first well region or a first standard cell, and the fins 102b and 104b are included in a second well region adjacent to the first well region or a second standard cell adjacent to the first standard cell. The longitudinal end 103a of the fin 102a is separated from the longitudinal end 103b of the fin 102b by a portion of the STI region 106, which will be covered by a continuous poly on oxide definition edge (CPODE) structure in subsequent processing extending in a direction perpendicular to the fins 102a, 102b, 104a, and 104b. The longitudinal end 105a of the fin 104a is separated from the longitudinal end 105b of the fin 104b by a portion of the STI region 106, which will be covered by a continuous poly on oxide definition edge (CPODE) structure in subsequent processing.

[0072] Once the fins 102a, 102b, 104a, and 104b are formed, an isolation region 106 is formed over the substrate 100 to laterally surround lower portions of the fins 102a, 102b, 104a, and 104b. In some embodiments, the isolation region 106 is formed of an insulating material, such as silicon oxide, nitride, the like, or combinations thereof. The insulating material can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to transform it into another material, such as an oxide), the like, or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material of the isolation region 106 is silicon oxide formed by a FCVD process. Once the insulating material is formed, an anneal process can be performed. Although the insulating material of the isolation region 106 is illustrated as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown) can first be formed along the surfaces of the substrate 100 and the fins 102a, 102b, 104a, and 104b. Thereafter, a fill material, such as the materials discussed above, can be formed over the liner.

[0073] Once the insulating material of the isolation region 106 is deposited over the fins 102a, 102b, 104a, and 104b, a removal process is applied to the insulating material to remove excess insulating material over the fins 102a, 102b, 104a, and 104b. In some embodiments, a planarization process, such as chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like, can be utilized. The planarization process exposes the fins 102a, 102b, 104a, and 104b such that the top surfaces of the fins 102a, 102b, 104a, and 104b are flush with the insulating material after the planarization process is completed. In embodiments where a mask remains over the fins 102a, 102b, 104a, and 104b, the planarization process can either expose the mask or remove the mask such that the mask or the top surfaces of the fins 102a, 102b, 104a, and 104b, respectively, are flush with the insulating material after the planarization process is completed.

[0074] Subsequently, the insulating material is recessed to form shallow trench isolation (STI) regions 106. The recessing of the insulating material causes the upper portions of the fins 102a, 102b, 104a, and 104b to protrude from between adjacent STI regions 106. Further, the top surfaces of the STI regions 106 can have a planar surface, a convex surface, a concave surface (such as a dished shape), or a combination thereof as shown. The top surfaces of the STI regions 106 can be formed to be planar, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI regions 106, such as an etching process that is selective to the material of the STI regions 106 (e.g., etches the insulating material faster than the semiconductor material of the fins 102a, 102b, 104a, and 104b). For example, the oxide can be removed using, for example, dilute hydrofluoric acid (dHF).

[0075] With respect to Figures 2-3 The process described is just one example of how the fins 102a, 102b, 104a, and 104b can be formed. In some embodiments, the fins 102a, 102b, 104a, and 104b can be formed by epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 100, and a trench can be etched through the dielectric layer to expose the underlying substrate 100. A homoepitaxial structure can be epitaxially grown in the trench, the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fins. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fins. For example, a dielectric layer can be formed over the top surface of the substrate 100, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material that is different from the substrate 100, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid prior and subsequent implantation, although in situ doping can be used together with implantation doping. Figure 3 In some embodiments, the fins 102a, 102b, 104a, and 104b in the substrate 100 can be recessed, and a material that is different from the fins 102a, 102b, 104a, and 104b can be epitaxially grown over the recessed fins 102a, 102b, 104a, and 104b. In such embodiments, the fins include a recessed material and an epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer can be formed over the top surface of the substrate 100, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material that is different from the substrate 100, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid prior and subsequent implantation, although in situ doping can be used together with implantation doping.

[0076] Still further, it can be advantageous to epitaxially grow a material in the NFET regions that is different from the material in the PFETs. In various embodiments, the upper portions of the fins 102a, 102b, 104a, and 104b can be formed of silicon germanium (SiGe) and the epitaxially grown material can be silicon (Si). In some embodiments, the epitaxially grown material can be doped in situ during growth, which can avoid prior and subsequent implantation, although in situ doping can be used together with implantation doping. x Ge 1-xwhere x can range from 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, materials useful for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0077] Although not specifically illustrated, appropriate wells can be formed in the fins 102a, 102b, 104a, and 104b and / or the substrate 100. For example, an n-well can be formed in a PFET region encompassing the fins 102a and 104a in the substrate 100 where p-type devices such as p-type FinFETs are formed, and a p-well can be formed in a NFET region encompassing the fins 102b and 104b in the substrate 100 where n-type devices such as n-type FinFETs are formed.

[0078] In Figure 5A and Figure 5B The sacrificial gate layer is formed over the fins 102a, 102b, 104a, and 104b by, for example, depositing a sacrificial material over the fins 102a, 102b, 104a, and 104b, followed by planarizing the sacrificial material such as by CMP. The sacrificial gate layer can be amorphous silicon, polysilicon (poly-silicon), poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The sacrificial gate layer can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The sacrificial gate layer can be made of other materials that have a high etch selectivity to the etching of isolation regions, such as the STI regions 106. In some embodiments, the sacrificial gate layer can include a semiconductor material such as polysilicon.

[0079] In some embodiments, a patterned mask 110 is formed over the sacrificial gate layer to aid in the patterning. In some embodiments, the patterned mask 110 is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. By using the patterned mask 110 as an etch mask, the sacrificial gate layer is patterned into a plurality of separate sacrificial gate structures 108 extending across channel regions of the fins 102a, 102b, 104a, and 104b, and CPODE isolation structures 112 extending over the isolation regions 106. Thus, the CPODE isolation structures 112 have a semiconductor material such as polysilicon. The sacrificial gate structures 108 and the CPODE isolation structures 112 can have a longitudinal axis that is substantially perpendicular to the longitudinal axes of the fins 102a, 102b, 104a, and 104b.

[0080] Unlike the sacrificial gate structures 108, the CPODE isolation structures 112 serve as isolation structures for isolating adjacent fins (e.g., fins 102a and 102b), and thus do not extend across any of the fins. In some embodiments, the CPODE isolation structures 112 have a bottom surface that is in full contact with the isolation region. In particular, as shown in the top view of FIG. 1 IB, the CPODE isolation structures 112 are located between the longitudinal ends 103a / 103b of the fins 102a / 102b, between the longitudinal ends 105a / 105b of the fins 104a / 104b. In this manner, the CPODE isolation structures 112 can be used to isolate a FinFET formed in the fin 102a / 104a from a FinFET formed in the fin 102b / 104b. Figure 5C

[0081] As shown in FIG. 1 IB, in some embodiments, the sacrificial gate structures 108 and the CPODE isolation structures 112 each have a non-linear sidewall profile. In particular, the CPODE isolation structures 112 have an upper portion 112u and a lower portion 112l that have different cross-sectional profiles, and the sacrificial gate structures 108 each have a lower portion 108l and an upper portion 108u that have different cross-sectional profiles. The lower portions 108l and 112l have a width that decreases as the distance from the substrate 100 increases. The upper portions 108u and 112u have a width that remains substantially constant as the distance from the substrate 100 increases. Figure 5B

[0082] Thus, the CPODE isolation structures 112 have an upper sidewall 113u and a lower sidewall 113l that is angled with respect to the upper sidewall 113u. The non-linear sidewall profile of the sacrificial gate structures 108 and the CPODE isolation structures 112 is primarily due to the anisotropic nature of the etching steps employed during their fabrication. In particular, due to the etching chemistry and conditions, the CPODE isolation structures 112 exhibit a different upper portion 112u and a lower portion 112l. The upper portion 112u extends substantially vertically, as the etching process is more anisotropic in this region, favoring vertical etching over lateral etching. This results in a sidewall profile where the width remains substantially constant as the distance from the substrate 100 increases. In contrast, the lower portion 112l of the CPODE isolation structures 112 experiences a different etching dynamic. As the etching proceeds into the polysilicon material, the etching speed can vary due to factors such as changes in etchant concentration, ion bombardment energy and angle, and the presence of byproducts that can passivate certain surfaces. These factors result in a decrease in the etching speed in the lateral direction, resulting in a decrease in the width of the lower portion 112l as the distance from the substrate 100 increases. This results in a tapered profile, where the lower sidewall 113l is angled with respect to the upper sidewall 113u.

[0083] ​​After the sacrificial gate structure 108 and the CPODE isolation structure 112 are formed, gate spacers 114 are formed on the sidewalls of the sacrificial gate structure 108 and the CPODE isolation structure 112. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 100. The spacer material layer may be a conformal layer subsequently etched back to form the gate spacers 114. By way of example and not limitation, the spacer material may be formed by depositing dielectric material(s) over the sacrificial gate structure 108 and the CPODE isolation structure 112 using suitable deposition processes (such as CVD, subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes). Next, an anisotropic etching process is performed on the deposited dielectric material(s) to expose portions of fins 102a, 102b, 104a, and 104b not covered by the sacrificial gate structure 108 (e.g., in the source / drain regions of fins 102a, 102b, 104a, and 104b). This anisotropic etching process completely removes the portion of the spacer layer 114 directly above the sacrificial gate structure 108 and the CPODE isolation structure 112. The portion of the spacer layer 114 on the sidewalls of the sacrificial gate structure 108 and the CPODE isolation structure 112 is retained, forming a gate sidewall spacer, referred to for simplicity as gate spacer 114.

[0084] In some embodiments, such as Figure 5B As shown, each of the gate spacers 114 has an upper portion 114u and a lower portion 114l that is angled to the upper portion 114u. This is because the gate spacers 114 conform to the nonlinear sidewalls of the sacrificial gate structure 108 and the CPODE isolation structure 112.

[0085] exist Figure 6 In this process, after the formation of the gate spacer 114 is completed, a source / drain epitaxial structure 116 is formed on the source / drain regions of fins 102a, 102b, 104a, and 104b that are not covered by the sacrificial gate structure 108 and the gate spacer 114. In some embodiments, the formation of the source / drain epitaxial structure 116 includes recessing the source / drain regions of fins 102a, 102b, 104a, and 104b, and then epitaxially growing semiconductor material in the recessed source / drain regions of fins 102a, 102b, 104a, and 104b.

[0086] The source / drain regions of the fins 102a, 102b, 104a, and 104b can be recessed using a suitable selective etch process that attacks the semiconductor fins 102a, 102b, 104a, and 104b but attacks the gate spacers 114 and the patterned mask 110 very little. For example, recessing the semiconductor fins 102a, 102b, 104a, and 104b can be performed by dry chemical etching using a plasma source and an etch gas. The plasma source can be inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), or the like, and the etch gas can be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the semiconductor fins 102a, 102b, 104a, and 104b at a faster etch rate than the gate spacers 114 and the mask 110. In some other embodiments, recessing the semiconductor fins 102a, 102b, 104a, and 104b can be performed by wet chemical etching, such as ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the semiconductor fins 102a, 102b, 104a, and 104b at a faster etch rate than the gate spacers 114 and the mask 110. In some other embodiments, recessing the semiconductor fins 102a, 102b, 104a, and 104b can be performed by a combination of dry chemical etching and wet chemical etching.

[0087] Once the recesses are formed in the source / drain regions of the fins 102a, 102b, 104a, and 104b, source / drain epitaxial structures 116 are formed in the source / drain recesses in the fins 102a, 102b, 104a, and 104b by using one or more epitaxial or epi processes that provide one or more epitaxial materials on the semiconductor fins 104. During the epitaxial growth process, the gate spacers 114 confine the one or more epitaxial materials to the source / drain regions in the fins 102a, 102b, 104a, and 104b. In some embodiments, the lattice constant of the epitaxial structures 116 is different from the lattice constant of the semiconductor fins 102a, 102b, 104a, and 104b, such that the channel regions in the fins 102a, 102b, 104a, and 104b and between the epitaxial structures 116 can be subjected to strain or stress of the epitaxial structures 116 to increase carrier mobility of the semiconductor devices and improve device performance. The epitaxial process includes CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial process can use gaseous and / or liquid precursors that interact with the composition of the semiconductor fins 102a, 102b, 104a, and 104b. In some embodiments, the epitaxial structures 116 can have surfaces that protrude from the individual outer surfaces of the fins 102a, 102b, 104a, 104b, and can have facets.

[0088] In some embodiments, the source / drain epitaxial structures 116 can include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structures 116 can be in-situ doped during the epitaxy process by introducing a dopant species, including p-type dopants such as boron or BF2, n-type dopants such as phosphorus or arsenic, and / or other suitable dopants including combinations thereof. If the source / drain epitaxial structures 116 are not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structures 116. In some example embodiments, the source / drain epitaxial structures 116 in n-type transistors include SiP, while the source / drain epitaxial structures in p-type transistors include GeSnB and / or SiGeSnB. In embodiments with different device types, a mask such as a photoresist can be formed over the n-type device regions while exposing the p-type device regions, and p-type epitaxial structures can be formed on the exposed fins 102a, 102b, 104a, and / or 104b in the p-type device regions. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the p-type device regions while exposing the n-type device regions, and n-type epitaxial structures can be formed on the exposed fins 102a, 102b, 104a, and / or 104b in the n-type device regions. The mask can then be removed.

[0089] Once the source / drain epitaxial structures 116 are formed, an anneal process can be performed to activate the p-type dopants or n-type dopants in the source / drain epitaxial structures 116. The anneal process can be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal annealing (MSA) process, or the like.

[0090] Next, a gate dielectric layer 118 is formed over the exposed fins 102a, 102b, 104a, and / or 104b. The gate dielectric layer 118 can be formed by a thermal oxidation process, a plasma oxidation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like. The gate dielectric layer 118 can include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon nitride oxide, silicon oxynitride oxide, silicon oxycarbide oxide, silicon carbonitride oxide, silicon oxycarbide nitride, silicon carbonitride oxide, or other suitable materials. Figure 7In some embodiments, a contact etch stop layer (CESL) 118 is optionally formed prior to forming the ILD layer 117. In some examples, the CESL 118 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable material having a different etch selectivity than the ILD layer 117. The CESL 118 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation process. In some embodiments, the ILD layer 117 includes a material such as tetraethyl orthosilicate (TEOS) oxide, a silicon-free glass, or a silicon-doped oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric material having a different etch selectivity than the CESL. The ILD layer 117 can be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 117 is formed, the wafer can be subjected to a high heat budget process to anneal the ILD layer 117.

[0091] In some examples, after the ILD layer 117 is formed, a planarization process can be performed to remove excess material of the ILD layer 117. For example, the planarization process includes a chemical mechanical polish (CMP) process that removes portions of the ILD layer 117 (and the CESL 118, if present) overlying the sacrificial gate structures 108 and the CPODE isolation structures 112. In some embodiments, the CMP process also removes the patterned mask 110 (as shown in FIG. 1 IB), and exposes the sacrificial gate structures 108 and the CPODE isolation structures 112. Figure 7

[0092] In some examples, after the ILD layer 117 is formed, a planarization process can be performed to remove excess material of the ILD layer 117. For example, the planarization process includes a chemical mechanical polish (CMP) process that removes portions of the ILD layer 117 (and the CESL 118, if present) overlying the sacrificial gate structures 108 and the CPODE isolation structures 112. In some embodiments, the CMP process also removes the patterned mask 110 (as shown in FIG. 1 IB), and exposes the sacrificial gate structures 108 and the CPODE isolation structures 112. Figure 8 ​In some embodiments, a patterned mask layer Ml is formed over the ILD layer 117 to define the location of the target polysilicon regions that will be removed in a subsequent gate replacement process. The patterned mask layer Ml can include an organic material, such as a photoresist material, and can be formed using a spin-on coating process, followed by patterning the photoresist material using a suitable lithography technique to form one or more openings Ol extending through the patterned mask layer Ml to expose the sacrificial gate structures 108, but not the CPODE isolation structures 112. For example, the photoresist material is illuminated (exposed) and developed to remove portions of the photoresist material. In more detail, a photomask (not shown) can be placed over the photoresist material, which can then be exposed to a beam of radiation, which can be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser, or an argon fluoride (ArF) excimer laser. For example, the exposure of the photoresist material can be performed using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to improve resolution and reduce the minimum pitch that can be achieved. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove either the exposed portions or the unexposed portions of the photoresist material, depending on whether a positive resist or a negative resist is used.

[0093] Next, in Figure 9In some embodiments, the patterned mask Ml is removed after the etching process(es) used to form the gate trenches GTl. In some embodiments, the patterned mask Ml is removed using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask Ml is increased until the photoresist mask Ml undergoes thermal decomposition and can be removed. However, any other suitable process can be utilized, such as a wet strip.

[0094] After the etching process(es) used to form the gate trenches GTl are complete, the patterned mask layer Ml is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask Ml is increased until the photoresist mask Ml undergoes thermal decomposition and can be removed. However, any other suitable process can be utilized, such as a wet strip.

[0095] Thereafter, as Figures 10A-10CAs shown, replacement gate structures 120 are formed in the gate trenches GT1, respectively. The gate structures 120 can be final gates for the FinFETs. Each of the final gate structures can be a high-k / metal gate (HKMG) stack, although other compositions are possible. In some embodiments, each of the gate structures 120 forms a gate associated with three sides of a channel region provided by the fins 102a, 102b, 104a, and 104b. In other words, each of the gate structures 120 wraps around the fins 102a, 102b, 104a, and 104b on three sides. In various embodiments, the high-k / metal gate structures 120 include a gate dielectric layer 122 lining the gate trenches GT1, a work function metal layer 124 formed over the gate dielectric layer 122, and a fill metal 126 formed over the work function metal layer 124 and filling the rest of the gate trenches GT1. The gate dielectric layer 122 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. As used and described herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant, e.g., greater than the dielectric constant of thermal silicon oxide (~3.9). The work function metal layer 124 and / or the fill metal layer 126 used within the high-k / metal gate structures 120 can include a metal, a metal alloy, or a metal silicide. Formation of the high-k / metal gate structures 120 can include multiple deposition processes to form the various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate material.

[0096] Because the gate structures 120 are formed in the gate trenches GT1 left by the removed sacrificial gate structures 108, the gate structures 120 inherently have the geometry of the removed sacrificial gate structures 108, so each of the gate structures 108 has a non-linear sidewall profile. For example, each of the gate structures 120 has an upper portion 120u and a lower portion 120l having different cross-sectional profiles. The lower portion 120l has a width that decreases as the distance from the substrate 100 increases. The upper portion 120u maintains a substantially constant width as the distance from the substrate 100 increases. Thus, the gate structures 120 have an upper sidewall 121u and a lower sidewall 121l that is angled from the upper sidewall 121u.

[0097] In some embodiments, the interface layer of the gate dielectric layer 122 can include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 122 can include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 122 can include other high-k dielectrics such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof.

[0098] The work function metal layer 124 can include a work function metal to provide a suitable work function for the high-k / metal gate structure 120. For an n-type FinFET, the work function metal layer 124 can include one or more n-type work function metals (N metals). The n-type work function metals can illustratively include, but are not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 124 can include one or more p-type work function metals (P metals). The p-type work function metals can illustratively include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0099] In some embodiments, the fill metal 126 can illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0100] Figures 11-16BCross-sectional and top views of intermediate stages of fabricating a FinFET are depicted in accordance with some demonstrative embodiments. Figures 11-16A Depicted are cross-sectional and top views of intermediate stages of fabricating a FinFET. Figure 1 Depicted are cross-sectional and top views of intermediate stages of fabricating a FinFET. Figure 16B Depicted are top views of a plurality of FinFETs. In various views and illustrative embodiments, like reference numerals are used to refer to like elements. It will be understood that additional embodiments for the method can be practiced with additional operations before, during, and after those described below, some of which have been described or will be described below. The order of the operations / processing can be interchanged. Figures 11-16B Depicted are cross-sectional and top views of intermediate stages of fabricating a FinFET.

[0101] Figure 11 Depicted are cross-sectional and top views of intermediate stages of fabricating a FinFET. Figure 7 Depicted are cross-sectional and top views of intermediate stages of fabricating a FinFET. For example, the photoresist material is illuminated (exposed) and developed to remove portions of the photoresist material. In more detail, a mask (not shown) can be placed over the photoresist material, which can then be exposed to a beam of radiation, which can be ultraviolet (UV) or excimer laser, such as KrF excimer laser, or ArF excimer laser. For example, the exposure of the photoresist material can be performed using an immersion lithography tool or an extreme ultraviolet light (EUV) tool, to improve resolution and reduce the minimum pitch that can be achieved. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove either the exposed portions or the unexposed portions of the photoresist material, depending on whether a positive or negative resist is used.

[0102] Next, a plurality of dummy gate structures 108 are formed over the CPODE isolation structures 112, as shown in FIG. 1C. The dummy gate structures 108 can be formed using a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process, to deposit a gate material over the CPODE isolation structures 112. The gate material can include a conductive material, such as a metal, a metal alloy, a conductive metal nitride, or a conductive metal silicide. The gate material can be deposited to a thickness of about 1000A to about 5000A. The dummy gate structures 108 can be formed to have a width of about 1000A to about 5000A. Figure 12In the process, with the patterned mask M2 in place, the patterned mask M2 is used as an etching mask to recess the CPODE isolation structure 112 through a selective etch-back process, thereby forming a CPODE recess R1 between the corresponding gate spacers 114. The CPODE isolation structure 112 is recessed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the polysilicon material in the CPODE isolation structure 112 at a faster etching rate than etching other materials (e.g., gate spacers 114 and / or ILD layer 117). In some embodiments, the CPODE recess R1 has a smaller initial height H1 than the CPODE isolation structure 112 (e.g., ...). Figure 11 The depth of the CPODE recess R1 (as shown). In some embodiments, the ratio of the depth of the CPODE recess R1 to the initial height H1 is in the range of about 0.2 to about 0.8. If the ratio of the CPODE recess depth to the initial height of the CPODE is too small (e.g., less than 0.2), the protective cap 132 subsequently formed in the CPODE recess R1 may be too thin to protect the CPODE isolation structure for removal of the sacrificial gate structure 108 during subsequent etching processes. If the ratio of the CPODE recess depth to the initial height of the CPODE is too large (e.g., greater than 0.8), the STI region 106 below the CPODE isolation structure 112 may be unintentionally damaged during the formation of the CPODE recess R1.

[0103] After the etching process for forming the CPODE recess R1 is completed, for example, a plasma ashing process is used to remove the patterned mask layer M2. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M2 is raised until the photoresist mask M2 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be used.

[0104] exist Figure 13 In this process, dielectric layer 130 is deposited using a suitable deposition technique (such as ALD or CVD) to overfill the CPODE trench R1. In some embodiments, dielectric layer 130 comprises a material similar to, but different from, the polysilicon material of the sacrificial gate structure 108, that is similar to ILD layer 117. For example, dielectric layer 130 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or silicon-doped oxides such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials.

[0105] Next, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or similar, can be performed on dielectric layer 130 until the sacrificial gate structure 108 is exposed.Figure 14 The planarization process removes a portion of the dielectric layer 130 outside the CPODE recess Rl while leaving the remaining portion of the dielectric layer 130 in the CPODE recess Rl to serve as a protective cap 132 covering the recessed CPODE isolation structure 112.

[0106] Next, in Figure 15 with the protective cap 132 covering the CPODE isolation structure 112, the exposed sacrificial gate structures 108 are removed by one or more etching processes. This removal creates gate trenches GT2 between the corresponding gate spacers 114. In this embodiment, the removal of the exposed sacrificial gate structures 108 can be achieved without the need for additional patterned photoresist as an etch mask. This is because the protective cap 132 effectively shields the CPODE isolation structure 112 from the etching processes. Without the protective cap 132, the etchant used to remove the polysilicon material of the sacrificial gate structures 108 would also remove the polysilicon material of the CPODE isolation structure 112. This removal would expose the interface region between the STI region 106 and the gate spacers 114, making it more susceptible to damage by the etchant. Such damage can result in unintended etching of the gate spacers 114 around the CPODE isolation structure 112. As a result, when the space left by the removed CPODE isolation structure 112 is filled with dummy metal gates in subsequent processing, it can result in the dummy metal gates being squeezed into the source / drain regions. However, since the etching processes are performed with the protective cap 132 covering the CPODE isolation structure 112, the CPODE isolation structure 112 is still protected from the etchant. This effectively mitigates the risk of unintended etching of the gate spacers 114 around the CPODE isolation structure 112, thereby preventing the dummy metal gate squeeze-out problem.

[0107] Thereafter, as Figures 16A-16B shown, replacement gate structures 120 are formed in the gate trenches GT2, respectively. The gate structures 120 can be the final gates of the FinFETs. Each of the final gate structures can be a high-k / metal gate (HKMG) stack, although other compositions are possible. In some embodiments, each of the gate structures 120 forms a gate associated with three sides of a channel region provided by the fins 102a, 102b, 104a, and 104b. Example materials, formation methods, and other details associated with the replacement gate structures have been discussed previously with respect to FIGS. 1-6, and thus will not be repeated for the sake of brevity. Figures 10A-10C

[0108] ​Based on the above discussion, it can be seen that the present disclosure provides advantages in various embodiments. However, it should be understood that other embodiments can provide additional advantages, not all of which need be realized in every embodiment, and that no particular advantage needs be realized in all embodiments. One advantage is that by preserving dummy poly material in the CPODE region, the problem of dummy metal gate extrusion on the CPODE region is mitigated.

[0109] In some embodiments, a method includes the following steps. A first semiconductor fin and a second semiconductor fin are formed over a substrate. An isolation region is formed laterally surrounding a lower portion of the first semiconductor fin and a lower portion of the second semiconductor fin. A first polysilicon structure is formed across the first semiconductor fin, a second polysilicon structure is formed across the second semiconductor fin, and a third polysilicon structure is formed over the isolation region. The first and second polysilicon structures are removed to form a first gate trench over the first semiconductor fin, a second gate trench over the second semiconductor fin, while leaving the third polysilicon structure over the isolation region. A first gate structure is formed in the first gate trench, and a second gate structure is formed in the second gate trench. In some embodiments, the method further includes recessing the third polysilicon structure prior to removing the first and second polysilicon structures, and forming a protective cap over the recessed third polysilicon structure prior to removing the first and second polysilicon structures. In some embodiments, the first and second polysilicon structures are removed while the protective cap remains over the recessed third polysilicon structure. In some embodiments, the method further includes forming a patterned mask over the third polysilicon structure, and removing the first and second polysilicon structures while the patterned mask remains over the third polysilicon structure. In some embodiments, the third polysilicon structure is between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin. In some embodiments, after the first and second gate structures are formed, the third polysilicon structure remains over the isolation region. In some embodiments, a lower portion of the third polysilicon structure has a different cross-sectional profile than an upper portion of the third polysilicon structure, and the lower portion of the third polysilicon structure has a width that decreases with increasing distance from the substrate. In some embodiments, the method further includes forming a first gate spacer on opposing sidewalls of the first polysilicon structure, forming a second gate spacer on opposing sidewalls of the second polysilicon structure, and forming a third gate spacer on opposing sidewalls of the third polysilicon structure.

[0110] In some embodiments, a method includes the following steps. A first semiconductor fin and a second semiconductor fin are formed over a substrate. A dielectric material is formed between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin. A first sacrificial gate structure is formed across the first semiconductor fin, and a second sacrificial gate structure is formed across the second semiconductor fin. An isolation structure is formed over the dielectric material. The isolation structure has opposing sidewalls between the longitudinal end of the semiconductor fin and the longitudinal end of the second semiconductor fin. A protective cap is formed over the isolation structure. The first sacrificial gate structure is replaced by a first gate structure and the second sacrificial gate structure is replaced by a second gate structure using the protective cap over the isolation structure. In some embodiments, the isolation structure includes the same material as the first sacrificial gate structure. In some embodiments, the isolation structure includes polysilicon. In some embodiments, prior to forming the protective cap, the isolation structure is recessed and the first and second sacrificial gate structures are covered by a patterned mask at the same time the isolation structure is recessed. In some embodiments, forming the protective cap includes recessing the isolation structure to form a recess over the isolation structure, depositing a dielectric layer that overfills the recess, and removing a portion of the dielectric layer outside the recess while leaving another portion of the dielectric layer in the recess.

[0111] In some embodiments, an apparatus includes a first semiconductor fin and a second semiconductor fin extending from a substrate, a first gate structure extending across the first semiconductor fin, a second gate structure extending across the second semiconductor fin, and an isolation structure. The isolation structure is between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin. From a top view, the isolation structure extends parallel to the first and second gate structures and includes a semiconductor material that is different from a conductive material of the first and second gate structures. In some embodiments, polysilicon of the isolation structure has a top surface that is flush with a top surface of the conductive material of the first gate structure. In some embodiments, the apparatus further includes a protective cap on top of the isolation structure, and the protective cap has a top surface that is flush with a top surface of the first gate structure.

[0112] In some embodiments, a semiconductor apparatus includes a first semiconductor fin; a second semiconductor fin aligned with the first semiconductor fin; a first gate structure on the first semiconductor fin; a second gate structure on the second semiconductor fin; and a semiconductor isolation structure between the first semiconductor fin and the second semiconductor fin and perpendicular to the first semiconductor fin and the second semiconductor fin. In some embodiments, the semiconductor isolation structure extends along a direction parallel to the first gate structure. In some embodiments, the semiconductor isolation structure extends along a direction parallel to the second gate structure.

[0113] In some embodiments, a semiconductor device includes a first semiconductor fin; a second semiconductor fin having a longitudinal axis parallel to a longitudinal axis of the first semiconductor fin; a semiconductor isolation structure between the first semiconductor fin and the second semiconductor fin, the semiconductor isolation structure having a longitudinal axis perpendicular to the longitudinal axis of the first semiconductor fin; a first gate across the first semiconductor fin; and a second gate across the second semiconductor fin. In some embodiments, the longitudinal axis of the semiconductor isolation structure is parallel to the longitudinal axis of the first gate. In some embodiments, the semiconductor isolation structure is on a dielectric isolation region.

[0114] The foregoing outlines features of several embodiments so that a thorough comprehension of the disclosure can be attained. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a first semiconductor fin and a second semiconductor fin extending from a substrate; a first gate structure extending across the first semiconductor fin; a second gate structure extending across the second semiconductor fin; and a semiconductor isolation structure between a longitudinal end of the first semiconductor fin and a longitudinal end of the second semiconductor fin, wherein the semiconductor isolation structure extends parallel to the first and second gate structures from a top view.

2. The semiconductor device according to claim 1, wherein wherein the semiconductor isolation structure has a top surface flush with a top surface of the first gate structure.

3. The semiconductor device according to claim 1, wherein Further comprising: a protective cap atop the semiconductor isolation structure.

4. The semiconductor device according to claim 3, wherein wherein the protective cap has a top surface flush with a top surface of the first gate structure.

5. A semiconductor device, characterized by comprising: Comprising: a first semiconductor fin; a second semiconductor fin aligned with the first semiconductor fin; a first gate structure on the first semiconductor fin; a second gate structure on the second semiconductor fin; and a semiconductor isolation structure between the first semiconductor fin and the second semiconductor fin and perpendicular to the first semiconductor fin and the second semiconductor fin.

6. The semiconductor device according to claim 5, wherein wherein the semiconductor isolation structure extends along a direction parallel to the first gate structure.

7. The semiconductor device according to claim 6, wherein wherein the semiconductor isolation structure extends along a direction parallel to the second gate structure.

8. A semiconductor device, characterized by comprising: Comprising: a first semiconductor fin; a second semiconductor fin having a longitudinal axis parallel to a longitudinal axis of the first semiconductor fin; a semiconductor isolation structure between the first semiconductor fin and the second semiconductor fin, the semiconductor isolation structure having a longitudinal axis perpendicular to the longitudinal axis of the first semiconductor fin; a first gate across the first semiconductor fin; and a second gate across the second semiconductor fin.

9. The semiconductor device according to claim 8, wherein wherein the longitudinal axis of the semiconductor isolation structure is parallel to the longitudinal axis of the first gate.

10. The semiconductor device according to claim 8, wherein wherein the semiconductor isolation structure is on a dielectric isolation region.

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