Isolated integrated circuit and common mode transient detection circuit thereof

Abstract

The utility model relates to an isolated integrated circuit and a common mode transient detection circuit thereof. A receiver circuit of an isolated integrated circuit generates an output voltage according to an input voltage of an input node thereof, and includes a common mode transient detection circuit. The common-mode transient detection circuit comprises a current generating circuit, a bias circuit, a warning circuit and a control circuit. The bias circuit is coupled to the input node and the current generating circuit and enables the current generating circuit in response to the change of the input voltage due to the common mode transient event so as to generate the detection current. The warning circuit is coupled to the bias circuit and generates a warning signal according to the detection current. The control circuit is coupled to the warning circuit and selectively shields the output voltage according to the warning signal so as to generate a receiver output signal at an output node of the receiver circuit. The common mode transient detection circuit shields an output voltage affected by a common mode transient event when the common mode transient event occurs to prevent the receiver circuit from outputting a signal having an undesirable voltage level and / or waveform to a post-stage circuit.

Description

Technical Field

[0001] This utility model relates to a common-mode transient detection circuit, and more particularly to a common-mode transient detection circuit applied to isolated integrated circuits. Background Technology

[0002] In the field of isolated gate drivers, events such as common-mode transients (CMTs) are common. CMT events cause voltage spikes to occur at at least one input node. These voltage spikes may cause current to flow into the isolated gate driver, damaging it, or they may affect its operation, resulting in erroneous outputs. Therefore, it is necessary to improve isolated gate drivers to address these problems. Utility Model Content

[0003] One embodiment of this invention is a common-mode transient detection circuit. This common-mode transient detection circuit is applicable to the receiver circuit of an isolated integrated circuit and includes a first current generating circuit, a first bias circuit, a first warning circuit, and a control circuit. The first current generating circuit receives a reference voltage and generates one of a first transient current and a second transient current in response to a level change in the first input voltage at the first input node of the receiver circuit due to a common-mode transient event. The first bias circuit is coupled to the first input node and the first current generating circuit, receives the first input voltage, and enables the first current generating circuit in response to the level change of the first input voltage to generate one of a first detection current and a second detection current based on the first transient current and the second transient current. The first warning circuit is coupled to the first bias circuit at the first node and the second node, receives the first detection current and the second detection current, and generates a first warning signal based on the first detection current and the second detection current. The control circuit is coupled to the first output node of the first warning circuit and the receiver circuit, and is used to receive the first warning signal and the first output voltage generated by the receiver circuit according to the first input voltage, and to selectively block the first output voltage according to the voltage level of the first warning signal, so as to generate a first receiver output signal at the first output node.

[0004] In some embodiments, the first bias circuit includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit is coupled to the first input node, coupled to the first current generating circuit to the third and fourth nodes, coupled to the first warning circuit to the first node, and is used to replicate the first transient current to generate the first detected current flowing sequentially through the fourth node and the first node, wherein the first transient current flows sequentially through the third node and the first input node. The second current mirror circuit is coupled to the first input node, coupled to the first current generating circuit to the fifth and sixth nodes, coupled to the first warning circuit to the second node, and is used to replicate the second transient current to generate the second detected current flowing sequentially through the second node and the sixth node, wherein the second transient current flows sequentially through the first input node and the fifth node.

[0005] In some embodiments, the first current generating circuit includes a first transistor pair and a second transistor pair. The first transistor pair is coupled to the reference voltage, coupled between the power supply voltage and the first current mirror circuit, coupled to the first current mirror circuit at the third and fourth nodes, and biased by the first current mirror circuit to generate the first transient current. The second transistor pair is coupled to the reference voltage, coupled between the ground voltage and the second current mirror circuit, coupled to the second current mirror circuit at the fifth and sixth nodes, and biased by the second current mirror circuit to generate the second transient current. One of the first and second transistor pairs is biased by the corresponding pair in the first and second current mirror circuits in response to a level change in the first input voltage.

[0006] In some embodiments, the first warning circuit includes a first comparison circuit, a second comparison circuit, and a logic gate. The first comparison circuit is coupled to the first current mirror circuit at the first node and is used to compare the first detected current with a first current threshold to generate a first comparison signal. The second comparison circuit is coupled to the second current mirror circuit at the second node and is used to compare the second detected current with a second current threshold to generate a second comparison signal. The logic gate is coupled to the first and second comparison circuits and is used to output the first warning signal based on the first and second comparison signals, wherein when at least one of the first and second comparison signals is an enabled level, the first warning signal is a disabled level, and wherein the control circuit, based on the disabled level of the first warning signal, blocks the first output voltage so that the voltage level of the first receiver output signal is not the same as the voltage level of the first output voltage in real time.

[0007] In some embodiments, the first warning circuit includes a first resistor, a second resistor, a first comparator circuit, a second comparator circuit, and a logic gate. The first resistor is coupled to the first current mirror circuit at the first node. The second resistor is coupled to the second current mirror circuit at the second node. The first comparator circuit is coupled to the first current mirror circuit at the first node and is used to compare the voltage at the first node with a first voltage threshold to generate a first comparison signal. The second comparator circuit is coupled to the second current mirror circuit at the second node and is used to compare the voltage at the second node with a second voltage threshold to generate a second comparison signal. The logic gate is coupled to the first comparison circuit and the second comparison circuit, and is used to output the first warning signal based on the first comparison signal and the second comparison signal. When at least one of the first comparison signal and the second comparison signal is an enable level, the first warning signal is a disable level. The control circuit blocks the first output voltage based on the first warning signal at the disable level, so that the voltage level of the first receiver output signal is not the same as the voltage level of the first output voltage in real time.

[0008] In some embodiments, the control circuit includes a latching circuit, wherein a gate terminal of the latching circuit is coupled to the first warning circuit to receive the first warning signal, a data input terminal of the latching circuit receives the first output voltage, and a data output terminal of the latching circuit is coupled to the first output node to output the first receiver output signal. When the first warning signal at the disable level is input to the gate terminal of the latching circuit, the latching circuit maintains the voltage at the data output terminal unchanged, so that the voltage level of the first receiver output signal is not identical to the voltage level of the first output voltage in real time. When the first warning signal at the enable level is input to the gate terminal of the latching circuit, the latching circuit directly outputs the first output voltage from the data output terminal, so that the voltage level of the first receiver output signal is identical to the voltage level of the first output voltage in real time.

[0009] In some embodiments, the common-mode transient detection circuit further includes a second current generation circuit and a second bias circuit. The second current generation circuit receives the reference voltage and generates one of a third transient current and a fourth transient current in response to a level change in the second input voltage at the second input node of the receiver circuit due to the common-mode transient event. The second bias circuit is coupled to the second input node and the second current generation circuit, receives the second input voltage, and enables the second current generation circuit in response to the level change of the second input voltage to generate one of the third detection current and the fourth detection current.

[0010] In some embodiments, the second bias circuit is coupled to the first warning circuit at the first node and the second node. The first warning circuit is used to generate the first warning signal based on at least one of the first detected current, the second detected current, the third detected current, and the fourth detected current, wherein the first detected current flows from the first bias circuit into the first node, the second detected current flows from the second node into the first bias circuit, the third detected current flows from the second bias circuit into the first node, and the fourth detected current flows from the second node into the second bias circuit.

[0011] In some embodiments, the common-mode transient detection circuit further includes a second warning circuit. The second warning circuit is coupled to the second bias circuit at the third node and the fourth node, for receiving the third detection current and the fourth detection current, and for generating a second warning signal based on the third detection current and the fourth detection current. The control circuit is coupled to the second warning circuit and the second output node of the receiver circuit, for receiving the second warning signal and the second output voltage generated by the receiver circuit based on the second input voltage, and for selectively blocking the first output voltage and the second output voltage based on the voltage levels of the first warning signal and the second warning signal, so as to generate the first receiver output signal and the second receiver output signal at the first output node and the second output node, respectively.

[0012] Another aspect of this utility model is an isolated integrated circuit. This isolated integrated circuit includes a receiver circuit. The receiver circuit includes a signal processing circuit and a common-mode transient detection circuit. The signal processing circuit is coupled to a first input node of the receiver circuit and is used to generate a first output voltage based on a first input voltage at the first input node. The common-mode transient detection circuit is coupled to the first input node, the signal processing circuit, and the first output node of the receiver circuit, and is used to detect a common-mode transient event based on the first input voltage, and to block the first output voltage when the common-mode transient event occurs, thereby generating a first receiver output signal at the first output node. The common-mode transient detection circuit includes a first current generation circuit, a first bias circuit, a first warning circuit, and a control circuit. The first current generation circuit receives a reference voltage and, in response to a level change in the first input voltage due to the common-mode transient event, generates one of a first transient current and a second transient current. The first bias circuit is coupled to the first input node and the first current generating circuit to receive the first input voltage and, in response to a level change in the first input voltage, enable the first current generating circuit to generate one of a first detection current and a second detection current based on the first transient current and the second transient current. The first warning circuit, coupled to the first bias circuit and the first node, receives the first detection current and the second detection current and generates a first warning signal based on the first detection current and the second detection current. The control circuit is coupled to the first warning circuit, the signal processing circuit, and the first output node to receive the first warning signal and the first output voltage and, based on the voltage level of the first warning signal, selectively blocks the first output voltage to generate the first receiver output signal at the first output node.

[0013] In summary, through the common-mode transient detection circuit, the isolated integrated circuit of this invention can shield the output voltage that may be affected by the common-mode transient event when it occurs, thereby preventing the receiver circuit from outputting signals with undesirable voltage levels and / or waveforms to the subsequent circuits of the isolated integrated circuit. Therefore, the isolated integrated circuit of this invention has the advantages of high reliability. Attached Figure Description

[0014] Figure 1 This is a circuit block diagram of an isolated integrated circuit illustrated according to some embodiments of the present invention.

[0015] Figure 2 The present invention is illustrated in a circuit block diagram of a common-mode transient detection circuit according to some embodiments thereof.

[0016] Figure 3AThe diagram shows a common-mode transient detection circuit according to some embodiments of the present invention.

[0017] Figure 3B The diagram shows a common-mode transient detection circuit according to some embodiments of the present invention.

[0018] Figure 4 The following is a circuit block diagram illustrating another common-mode transient detection circuit based on some embodiments of the present invention.

[0019] Figure 5 Illustrations based on some embodiments of the present utility model Figure 4 A circuit diagram of the control circuit.

[0020] Figure 6 The following is a circuit block diagram illustrating yet another common-mode transient detection circuit based on some embodiments of the present invention.

[0021] Figure 7 Illustrations based on some embodiments of the present utility model Figure 6 A circuit diagram of the control circuit. Detailed Implementation

[0022] The following detailed description of embodiments, in conjunction with the accompanying drawings, is provided. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this utility model.

[0023] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0024] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0025] Please see Figure 1 , Figure 1 The following is a circuit block diagram illustrating an isolated integrated circuit 100 according to some embodiments of the present invention. Figure 1 As shown, the isolated integrated circuit 100 includes a transmitter circuit 11, an isolation circuit 13, and a receiver circuit 15. Specifically, the isolated integrated circuit 100 can be implemented using an isolated gate driver.

[0026] In some embodiments, isolation circuit 13 is coupled to the signal output terminal (not shown) of transmitter circuit 11 and to the signal input terminal (not shown) of receiver circuit 15 at input node NIN, serving as an electrical isolation barrier between transmitter circuit 11 and receiver circuit 15. Specifically, isolation circuit 13 can be implemented using capacitors or other insulating components (e.g., transformers).

[0027] Through isolation circuit 13, transmitter circuit 11 and receiver circuit 15 can operate in two different voltage domains. For example, Figure 1 As shown, the transmitter circuit 11 can be biased by the power supply voltage VDD1 and the ground voltage VSS1, while the receiver circuit 15 can be biased by the power supply voltage VDD2 and the ground voltage VSS2. It should be understood that the power supply voltages VDD1 and VDD2 can be different from each other. Similarly, the ground voltages VSS1 and VSS2 can be different from each other.

[0028] In some embodiments, the transmitter circuit 11 can be implemented using various circuits such as logic circuits, oscillators, modulators, and transmitters to convert the input signal (not shown) received by the isolated integrated circuit 100 into a modulated signal (not shown). While serving as an electrical isolation barrier between the transmitter circuit 11 and the receiver circuit 15, the isolation circuit 13 also converts the modulated signal output by the transmitter circuit 11 through, for example, voltage coupling, to generate an input voltage VIN at the input node NIN. Therefore, the receiver circuit 15 can receive the input voltage VIN through the input node NIN.

[0029] In addition, such as Figure 1 As shown, the receiver circuit 15 includes a signal processing circuit 151. The signal processing circuit 151 of the receiver circuit 15 can be implemented using various circuits such as logic circuits, demodulators, and receivers. With this configuration, the receiver circuit 15 can demodulate the input voltage VIN using the signal processing circuit 151 to generate an output voltage VOUT. Therefore, it can be seen that the signal processing circuit 151 generates the output voltage VOUT based on the input voltage VIN.

[0030] In some embodiments, common-mode transient (CMT) events may occur in the isolated integrated circuit 100. When a CMT event occurs, the voltage level of the input voltage VIN at the input node NIN may increase or decrease sharply. In some practical applications, the drastic change in the input voltage VIN due to the CMT event may affect the operation of the signal processing circuit 151 in generating the output voltage VOUT, resulting in a suboptimal voltage level and / or waveform for the output voltage VOUT. Therefore, Figure 1The isolated integrated circuit 100 employs a common-mode transient detection circuit 200 to handle these situations.

[0031] In some embodiments, the common-mode transient detection circuit 200 is configured in the receiver circuit 15 of the isolated integrated circuit 100. For example... Figure 1 As shown, the common-mode transient detection circuit 200 is coupled to the input node NIN, the signal processing circuit 151, and the output node NOUT of the receiver circuit 15. The common-mode transient detection circuit 200 is used to detect CMT events based on the input voltage VIN and to mask the output voltage VOUT when a CMT event occurs. For example, the common-mode transient detection circuit 200 can maintain the voltage level of the output voltage VOUT at the state before the CMT event. In another example, the common-mode transient detection circuit 200 can replace the output voltage VOUT at the time of the CMT event with a blank signal (not shown) as the output of the receiver circuit 15. In this way, the receiver circuit 15 can avoid transmitting the output voltage VOUT, which has an undesirable voltage level and / or waveform due to the CMT event, to the subsequent circuitry (not shown) of the isolated integrated circuit 100. It should be understood that the output node NOUT of the receiver circuit 15 can also be considered as the signal output terminal of the isolated integrated circuit 100 for coupling to subsequent circuitry.

[0032] Next, the pairing Figure 2 and Figures 3A-3B Further explanation of the common-mode transient detection circuit 200. Figure 2 The following is a circuit block diagram illustrating a common-mode transient detection circuit 200 according to some embodiments of the present invention. In some embodiments, the common-mode transient detection circuit 200 includes a bias circuit 21, a current generation circuit 23, an alarm circuit 25, and a control circuit 27. The bias circuit 21 is coupled to the input node NIN of the receiver circuit 15. The current generation circuit 23 is coupled to the bias circuit 21 and is used to receive a reference voltage VREF. The alarm circuit 25 is coupled to the bias circuit 21, for example, coupled to the bias circuit 21 at nodes NA and NB. The control circuit 27 is coupled to the alarm circuit 25 and the output node NOUT, and is coupled to the signal processing circuit 151 to receive the output voltage VOUT.

[0033] Figure 3A and Figure 3BThis is a circuit diagram illustrating a common-mode transient detection circuit 200 during a CMT event, according to some embodiments of the present invention. In some embodiments, the bias circuit 21 includes current mirror circuits 211 and 212. The current mirror circuit 211 consists of transistors MPU1 and MPU2. The first terminal (e.g., the source terminal) of transistor MPU1 is coupled to the current generating circuit 23 at node N1, while the second terminal (e.g., the drain terminal) of transistor MPU1 is coupled to the input node NIN and the control terminal (e.g., the gate terminal) of transistor MPU1. The first terminal of transistor MPU2 is coupled to the current generating circuit 23 at node N2, the second terminal of transistor MPU2 is coupled to the warning circuit 25 at node NA, and the control terminal of transistor MPU2 is coupled to the control terminal of transistor MPU1, the second terminal of transistor MPU1, and the input node NIN. Thus, the current mirror circuit 211 is coupled to the input node NIN, coupled to the current generating circuit 23 at nodes N1 and N2, and coupled to the warning circuit 25 at node NA.

[0034] As described above, the current mirror circuit 212 consists of transistors MNL1 and MNL2. The first terminal of transistor MNL1 is coupled to the current generating circuit 23 at node N3, while the second terminal of transistor MNL1 is coupled to the input node NIN and the control terminal of transistor MNL1. The first terminal of transistor MNL2 is coupled to the current generating circuit 23 at node N4, the second terminal of transistor MNL2 is coupled to the warning circuit 25 at node NB, and the control terminal of transistor MNL2 is coupled to the control terminal of transistor MNL1, the second terminal of transistor MNL1, and the input node NIN. Therefore, the current mirror circuit 212 is coupled to the input node NIN, coupled to the current generating circuit 23 at nodes N3 and N4, and coupled to the warning circuit 25 at node NB.

[0035] In the above embodiments, transistors MPU1 and MPU2 in the bias circuit 21 can each be implemented using a P-type metal-oxide-semiconductor transistor, while transistors MNL1 and MNL2 in the bias circuit 21 can each be implemented using an N-type metal-oxide-semiconductor transistor. However, this invention is not limited thereto.

[0036] In some embodiments, the current generating circuit 23 includes a transistor pair 231 and another transistor pair 232. Transistor pair 231 includes transistors MNU1 and MNU2. A first terminal of transistor MNU1 is coupled to node N1, and a second terminal of transistor MNU1 is coupled to a power supply voltage (e.g., ...). Figure 1The power supply voltage is VDD2), and the control terminal of transistor MNU1 is coupled to the reference voltage VREF. The first terminal of transistor MNU2 is coupled to node N2, the second terminal of transistor MNU2 is coupled to the aforementioned power supply voltage, and the control terminal of transistor MNU2 is coupled to the reference voltage VREF. Therefore, transistor pair 231 is coupled between the reference voltage VREF and the current mirror circuit 211, wherein transistor pair 231 and the current mirror circuit 211 are coupled to nodes N1 and N2.

[0037] As described above, transistor pair 232 includes transistors MPL1 and MPL2. The first terminal of transistor MPL1 is coupled to node N3, and the second terminal of transistor MPL1 is coupled to ground (e.g., ...). Figure 1 The ground voltage VSS2 is used as the reference voltage, while the control terminal of transistor MPL1 is coupled to the reference voltage VREF. The first terminal of transistor MPL2 is coupled to node N4, the second terminal of transistor MPL2 is coupled to the aforementioned ground voltage, and the control terminal of transistor MPL2 is coupled to the reference voltage VREF. Therefore, transistor pair 232 is coupled between the reference voltage VREF and the current mirror circuit 212, wherein transistor pair 232 and the current mirror circuit 212 are coupled to nodes N3 and N4.

[0038] In the above embodiments, transistors MNU1 and MNU2 in the current generating circuit 23 can each be implemented using N-type metal-oxide-semiconductor transistors, while transistors MPL1 and MPL2 in the current generating circuit 23 can each be implemented using P-type metal-oxide-semiconductor transistors. However, this invention is not limited thereto.

[0039] In some embodiments, the warning circuit 25 includes resistors RA and RB, comparator circuits 251 and 252, and a logic gate 253. Resistor RA is coupled to node NA and the aforementioned ground voltage, while resistor RB is coupled to node NB and the aforementioned power supply voltage. The input of comparator circuit 251 is coupled to node NA, and the output of comparator circuit 251 is coupled to the first input of logic gate 253. The input of comparator circuit 252 is coupled to node NB, and the output of comparator circuit 252 is coupled to the second input of logic gate 253. The output of logic gate 253 is coupled to control circuit 27.

[0040] In the above embodiments, the comparator circuit 251 can be implemented by a non-inverting Schmitt trigger, the comparator circuit 252 can be implemented by an inverting Schmitt trigger, and the logic gate 253 can be implemented by an inverse OR (NOR) gate. However, the present invention is not limited thereto.

[0041] In some embodiments, the control circuit 27 includes a latching circuit 271. The data input terminal D of the latching circuit 271 is coupled to... Figure 1The signal processing circuit 151 receives the output voltage VOUT. The gate terminal of the latch circuit 271 (in...) Figure 3A and Figure 3B The output terminal (represented by the symbol ">") is coupled to the output terminal of logic gate 253. The data output terminal Q of latch circuit 271 is coupled to the output node NOUT. Specifically, latch circuit 271 can be implemented by circuits such as SR latch circuit and gated D latch circuit.

[0042] At Figure 3A In this embodiment, it is assumed that the input voltage VIN at the input node NIN drops sharply due to a CMT event. In this case, transistors MPU1 and MPU2 both switch to the ON state, while transistors MNL1 and MNL2 remain in the OFF state. Furthermore, transistor MPU1 biases node N1 according to the input voltage VIN and its gate-source voltage, causing transistor MNU1 to switch to the ON state; simultaneously, transistor MPU2 biases node N2 according to the input voltage VIN and its gate-source voltage, causing transistor MNU2 to switch to the ON state. Based on the ON state of transistors MPU1 and MNU1, transistor MNU1 generates a transient current I1, which flows sequentially through transistor MNU1, node N1, transistor MPU1, and input node NIN. In other words, transistor pair 231 is biased by the current mirror circuit 211, causing the transient current I1 to be generated. Next, the current mirror circuit 211 replicates the transient current I1 to generate a detection current IA that flows sequentially through transistor MNU2, node N2, transistor MPU2, and node NA.

[0043] As described above, the detected current IA flows from node NA into resistor RA, causing an increase in the input voltage (not shown) of comparator circuit 251. When the input voltage of comparator circuit 251 increases to a level greater than its upper voltage threshold (not shown), comparator circuit 251 outputs a comparator signal SC1 with an enable level (e.g., logic "1"). Logic gate 253 performs an inverse OR operation on the comparator signal SC1 with the enable level and outputs a warning signal SOC with a disable level (e.g., logic "0"). Then, since the warning signal SOC with the disable level is input to the gate of latch circuit 271, latch circuit 271 maintains the voltage at data output terminal Q unchanged. For example, if latch circuit 271 outputs an enable level output voltage VOUT as the receiver output signal SOUT just before the CMT event occurs, then the receiver output signal SOUT output by latch circuit 271 at the time of the CMT event will still be at the enable level (even if the output voltage VOUT has switched to the disable level at this time). It should be understood that the input voltage of comparator circuit 251 can also be regarded as the voltage at node NA.

[0044] At Figure 3B In this embodiment, it is assumed that the input voltage VIN at the input node NIN increases sharply due to a CMT event. In this case, transistors MNL1 and MNL2 both switch to the ON state, while transistors MPU1 and MPU2 remain in the OFF state. Furthermore, transistor MNL1 biases node N3 according to the input voltage VIN and its gate-source voltage, causing transistor MPL1 to switch to the ON state; simultaneously, transistor MNL2 biases node N4 according to the input voltage VIN and its gate-source voltage, causing transistor MPL2 to switch to the ON state. Based on the ON state of transistors MNL1 and MPL1, transistor MPL1 generates a transient current I2, which flows sequentially through the input node NIN, transistor MNL1, node N3, and transistor MPL1. In other words, transistor pair 232 is biased by the current mirror circuit 212, causing the transient current I2 to be generated. Next, the current mirror circuit 212 replicates the transient current I2 to generate a detection current IB that flows sequentially through node NB, transistor MNL2, node N4, and transistor MPL2.

[0045] As described above, the detection current IB flows out of resistor RB and into node NB, causing a decrease in the input voltage (not shown) of comparator circuit 252. When the input voltage of comparator circuit 252 decreases to below its lower limit voltage threshold (not shown), comparator circuit 252 outputs an enable signal SC2. Logic gate 253 performs an inverse OR operation on the enable signal SC2 to output a disable warning signal SOC. Then, since the disable warning signal SOC is input to the gate of latch circuit 271, latch circuit 271 maintains a constant voltage at data output terminal Q, similar to... Figure 3A Description of latch circuit 271 in the embodiment. It should be understood that the input voltage of comparator circuit 252 can also be regarded as the voltage at node NB.

[0046] In some embodiments, no CMT event occurs in the isolated integrated circuit 100. Figure 3A and Figure 3BThe common-mode transient detection circuit 200, through the configuration of the reference voltage VREF and the bias circuit 21, ensures that transistors MNU1, MNU2, MPL1, and MPL2 are all in the off state, i.e., the current generation circuit 23 is disabled. This further ensures that the bias circuit 21 will not output the detection current IA (or detection current IB). Therefore, the input voltage of the comparator circuit 251 (which is equivalent to the ground voltage VSS2) will be less than the lower threshold voltage of the comparator circuit 251 (not shown in the figure), causing the comparator circuit 251 to output a comparator signal SC1 at the disabled level. It should be understood that the upper threshold voltage of the comparator circuit 251 is greater than the lower threshold voltage of the comparator circuit 251. Furthermore, the input voltage of the comparator circuit 252 (which is equivalent to the power supply voltage VDD2) will be greater than the upper threshold voltage of the comparator circuit 252 (not shown in the figure), causing the comparator circuit 252 to output a comparator signal SC2 at the disabled level. It should be understood that the upper threshold voltage of the comparator circuit 252 is greater than the lower threshold voltage of the comparator circuit 252. Next, the logic gate 253 performs an inverse OR operation on the comparison signals SC1 and SC2 of the disable level to output the warning signal SOC of the enable level.

[0047] As described above, since the alarm signal SOC of the enable level is input to the gate terminal of the latch circuit 271, the latch circuit 271 directly outputs the output voltage VOUT generated by the signal processing circuit 151 from the data output terminal Q. In other words, when no CMT event occurs in the isolated integrated circuit 100, the control circuit 27 does not perform any processing on the output voltage VOUT (e.g., masking) and directly transmits the output voltage VOUT to the output node NOUT as the output of the receiver circuit 15, i.e., as the receiver output signal SOUT. In short, when no CMT event occurs in the isolated integrated circuit 100, the common-mode transient detection circuit 200 does not change or affect the normal operation of the receiver circuit 15 in the isolated integrated circuit 100 (i.e., the operation of the signal processing circuit 151).

[0048] As described in the above embodiments, in some embodiments, the bias circuit 21 is used to enable the current generating circuit 23 in response to a level change in the input voltage VIN due to a CMT event, i.e., switching transistors MNU1 and MNU2 (or transistors MPL1 and MPL2) to the on state, thereby generating a transient current I1 (or transient current I2). The current generating circuit 23 is used to generate a transient current I1 (or transient current I2) in response to a level change in the input voltage VIN due to a CMT event, causing the bias circuit 21 to generate a detection current IA (or detection current IB). The warning circuit 25 is used to generate a warning signal SOC based on the detection current IA (or detection current IB). The control circuit 27 is used to selectively block the output voltage VOUT based on the voltage level (i.e., the disable level or the enable level) of the warning signal SOC, thereby generating a receiver output signal SOUT at the output node NOUT.

[0049] As further explained above, when the warning signal SOC is at the enabled level (indicating that no CMT event has occurred in the isolated integrated circuit 100), the voltage level of the receiver output signal SOUT and the voltage level of the output voltage VOUT may be the same in real time. When the warning signal SOC is at the disabled level (indicating that a CMT event has occurred in the isolated integrated circuit 100), the voltage level of the receiver output signal SOUT and the voltage level of the output voltage VOUT may not be the same in real time.

[0050] In the above embodiments, as Figure 3A and Figure 3B As shown, the warning circuit 25 converts the detected current IA (or detected current IB) to voltage via resistor RA (or resistor RB) to generate a warning signal SOC. It should be understood that the warning circuit 25 of this invention is not limited to... Figure 3A and Figure 3B The circuit architecture shown in the embodiment. For example, in some embodiments, resistors RA and RB are omitted, and the comparator circuits 251 and 252 in the alarm circuit 25 can each be implemented using current comparators. With this configuration, the alarm circuit 25 can compare the detected current IA with a current threshold (not shown) using comparator circuit 251 to generate a comparison signal SC1, and can compare the detected current IB with another current threshold (not shown) using comparator circuit 252 to generate a comparison signal SC2. Furthermore, the alarm circuit 25 can output an alarm signal SOC based on the comparison signals SC1 and SC2 using logic gate 253.

[0051] Furthermore, in the above embodiments, as Figure 1 As shown, receiver circuit 15 is a single-ended input architecture. Furthermore, Figure 2The common-mode transient detection circuit 200 is applicable to the receiver circuit 15 of a single-ended input architecture. It should be understood that the receiver circuit in the isolated integrated circuit 100 of this invention is not limited to... Figure 1 and Figure 2 The single-ended input architecture shown in the embodiment.

[0052] Please see Figure 4 , Figure 4 This is a circuit block diagram illustrating a common-mode transient detection circuit 400 for a receiver circuit 45 with a differential input architecture, according to some embodiments of the present invention. In some embodiments, the signal processing circuit 451 of the receiver circuit 45 is coupled to an input node NINP and another input node NINN, and generates output voltages VOUTP and VOUTN based on an input voltage VINP at input node NINP and another input voltage VINN at input node NINN, wherein the input voltages VINP and VINN form a differential input signal, and the output voltages VOUTP and VOUTN form a differential output signal. Specifically, the signal processing circuit 451 of the receiver circuit 45 can be implemented by various circuits such as logic circuits, demodulators, and receivers.

[0053] At Figure 4 In this embodiment, the common-mode transient detection circuit 400 is coupled to the input nodes NINP, NINN, signal processing circuit 451, and the output nodes NOUTP and NOUTN of the receiver circuit 45. Figure 2 and Figure 4 As shown, compared to Figure 2 The circuit configuration of the common-mode transient detection circuit 200. Figure 4 The common-mode transient detection circuit 400 also includes another bias circuit 31, another current generation circuit 33, and another warning circuit 35. In addition, the control circuit 37 in the common-mode transient detection circuit 400 is slightly different from the control circuit 27 in the common-mode transient detection circuit 200.

[0054] Bias circuit 21 is coupled to input node NINP. Current generation circuit 23 is coupled to bias circuit 21 and receives reference voltage VREF. Alarm circuit 25 is coupled to bias circuit 21 at nodes NA and NB. Bias circuit 31 is coupled to input node NINN. Current generation circuit 33 is coupled to bias circuit 31 and receives reference voltage VREF. Alarm circuit 35 is coupled to bias circuit 31 at nodes NC and ND. Furthermore, control circuit 37 is coupled to alarm circuit 25, alarm circuit 35, and output nodes NOUTP and NOUTN, and receives output voltages VOUTP and VOUTN generated by signal processing circuit 451.

[0055] Figure 4The circuit architecture of the medium bias circuits 21 and 31 can be similar to Figure 3A and Figure 3B Circuit architecture of medium bias circuit 21. Figure 4 The circuit architecture of the medium current generating circuits 23 and 33 can be similar to Figure 3A and Figure 3B The circuit architecture of the medium current generating circuit 23. Furthermore... Figure 4 The circuit architecture of warning circuits 25 and 35 can be similar to Figure 3A and Figure 3B The circuit architecture of the warning circuit 25. Figure 4 For instructions on operating the bias circuits 21 and 31, the current generating circuits 23 and 33, and the warning circuits 25 and 35, please refer to [link / reference needed]. Figure 3A and Figure 3B The relevant description.

[0056] As stated above, please refer to Figure 5 The control circuit 37 may include an AND gate 371 and latching circuits 373 and 375. The two inputs of the AND gate 371 may be coupled to the outputs of the warning circuit 25 and the warning circuit 35, respectively, while the output of the AND gate 371 may be coupled to the gate control terminals of the latching circuits 373 and 375. The data input D of the latching circuit 373 receives the output voltage VOUTP generated by the signal processing circuit 451, and the data output Q of the latching circuit 373 is coupled to the output node NOUTP. The data input D of the latching circuit 375 receives the output voltage VOUTN generated by the signal processing circuit 451, and the data output Q of the latching circuit 375 is coupled to the output node NOUTN.

[0057] Similar to Figure 2 , Figure 3A and Figure 3B In this embodiment, bias circuit 21, in response to a level change in input voltage VINP due to a CMT event, enables current generation circuit 23 to generate a detection current IA flowing into node NA (or a detection current IB flowing out of node NB) based on the transient current I1 (or transient current I2) generated by current generation circuit 23. Alarm circuit 25 generates an alarm signal SOCP based on the detection current IA flowing into node NA (or the detection current IB flowing out of node NB). Bias circuit 31, in response to a level change in input voltage VINN due to a CMT event, enables current generation circuit 33 to generate a detection current flowing into node NC (or another detection current flowing out of node ND) based on a transient current from current generation circuit 33 to bias circuit 31 (or another transient current from bias circuit 31 to current generation circuit 33). Alarm circuit 35 generates another alarm signal SOCN based on the detection current flowing into node NC (or the detection current flowing out of node ND).

[0058] Through the circuit configuration of the control circuit 37 described above, when at least one of the input voltages VINP and VINN changes drastically due to a CMT event, gate 371 can perform an AND operation based on at least one of the disable level warning signals SOCP and SOCN to output a disable level logic signal (not shown in the figure) to the gate control terminals of latch circuits 373 and 375. Accordingly, latch circuits 373 and 375 of control circuit 37 maintain the voltage of the data output terminal Q unchanged, that is, maintain the voltage levels of the receiver output signals SOUTP and SOUTN generated at the output nodes NOUTP and NOUTN respectively.

[0059] Furthermore, in the absence of a CMT event, alarm circuit 25 outputs an alarm signal SOCP to enable the level, while alarm circuit 35 outputs an alarm signal SOCN to enable the level. Gate 371 can perform an AND operation based on the alarm signals SOCP and SOCN to output the aforementioned logic signal to enable the level to the gate terminals of latch circuits 373 and 375. Accordingly, latch circuits 373 and 375 of control circuit 37 directly output the output voltages VOUTP and VOUTN generated by signal processing circuit 451 from data output terminal Q, respectively, as receiver output signals SOUTP and SOUTN.

[0060] As explained above, control circuit 37 selectively masks output voltages VOUTP and VOUTN based on the voltage levels of warning signals SOCP and SOCN, thereby generating receiver output signals SOUTP and SOUTN at output nodes NOUTP and NOUTN. Further explanation: when both warning signals SOCP and SOCN are enabled (indicating no CMT event has occurred), the voltage levels of receiver output signals SOUTP and SOUTN may be the same as the voltage levels of output voltages VOUTP and VOUTN in real time. When at least one of the warning signals SOCP and SOCN is disabled (indicating a CMT event has occurred), the voltage levels of receiver output signals SOUTP and SOUTN may not be the same as the voltage levels of output voltages VOUTP and VOUTN in real time.

[0061] It should be understood that the common-mode transient detection circuit 400 of the receiver circuit 45, which is suitable for a differential input architecture, is not limited to... Figure 4 The circuit configuration shown in the embodiment. For example, see [link to example]. Figure 6 In some embodiments, the common-mode transient detection circuit 600 is adapted to the receiver circuit 45 of a differential input architecture. Figure 6 The common-mode transient detection circuit 600 includes bias circuits 21 and 31, current generation circuits 23 and 33, an alarm circuit 25, and a control circuit 47, namely... Figure 4The warning circuit 35 can be omitted, and the bias circuit 31 can be coupled to the warning circuit 25 at nodes NA and NB. (See also...) Figure 7 The control circuit 47 may include latch circuits 471 and 473. The gate terminals of latch circuits 373 and 375 are both coupled to the output terminal of the alarm circuit 25. The data input terminal D of latch circuit 471 receives the output voltage VOUTP generated by signal processing circuit 451, while the data output terminal Q of latch circuit 471 is coupled to output node NOUTP. The data input terminal D of latch circuit 473 receives the output voltage VOUTN generated by signal processing circuit 451, while the data output terminal Q of latch circuit 473 is coupled to output node NOUTN. With this configuration, when at least one of the bias circuits 21 and 31 generates at least one detection current due to a CMT event (e.g., detection current IA, detection current IB, a detection current generated by bias circuit 31 and flowing into node NA from bias circuit 31, another detection current generated by bias circuit 31 and flowing into bias circuit 31 from node NB, etc.), the alarm circuit 25 can generate an alarm signal SOCP based on at least one detection current. The control circuit 47 receives the warning signal SOCP and can selectively block the output voltages VOUTP and VOUTN according to the voltage level of the warning signal SOCP, so as to generate receiver output signals SOUTP and SOUTN at the output nodes NOUTP and NOUTN.

[0062] As can be seen from the above embodiments of this utility model, through the common-mode transient detection circuit 200 (or common-mode transient detection circuit 400, common-mode transient detection circuit 600, etc.), the isolated integrated circuit 100 of this utility model can shield the output voltage VOUT (or output voltages VOUTP and VOUTN) that may be affected by the common-mode transient event when it occurs, thereby achieving the technical effect of preventing the receiver circuit 15 (or receiver circuit 45) from outputting an output voltage VOUT with an undesirable voltage level and / or waveform to the subsequent circuits of the isolated integrated circuit 100. Therefore, the isolated integrated circuit 100 of this utility model has the advantage of high reliability.

[0063] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0064] [Symbol Explanation]

[0065] 11: Transmitter Circuit

[0066] 13: Isolation circuit

[0067] 15,45: Receiver circuit

[0068] 21, 31: Bias circuit

[0069] 23, 33: Current generating circuit

[0070] 25, 35: Warning circuit

[0071] 27, 37, 47: Control circuit

[0072] 100: Isolated Integrated Circuits

[0073] 151,451: Signal processing circuit

[0074] 200, 400, 600: Common-mode transient detection circuit

[0075] 211, 212: Current mirror circuit

[0076] 231, 232: Transistor pairs

[0077] 251, 252: Comparator circuits

[0078] 253: Logic gate

[0079] 271, 373, 375, 471, 473: Latch circuits

[0080] 371: and gate

[0081] D: Data input terminal

[0082] I1, I2: Transient currents

[0083] IA,IB: Detecting current

[0084] MNL1, MNL2, MNU1, MNU2, MPL1, MPL2, MPU1, MPU2: Transistors

[0085] N1, N2, N3, N4, NA, NB, NC, ND: Nodes

[0086] NIN, NINP, NINN: Input nodes

[0087] NOUT, NOUTP, NOUTN: Output nodes

[0088] Q: Data output end

[0089] RA, RB: Resistance

[0090] SC1, SC2: Comparison signals

[0091] SOC, SOCP, SOCN: Warning signals

[0092] SOUT, SOUTP, SOUTN: Receiver output signal

[0093] VDD1, VDD2: Power supply voltage

[0094] VIN, VINP, VINN: Input voltage

[0095] VOUT, VOUTP, VOUTN: Output voltage

[0096] VREF: Reference Voltage

[0097] VSS1, VSS2: Grounding voltage.

Claims

1. A common-mode transient detection circuit, characterized in that, A receiver circuit suitable for isolated integrated circuits, comprising: A first current generating circuit is used to receive a reference voltage and to generate one of a first transient current and a second transient current in response to a level change of the first input voltage at the first input node of the receiver circuit due to a common-mode transient event. A first bias circuit, coupled to the first input node and the first current generating circuit, is used to receive the first input voltage and to enable the first current generating circuit in response to the level change of the first input voltage, so as to generate one of the first detection current and the second detection current based on the first transient current and the second transient current. A first warning circuit, coupled to the first bias circuit at the first node and the second node, is used to receive the first detection current and the second detection current, and to generate a first warning signal based on the first detection current and the second detection current. as well as A control circuit, coupled to the first output node of the first warning circuit and the receiver circuit, is used to receive the first warning signal and the first output voltage generated by the receiver circuit based on the first input voltage, and to selectively block the first output voltage based on the voltage level of the first warning signal, so as to generate a first receiver output signal at the first output node.

2. The common-mode transient detection circuit according to claim 1, characterized in that, The first bias circuit includes: A first current mirror circuit is coupled to the first input node, coupled to the first current generating circuit to the third and fourth nodes, coupled to the first warning circuit to the first node, and is used to replicate the first transient current to generate the first detection current that flows sequentially through the fourth node and the first node, wherein the first transient current flows sequentially through the third node and the first input node. as well as The second current mirror circuit is coupled to the first input node, coupled to the first current generating circuit to the fifth and sixth nodes, coupled to the first warning circuit to the second node, and is used to replicate the second transient current to generate the second detection current that flows sequentially through the second and sixth nodes, wherein the second transient current flows sequentially through the first input node and the fifth node.

3. The common-mode transient detection circuit according to claim 2, characterized in that, The first current generating circuit includes: The first transistor pair is coupled to the reference voltage, coupled between the power supply voltage and the first current mirror circuit, coupled to the first current mirror circuit at the third node and the fourth node, and is biased by the first current mirror circuit to generate the first transient current. as well as The second transistor pair is coupled to the reference voltage, coupled between the ground voltage and the second current mirror circuit, coupled to the second current mirror circuit at the fifth node and the sixth node, and is biased by the second current mirror circuit to generate the second transient current. One of the first transistor pair and the second transistor pair is biased by the corresponding current mirror circuit in the first current mirror circuit and the second current mirror circuit in response to the level change of the first input voltage.

4. The common-mode transient detection circuit according to claim 2, characterized in that, The first warning circuit includes: A first comparison circuit is coupled to the first current mirror circuit at the first node and is used to compare the first detected current with a first current threshold to generate a first comparison signal. The second comparison circuit is coupled to the second current mirror circuit at the second node and is used to compare the second detected current with the second current threshold to generate a second comparison signal. as well as A logic gate is coupled to the first comparison circuit and the second comparison circuit, and is used to output the first warning signal based on the first comparison signal and the second comparison signal. When at least one of the first comparison signal and the second comparison signal is an enable level, the first warning signal is a disable level. The control circuit blocks the first output voltage based on the first warning signal at the disable level, so that the voltage level of the first receiver output signal is not the same as the voltage level of the first output voltage in real time.

5. The common-mode transient detection circuit according to claim 2, characterized in that, The first warning circuit includes: The first resistor is coupled to the first current mirror circuit at the first node; The second resistor is coupled to the second current mirror circuit at the second node; A first comparison circuit is coupled to the first current mirror circuit at the first node and is used to compare the voltage at the first node with a first voltage threshold to generate a first comparison signal. The second comparison circuit is coupled to the second current mirror circuit at the second node and is used to compare the voltage at the second node with a second voltage threshold to generate a second comparison signal. as well as A logic gate is coupled to the first comparison circuit and the second comparison circuit, and is used to output the first warning signal based on the first comparison signal and the second comparison signal. When at least one of the first comparison signal and the second comparison signal is an enable level, the first warning signal is a disable level. The control circuit blocks the first output voltage based on the first warning signal at the disable level, so that the voltage level of the first receiver output signal is not the same as the voltage level of the first output voltage in real time.

6. The common-mode transient detection circuit according to claim 1, characterized in that, The control circuit includes: A latching circuit, wherein the gate terminal of the latching circuit is coupled to the first warning circuit to receive the first warning signal, the data input terminal of the latching circuit receives the first output voltage, and the data output terminal of the latching circuit is coupled to the first output node to output the first receiver output signal. When the first warning signal at the disabled level is input to the gate terminal of the latch circuit, the latch circuit maintains the voltage at the data output terminal unchanged, so that the voltage level of the first receiver output signal is not immediately the same as the voltage level of the first output voltage. When the first warning signal of the enable level is input to the gate terminal of the latch circuit, the latch circuit directly outputs the first output voltage from the data output terminal, so that the voltage level of the first receiver output signal is the same as the voltage level of the first output voltage in real time.

7. The common-mode transient detection circuit according to claim 1, characterized in that, Also includes: The second current generating circuit is used to receive the reference voltage and to generate one of the third transient current and the fourth transient current in response to the level change of the second input voltage at the second input node of the receiver circuit due to the common-mode transient event. as well as The second bias circuit, coupled to the second input node and the second current generating circuit, is used to receive the second input voltage and, in response to the level change of the second input voltage, enable the second current generating circuit to generate one of the third detection current and the fourth detection current.

8. The common-mode transient detection circuit according to claim 7, characterized in that, The second bias circuit is coupled to the first warning circuit at the first node and the second node; The first warning circuit is used to generate the first warning signal based on at least one of the first detection current, the second detection current, the third detection current and the fourth detection current. The first detection current flows into the first node from the first bias circuit, the second detection current flows into the first bias circuit from the second node, the third detection current flows into the first node from the second bias circuit, and the fourth detection current flows into the second bias circuit from the second node.

9. The common-mode transient detection circuit according to claim 7, characterized in that, Also includes: The second warning circuit is coupled to the second bias circuit at the third node and the fourth node to receive the third detection current and the fourth detection current, and to generate a second warning signal based on the third detection current and the fourth detection current. The control circuit is coupled to the second output node of the second warning circuit and the receiver circuit, and is used to receive the second warning signal and the second output voltage generated by the receiver circuit based on the second input voltage. It is also used to selectively block the first output voltage and the second output voltage based on the voltage level of the first warning signal and the voltage level of the second warning signal, so as to generate the first receiver output signal and the second receiver output signal at the first output node and the second output node respectively.

10. An isolated integrated circuit, characterized in that, Include: Receiver circuit, comprising: A signal processing circuit is coupled to the first input node of the receiver circuit and is used to generate a first output voltage based on the first input voltage of the first input node. as well as A common-mode transient detection circuit is coupled to the first input node, the signal processing circuit, and the first output node of the receiver circuit. It is used to detect common-mode transient events based on the first input voltage and to block the first output voltage when the common-mode transient event occurs, so as to generate a first receiver output signal at the first output node. The common-mode transient detection circuit includes: A first current generating circuit is used to receive a reference voltage and to generate one of a first transient current and a second transient current in response to a level change in the first input voltage due to the common-mode transient event. A first bias circuit, coupled to the first input node and the first current generating circuit, is used to receive the first input voltage and to enable the first current generating circuit in response to the level change of the first input voltage, so as to generate one of the first detection current and the second detection current based on the first transient current and the second transient current. A first warning circuit, coupled to the first bias circuit at the first node and the second node, is used to receive the first detection current and the second detection current, and to generate a first warning signal based on the first detection current and the second detection current. as well as A control circuit, coupled to the first warning circuit, the signal processing circuit and the first output node, is used to receive the first warning signal and the first output voltage, and to selectively block the first output voltage according to the voltage level of the first warning signal, so as to generate the first receiver output signal at the first output node.

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