Complementary metal oxide semiconductor (CMOS) detector reading device with chopping

Abstract

The utility model relates to the fields of aerospace, geological exploration, low-light detection and the like, in particular to a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) detector reading device with chopping, which comprises a photoelectric conversion unit, a pixel reading unit and an image reading unit. The photoelectric conversion unit includes a plurality of photodiodes. And the plurality of pixel reading units are in one-to-one correspondence with the photodiodes and are connected to the photodiodes. The image readout unit is connected to the plurality of pixel readout units. The pixel reading unit comprises an integration unit, a filtering unit, a sampling unit and an output driving unit. The integration unit comprises a chopping module. The photodiode is connected to the integration unit, and the integration unit is connected to the filtering unit. The filtering unit is connected to the sampling unit. The sampling unit is connected to the output driving unit. The output driving unit is connected to the image readout unit. According to the utility model, circuit noise is eliminated by using chopping processing, the bandwidth range of processable signals is increased, and signal burrs introduced by the chopping processing are eliminated by using the correlated double-sampling circuit.

Description

TECHNICAL FIELD

[0001] The utility model relates to aerospace, geological exploration and micro-light detection fields, especially a CMOS detector reading device with chopper. BACKGROUND

[0002] With the progress of science and technology and the continuous development of modern society, the requirement of micro-light signal detection is also higher and higher. In recent years, CMOS image sensor technology has shown strong advantages in the field of optical sensors, and the performance and performance index of low-noise photoelectric detector are also continuously improved. In the field of micro-light detection, noise further becomes the key factor restricting the performance improvement of photoelectric detector. Therefore, it is necessary to improve the structure of the readout circuit to reduce the circuit noise.

[0003] Modern CMOS integrated circuit technology is more and more towards the direction of improving the performance of digital circuits, which makes the analog signal processing in digital environment have to face the challenge brought by the decrease of power supply voltage and the increase of noise voltage and offset voltage. Taking a typical 0.35μm CMOS process as an example, its working voltage has been reduced to 3.3V, while the noise corner frequency of a typical size MOS tube is generally greater than 100k Hz, and the input offset voltage is in the order of mV. With the rapid development of integrated circuit technology, an important development trend of sensing technology is to realize the integration of sensor readout circuit, and even to realize the single-chip integration of micro-sensor and sensor readout circuit. For micro-sensor, since its output signal is mainly at the low frequency end and the signal amplitude is very small, therefore the increase of offset and low-frequency noise caused by CMOS process poses a great challenge to the design of micro-sensor readout circuit. The continuous development of modern society requires higher and higher micro-light signal detection, so in the design of CMOS image sensor readout circuit, it is very important to suppress and eliminate the noise of readout circuit and improve the signal-to-noise ratio.

[0004] The device electronic noise of readout circuit is mainly divided into three categories according to the generation mechanism: first, the noise inherent to the device, such as the thermal noise and 1 / f noise of MOS tube; second, the noise caused by circuit structure and working mode, such as channel charge injection, clock feedthrough, KTC noise, etc.; third, the spatial noise caused by process manufacturing error, such as fixed pattern noise. These noises will be transmitted to the next stage, reducing the signal-to-noise ratio and limiting the dynamic range of output, so noise processing is necessary for readout circuit design. CTIA is one of the most widely used photoelectric detector readout circuits, and in recent years, the research on noise reduction of CTIA has never stopped, mainly including the processing of KTC noise and 1 / f noise. At present, through the use of correlated double sampling technology, the KTC noise of the readout circuit can be significantly suppressed, but the substantial reduction of 1 / f noise is more realized by process means. SUMMARY

[0005] The purpose of this invention is to provide a CMOS detector readout device with chopper, which mainly solves the problems existing in the prior art. It reduces the 1 / f noise of the CTIA core amplifier from the circuit aspect by using the relevant principles of chopper technology, so as to further improve the signal-to-noise ratio of the readout circuit under the existing process conditions, thereby optimizing the performance indicators of the photodetector.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is to provide a CMOS detector readout device with chopper, characterized in that the CMOS detector readout device with chopper includes a photoelectric conversion unit, a pixel readout unit and an image readout unit.

[0007] The photoelectric conversion unit includes multiple photodiodes; there are also multiple pixel readout units, each corresponding to one of the photodiodes and connected to them; the image readout unit is connected to multiple pixel readout units.

[0008] The pixel readout unit includes an integration unit, a filtering unit, a sampling unit, and an output driving unit; the integration unit includes a chopper module; the input of the integration unit is connected to the photodiode, and the output is connected to the input of the filtering unit; the output of the filtering unit is connected to the input of the sampling unit; the output of the sampling unit is connected to the input of the output driving unit; and the output of the output driving unit is connected to the image readout unit.

[0009] Furthermore, the integration unit also includes an integration capacitor, an operational amplifier module, and a bias module;

[0010] The integrating capacitor is connected between the input and output terminals of the operational amplifier module; the bias module is a current source connected to the operational amplifier module; and the chopper module is connected to the operational amplifier module.

[0011] Furthermore, the chopper module includes an input chopper module and an output chopper module; the input chopper module is disposed at the input terminal of the operational amplifier module, and the output chopper module is disposed at the output terminal of the operational amplifier module.

[0012] Furthermore, the operational amplifier module is a capacitor transimpedance amplifier, employing a folded common-source and common-gate structure, comprising a common-source submodule and a common-gate submodule; the input terminal is connected to the common-source submodule via the input chopper module; the output of the common-source submodule is connected to the common-gate submodule; and the output of the common-gate submodule is connected to the output terminal via the output chopper module.

[0013] Furthermore, the operational amplifier module includes two input terminals and one output terminal.

[0014] Furthermore, the input chopper module and the output chopper module include a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a clock control switch; the clock control switch includes four sets of CMOS devices with the same channel length, namely a first clock controller, a second clock controller, a third clock controller, and a fourth clock controller;

[0015] The first input terminal is connected to the first output terminal via the first clock controller and to the second output terminal via the second clock controller; the second input terminal is connected to the first output terminal via the third clock controller and to the second output terminal via the fourth clock controller.

[0016] Furthermore, the filtering unit is an RC low-pass filter.

[0017] Furthermore, the sampling unit is a correlated dual sampling circuit, comprising a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor;

[0018] The reset switch is connected to the second sampling capacitor and the power supply ground; the first sampling switch is connected to the first sampling capacitor and the reference voltage; the second sampling switch is connected to the second sampling capacitor and the filter unit.

[0019] Furthermore, the output driving unit is a unity-gain buffer.

[0020] Furthermore, the image readout unit includes a shift register; the input of the shift register is connected to a plurality of pixel readout units.

[0021] In view of the above technical features, the CMOS detector readout device with chopper provided by this utility model has the following significant features compared with the prior art:

[0022] 1. The input chopper module and output chopper module in the CMOS detector readout device with chopper of this utility model adopt the method of low-impedance node chopper and dynamic element matching, which can increase the bandwidth range of the signal that can be processed without significant deterioration of the input equivalent offset voltage.

[0023] 2. The output of the integrating unit with chopping processing function in the CMOS detector of this invention is optimized into a single-ended output circuit. When the common-mode output level of this single-ended output circuit shifts, the change in the branch current can be affected by the change in the self-bias voltage, thereby forming a negative feedback effect on the common-mode output level, without the need to design an additional common-mode feedback circuit.

[0024] 3. The two choppers in the output chopper module of the integrating unit with chopper processing function in the CMOS detector with chopper of this utility model dynamically switch the two PMOS transistors in the current mirror of the operational amplifier module, and further reduce the current mismatch of the current mirror by using the dynamic component matching method.

[0025] 4. The sampling unit in the CMOS detector readout device with chopper of this utility model adopts a timing design of related dual sampling circuit, which can eliminate the related noise of the circuit and the voltage glitches introduced by the preceding input chopper module and the output chopper module in the chopper process.

[0026] 5. The sampling unit of the CMOS detector readout device with chopper of this utility model uses two simple capacitors as sampling circuits to obtain the difference integral voltage at two time points, eliminating the need for a subtractor and saving layout area. Attached Figure Description

[0027] Figure 1 This is a system block diagram of a preferred embodiment of the CMOS detector readout device with chopper of this utility model;

[0028] Figure 2 This is a system block diagram of the pixel readout unit in a preferred embodiment of the CMOS detector readout device with chopper of this utility model;

[0029] Figure 3 This is a circuit diagram of the integration unit and the filtering unit in a preferred embodiment of the CMOS detector readout device with chopper of this utility model;

[0030] Figure 4 This is a circuit diagram of the input chopper module and the output chopper module in the integration unit of a preferred embodiment of the CMOS detector readout device with chopper of this utility model;

[0031] Figure 5 This is a circuit diagram of the sampling unit in a preferred embodiment of the CMOS detector readout device with chopper of this utility model;

[0032] Figure 6 This is a timing diagram of a preferred embodiment of the CMOS detector readout device with chopper of this utility model.

[0033] In the diagram: 100 - photoelectric conversion unit, 200 - pixel readout unit, 300 - image readout unit;

[0034] 101-Photodiode;

[0035] 210 - Integrating unit, 220 - Filtering unit, 230 - Sampling unit, 240 - Output driving unit;

[0036] 211-Integrating capacitor, 212-Operational amplifier module, 213-Bias module, 214-Input chopper module, 215-Output chopper module;

[0037] 2161 - First clock controller, 2162 - Second clock controller, 2163 - Third clock controller, 2164 - Fourth clock controller. Detailed Implementation

[0038] The specific embodiments of this utility model will be described below with reference to the accompanying drawings.

[0039] Please see Figures 1 to 5 This utility model discloses a CMOS detector readout device with chopper. As shown in the figure, a preferred embodiment includes a photoelectric conversion unit 100, a pixel readout unit 200, and an image readout unit 300.

[0040] The photoelectric conversion unit 100, composed of multiple photodiodes 101, converts optical signals into electrical signals. Each photodiode 101 corresponds to a pixel. The electrical signals from all photodiodes 101 are concatenated to form an image from one photoelectric conversion. The pixel readout unit 200 corresponds one-to-one with each photodiode 101, reading the raw electrical signal of a single photodiode 101 and processing it to obtain the pixel electrical signal. The image readout unit 300 sequentially acquires the pixel electrical signal corresponding to each pixel from all pixel readout units 200, concatenating it to form the image electrical signal corresponding to the complete image. A key component in the image readout unit 300 is a shift register, whose input is connected to multiple pixel readout units, controlling the bus switch to read out each pixel one by one. Under the control of the shift register, the image readout unit 300 is sequentially connected to each pixel readout unit 200, storing the pixel electrical signal corresponding to each pixel in the shift register. Before each new pixel electrical signal is read, the already read pixel electrical signal is shifted to make room for the new pixel electrical signal. Finally, all pixel electrical signals are read out from the shift register in one complete operation to obtain the entire image electrical signal.

[0041] In this invention, the main structural optimization is made to the pixel readout unit 200. The pixel readout unit 200 consists of an integration unit 210, a filtering unit 220, a sampling unit 230, and an output driving unit 240. The integration unit 210 is connected to a photodiode 101 (PD), obtains the original electrical signal from the photodiode 101 (PD), integrates the original electrical signal, and obtains the integrated output signal. Chopper units are set at the input and output terminals of the integration unit 210 to chopper the signals input to and output to the integration unit 210. In this way, the original electrical signal undergoes two chopper processes when entering and exiting the integration unit 210, and the frequency jumps back to the original low-frequency band. However, the noise signal generated inside the integration unit 210 is only chopper processed once at the output terminal and switched to the high-frequency band. Therefore, the filtering unit 220 connected after the integration unit 210 is used to filter out the high-frequency band electrical signal, thereby removing the noise signal generated inside the integration unit 210 and outputting only the integrated output signal based on the original electrical signal. The integrated output signal, filtered by filter unit 220, is input to sampling unit 230. Filter unit 220 is an RC low-pass filter composed of C1 and R1. Its cutoff frequency is lower than the chopping frequency in integrator unit 210, thus filtering out high-frequency signals that only undergo one chopping operation. A compensation capacitor C2 with a value of 1 pF is also included in filter unit 220. Sampling unit 230 performs sample-and-hold operations. It reads and holds the integrated output signal according to a preset sampling frequency, allowing image readout unit 300 to sequentially read the outputs of all pixel readout units 200 within a certain period. Sampling unit 230 itself obtains the sampled output signal by sampling the voltage difference at different time points, further eliminating the inherent signal offset of the system. The output signal of sampling unit 230 is amplified by output drive unit 240 and used as the pixel electrical signal of the current sampling unit 230. Output drive unit 240 is specifically implemented as a unity-gain buffer, enabling lossless differential signal readout.

[0042] The integrator unit 210 consists of an integrating capacitor 211, an operational amplifier module 212, a bias module 213, an input chopper module 214, and an output chopper module 215. The core component of the integrator unit 210 is the operational amplifier module 212, which is a capacitor transimpedance amplifier using a folded cascode structure. The operational amplifier module 212 and the integrating capacitor 211 are combined, with the integrating capacitor 211 connected between the input and output terminals of the operational amplifier module 212, thus utilizing the electrical characteristics of the integrating capacitor itself to perform voltage integration. The integrating capacitor 211 is a Cint with a value of 500 fF. The integration starting voltage is provided by a voltage source Vdc, connected to the input of the integrator unit 210, and set to 1V. The operational amplifier module 212 requires an external bias current for normal operation. The bias module 213 performs this function; it is a current source composed of MOSFETs PM6, PM7, PM8, NM5, NM6, NM7, NM8, and NM9. Its output is connected to the operational amplifier module 212, providing the bias current required for the operational amplifier module 212 to operate. The input chopper module 214 and the output chopper module 215 are new designs in this invention, used to filter internal thermal noise of the operational amplifier module 212. The input chopper module 214 is located before the input terminal of the operational amplifier module 212, while the output chopper module 215 is located after the output terminal of the operational amplifier module 212. The input chopper module 214 chops all input signals (raw electrical signals), while the output chopper module 215 chops all output signals (processed raw electrical signals and noise signals).

[0043] The operational amplifier module 212 adopts a self-biased dual-input single-output structure, containing two input terminals and one output terminal. Internally, it is further subdivided into a common-source submodule and a common-gate submodule. The common-source submodule consists of MOSFETs PM1, PM2, and PM3. PM1 and PM2 are connected to the input terminals to convert the input signal into an intermediate signal. The common-gate submodule consists of MOSFETs PM4, PM5, NM1, NM2, NM3, and NM4. The common-gate submodule is controlled by the intermediate signal output from PM1 and PM2, and its output is the amplified integral output signal. The output of the input chopper module is connected to the gates of PM1 and PM2 in the common-source submodule to chop the input signal. There are two output chopper modules, connected to the source and drain of NM1 and NM2 in the common-gate submodule, respectively, to chop the integral output signal. The integration unit 210 includes a reset switch. When the reset switch is closed, Cint is short-circuited, and the charge is cleared to zero, which is the initial stage of the integration unit 210. When the reset switch is open, the integration unit 210 starts to work. The current generated by the photodiode 101 (PD) causes the charge to accumulate on Cint, generating a linearly rising voltage at the output terminal. After passing through the filter unit 220 (low-pass filter structure), the voltage is output to the next stage sampling unit 230.

[0044] The input chopper module 214 and the output chopper module 215 have the same internal structure, including a first input terminal INP, a second input terminal INN, a first output terminal OP, a second output terminal ON, and four sets of CMOS devices with the same channel length. The ratio of the PMOS channel width to the NMOS channel width is 2.5 to 1. The CMOS devices meet the dynamic element matching condition and are controlled by paired clock signals clk and clkb, forming a clock control switch, including a first clock controller 2161, a second clock controller 2162, a third clock controller 2163, and a fourth clock controller 2164. The first clock controller 2161 and the fourth clock controller 2164 are simultaneously turned on and off, while the second clock controller 2162 and the third clock controller 2163 are simultaneously turned on and off, and they alternate between turning on and off. clk and clkb are opposite square wave signals, with a high level of 5V, a low level of 0V, a duty cycle of 50%, and a period of 40 kHz. Specifically, the first input terminal INP is connected to the first output terminal OP through the first clock controller 2161, and to the second output terminal ON through the second clock controller 2162. The second input terminal INN is connected to the first output terminal INP through the third clock controller 2163, and to the second output terminal ON through the fourth clock controller 2164. When the clock signal clk is high, the first clock controller 2161 and the fourth clock controller 2164 are turned on, and the second clock controller 2162 and the third clock controller 2163 are turned off. At this time, the first input terminal INP and the first output terminal OP are connected, and the second input terminal INN and the second output terminal ON are connected. When the clock signal clk is low, the first clock controller 2161 and the fourth clock controller 2164 are turned off, and the second clock controller 2162 and the third clock controller 2163 are turned on. At this time, the first input terminal INP is connected to the second output terminal ON, and the second input terminal INN is connected to the first output terminal OP.

[0045] The chopping principle is that when a signal passes through the input chopper module 214 or the output chopper module 215, a 40 kHz frequency domain modulation is achieved. For the integrator unit 210, the input voltage signal undergoes an even number of chopping operations (twice), while the low-frequency noise (1 / f noise) generated by its own circuitry undergoes an odd number of chopping operations (once). According to the frequency modulation principle of the chopper, the signal after an even number of chopping operations returns to the fundamental frequency, but the signal after an odd number of chopping operations remains at a high frequency (40 kHz). Therefore, the signal and noise are separated in the frequency domain. After low-frequency filtering by the filter unit 220, the high-frequency noise is filtered out, achieving a noise reduction effect.

[0046] Sampling unit 230 is a correlated dual-sampling circuit that samples the voltage difference between two time points on the integral curve to achieve FPN noise removal. It includes a first sampling switch S1, a second sampling switch S2, a reset switch S3, a first sampling capacitor C1, and a second sampling capacitor C2. Its structure is simple and easy to control. Connecting it to the output drive unit 240, which forms a unity-gain buffer, enables lossless differential signal readout. The first sampling switch S1, the second sampling switch S2, and the reset switch S3 operate in a specific timing sequence to complete dual sampling and hold operations. The reset switch S3 connects the second sampling capacitor C1 to the power supply ground. When the reset switch S3 is on, it discharges the second sampling capacitor C1. The first sampling switch S1 connects to the reference voltage Vref and the first sampling capacitor C1; when on, it charges the first sampling capacitor C1 using the reference voltage Vref. The input IN terminal of the second sampling switch S2 connects to the filter unit 220 and the second sampling capacitor C2; when on, it reads the filtered integral output signal to charge the second sampling capacitor C2.

[0047] Please Figures 1 to 5 Based on the combination Figure 6 As shown in the figure, a preferred embodiment of the CMOS detector readout device with chopper of this utility model achieves signal integration, sampling, and noise reduction within one sampling period by controlling the timing of the operational amplifier module 212, input chopper module 214, output chopper module 215, and sampling unit 230 in the integration unit 210, resulting in a low-noise voltage output. Specifically, the Choppr signal is the clock signal of the input chopper module 214 and the output chopper module 215, which varies with a period of 25 microseconds (40kHz). The integration unit 210 enters the working state after being reset under the CTIA_reset signal. The sampling unit 230 is reset under the CDS_reset control. In the sampling unit 230, the CDS1 signal controls the first sampling switch S1, the CDS2 signal controls the second sampling switch S2, and the CDS_reset signal controls the reset switch S3. The reset signal CDS_reset first activates the reset switch S3, then uses the first sampling switch S1 to activate Vref for the first sampling, and subsequently uses the second sampling switch S2 to sample the integrated output signal. After the first sampling switch S1 and the second sampling switch S2 are both activated and held for a period of time, the voltage difference between the second sampling capacitor C2 and the first sampling capacitor C1 is obtained, which serves as the sampling output signal of the sampling unit 230. DFF_clk is used to control the operation of the shift register in the image readout unit 300, with a period of 80 microseconds. DFF_in varies depending on the pixel electrical signal.

[0048] The noise measurement results for this embodiment are as follows. At a chopping frequency of 40 kHz, the output noise of the chopper-equipped integrator is 87.9 μVrms. In comparison, the output noise of a CTIA chip without a chopper, manufactured using the same process, is 158.6 μVrms. The introduction of chopping technology reduces the RMS noise of the chip test by 44.58%.

[0049] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of this utility model. All equivalent changes and modifications made within the scope of the claims of this utility model should be considered within the technical scope of this utility model.

Claims

1. A CMOS detector readout device with chopper, characterized in that, It includes a photoelectric conversion unit, a pixel readout unit, and an image readout unit; The photoelectric conversion unit includes multiple photodiodes; there are also multiple pixel readout units, each corresponding to one of the photodiodes and connected to them; the image readout unit is connected to multiple pixel readout units. The pixel readout unit includes an integration unit, a filtering unit, a sampling unit, and an output driving unit; the integration unit includes a chopper module; the input of the integration unit is connected to the photodiode, and the output is connected to the input of the filtering unit. The output of the filtering unit is connected to the input of the sampling unit; the output of the sampling unit is connected to the input of the output driving unit; and the output of the output driving unit is connected to the image readout unit.

2. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The integration unit also includes an integration capacitor, an operational amplifier module, and a bias module; The integrating capacitor is connected between the input and output terminals of the operational amplifier module; the bias module is a current source connected to the operational amplifier module; and the chopper module is connected to the operational amplifier module.

3. The CMOS detector readout device with chopper as described in claim 2, characterized in that, The chopper module includes an input chopper module and an output chopper module; the input chopper module is located at the input terminal of the operational amplifier module, and the output chopper module is located at the output terminal of the operational amplifier module.

4. The CMOS detector readout device with chopper as described in claim 3, characterized in that, The operational amplifier module is a capacitor transimpedance amplifier with a folded common-source and common-gate structure, comprising a common-source submodule and a common-gate submodule; the input terminal is connected to the common-source submodule through the input chopper module; the output of the common-source submodule is connected to the common-gate submodule. The output of the common-gate submodule is connected to the output terminal via the output chopper module.

5. The CMOS detector readout device with chopper as described in claim 2, characterized in that, The operational amplifier module includes two input terminals and one output terminal.

6. The CMOS detector readout device with chopper as described in claim 3, characterized in that, The input chopper module and the output chopper module include a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a clock control switch; the clock control switch includes four sets of CMOS devices with the same channel length, namely a first clock controller, a second clock controller, a third clock controller, and a fourth clock controller; The first input terminal is connected to the first output terminal via the first clock controller and to the second output terminal via the second clock controller; the second input terminal is connected to the first output terminal via the third clock controller and to the second output terminal via the fourth clock controller.

7. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The filtering unit is a resistor-capacitor low-pass filter.

8. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The sampling unit is a correlated dual sampling circuit, which includes a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor; The reset switch is connected to the second sampling capacitor and the power supply ground; the first sampling switch is connected to the first sampling capacitor and the reference voltage; the second sampling switch is connected to the second sampling capacitor and the filter unit.

9. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The output drive unit is a unity-gain buffer.

10. The CMOS detector readout device with chopper as described in claim 1, characterized in that, The image readout unit includes a shift register; the input of the shift register is connected to multiple pixel readout units.

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