Three-dimensional package-on-package structure

Abstract

The utility model discloses a three-dimensional stacked packaging structure. The three-dimensional stacked packaging structure comprises a bottom chip; the core chip group is positioned on the first active surface of the bottom chip; the top chip set is located on the top surface of the core chip set, the core chip set comprises a plurality of hybrid bonding units which are sequentially stacked in the direction perpendicular to the first active face of the bottom chip, and each hybrid bonding unit comprises two core chips with the active faces opposite to each other and bonded together in a hybrid mode; the bottom chip is mixed and bonded with one core chip of the mixed bonding unit at the bottommost layer in the core chip set, and the top chip set comprises two top chips of which the active surfaces are oppositely mixed and bonded together; one top chip in the top chip set and one core chip of the hybrid bonding unit on the topmost layer in the core chip set are bonded together in a hybrid mode, the interconnection distance between the chips is greatly reduced through the hybrid bonding mode, and therefore more layers of chips can be stacked.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and particularly relates to a three-dimensional stacked packaging structure. BACKGROUND

[0002] HBM (High Bandwidth Memory) is a new type of CPU / GPU memory chip (i.e. "RAM"), which is actually a combination of many DDR chips stacked together and packaged with a GPU to realize a large-capacity, high-bit-width DDR array.

[0003] At present, the most advanced packaging technology of HBM adopts a through-silicon via + micro-bump (TSV + Micro-bump) mode for vertical interconnection of chips. Although this interconnection mode can greatly improve the urgent demand of HBM for high bandwidth and large capacity, the micro-bump interconnection technology still has further improvement space. For example, in the existing micro-bump interconnection technology, a medium material needs to be filled between chips, which increases the thickness of HBM, limits the stackable number of layers, and also affects the heat dissipation of the chip. At present, the minimum micro-bump pitch of the advanced packaging technology of HBM is 40 um, and the bump size is about 20 um or above, which is difficult to further reduce. CONTENT OF THE INVENTION

[0004] The purpose of the present application is to reduce the interconnection pitch of chips in the vertical direction in the three-dimensional stacked packaging structure, reduce the thickness of the overall chip, and thus stack more layers of chips.

[0005] In order to achieve the above-mentioned purpose, the present application provides a three-dimensional stacked packaging structure in one aspect, comprising:

[0006] a bottom chip, the bottom chip comprising a first active surface and a first back surface opposite to each other, and the first active surface being provided with a first hybrid bonding layer;

[0007] a core chip set on the first active surface of the bottom chip, the core chip set comprising a plurality of hybrid bonding units stacked in sequence along a direction perpendicular to the first active surface of the bottom chip, each of the hybrid bonding units comprising two core chips with their active surfaces bonded together, each of the core chips comprising a second active surface and a second back surface opposite to the second active surface, the second active surface having a second hybrid bonding layer thereon, the second back surface having a third hybrid bonding layer thereon, the second hybrid bonding layers of the second active surfaces of the two core chips in each of the hybrid bonding units being bonded together, and the third hybrid bonding layer of the second back surface of one of the core chips in an upper hybrid bonding unit of the core chip set being bonded to the corresponding third hybrid bonding layer of the second back surface of one of the core chips in a lower hybrid bonding unit, the third hybrid bonding layer of the second back surface of one of the core chips in a bottommost hybrid bonding unit of the core chip set being bonded to the first hybrid bonding layer of the first active surface of the bottom chip;

[0008] a top chip set on a top surface of the core chip set, the top chip set comprising two top chips with their third active surfaces bonded together, each of the two top chips comprising a third back surface and a third active surface opposite to the third back surface, each of the third active surfaces of the two top chips having a fourth hybrid bonding layer thereon, the third back surface of one of the top chips having a fifth hybrid bonding layer thereon, the fourth hybrid bonding layers of the third active surfaces of the two top chips of the top chip set being bonded together, and the fifth hybrid bonding layer of the third back surface of one of the top chips of the top chip set being bonded to the third hybrid bonding layer of the second back surface of one of the core chips in a topmost hybrid bonding unit of the core chip set.

[0009] In some embodiments, the bottom chip has a first integrated circuit and a first through-hole interconnection structure electrically connected to the first integrated circuit, the first through-hole interconnection structure comprising a first end and a second end opposite to the first end, the second end of the first through-hole interconnection structure being exposed by the first back surface of the bottom chip, the first active surface of the bottom chip having a first pad electrically connected to the first end of the first through-hole interconnection structure; the first hybrid bonding layer comprises a first bonding dielectric layer on the first active surface of the bottom chip and a first bonding metal layer in the first bonding dielectric layer, the first bonding dielectric layer exposing a surface of the first bonding metal layer, the first bonding metal layer being electrically connected to the first pad.

[0010] In some embodiments, each of the core chips has a second integrated circuit and a second through-hole interconnection structure, a first end of the second through-hole interconnection structure is electrically connected with the second integrated circuit, the second through-hole interconnection structure includes opposite first and second ends, the second back surface of the core chip exposes the second end of the second through-hole interconnection structure, and the second active surface of the core chip has a second pad that is electrically connected with the first end of the second through-hole interconnection structure; the second hybrid bonding layer includes a second bonding medium layer on the second active surface of the core chip and a second bonding metal layer in the second bonding medium layer, the second bonding medium layer exposes a surface of the second bonding metal layer, and the second bonding metal layer is electrically connected with the second pad; and the third hybrid bonding layer includes a third bonding medium layer on the second back surface of the core chip and a third bonding metal layer in the third bonding medium layer, the third bonding medium layer exposes a surface of the third bonding metal layer, and the third bonding metal layer is electrically connected with the second end of the second through-hole interconnection structure.

[0011] In some embodiments, the second hybrid bonding layers of the second active surfaces of the two core chips in each of the hybrid bonding units are bonded together at least by: in each of the hybrid bonding units, the second bonding medium layer of one core chip is bonded together with the second bonding medium layer of the other core chip, and the second bonding metal layer of one core chip is bonded together with the second bonding metal layer of the other core chip.

[0012] In some embodiments, the third hybrid bonding layers of the second back surfaces of the core chips in the upper hybrid bonding unit of the core chip group are bonded together with the corresponding third hybrid bonding layers of the second back surfaces of the core chips in the lower hybrid bonding unit at least by: the third bonding medium layer of one core chip in the upper hybrid bonding unit of the core chip group is bonded together with the third bonding medium layer of one core chip in the lower hybrid bonding unit, and the third bonding metal layer of one core chip in the upper hybrid bonding unit of the core chip group is bonded together with the third bonding metal layer of one core chip in the lower hybrid bonding unit.

[0013] In some embodiments, the bonding of the third hybrid bonding layer on the second back surface of the core chip of the bottommost hybrid bonding unit of the core chipset to the first hybrid bonding layer on the first active surface of the bottom chip at least includes: the third bonding medium layer of the core chip of the bottommost hybrid bonding unit of the core chipset is bonded to the first bonding medium layer in the first hybrid bonding layer on the first active surface of the bottom chip, and the third bonding metal layer of the core chip of the bottommost hybrid bonding unit of the core chipset is bonded to the first bonding metal layer of the bottom chip.

[0014] In some embodiments, both of the top chips have a third integrated circuit, and the second active surface of both of the top chips has a third pad electrically connected to the third integrated circuit, wherein one of the top chips further has a third through-hole interconnection structure including opposite first and second ends, the first end of the third through-hole interconnection structure is electrically connected to the third integrated circuit in the top chip, and the second back surface of the core chip exposes the second end of the second through-hole interconnection structure; the fourth hybrid bonding layer includes a fourth bonding medium layer on the third active surface of the top chip and a fourth bonding metal layer in the fourth bonding medium layer, the fourth bonding medium layer exposes the surface of the fourth bonding metal layer, and the fourth bonding metal layer is electrically connected to the third pad; the fifth hybrid bonding layer includes a fifth bonding medium layer on the third back surface of the top chip and a fifth bonding metal layer in the fifth bonding medium layer, the fifth bonding medium layer exposes the surface of the fifth bonding metal layer, and the fifth bonding metal layer is electrically connected to the second end of the third through-hole interconnection structure.

[0015] In some embodiments, the bonding of the fourth hybrid bonding layer on the third active surface of the two top chips of the top chipset at least includes: the fourth bonding medium layer of one of the top chips is bonded to the fourth bonding medium layer of the other top chip, and the fourth bonding metal layer of one of the top chips is bonded to the fourth bonding metal layer of the other top chip.

[0016] In some embodiments, the bonding together of the fifth hybrid bonding layer on the third back surface of one of the top chips in the top chip group and the third hybrid bonding layer on the second back surface of one of the core chips in the hybrid bonding unit of the topmost layer of the core chip group comprises at least: the fifth bonding medium layer of one of the top chips in the top chip group and the third bonding medium layer of one of the core chips in the hybrid bonding unit of the topmost layer of the core chip group are bonded together in correspondence; and the fifth bonding metal layer of one of the top chips in the top chip group and the third bonding metal layer of one of the core chips in the hybrid bonding unit of the topmost layer of the core chip group are bonded together in correspondence.

[0017] In some embodiments, the material of the first, second, third, fourth and fifth bonding medium layers is one of silicon oxide, titanium oxide or silicon carbon nitride, and the material of the first, second, third, fourth and fifth bonding metal layers is one of copper or titanium.

[0018] In some embodiments, the number of hybrid bonding units in the core chip group is at least one.

[0019] In some embodiments, the function of the bottom chip is the same as or different from the function of the core chip and the top chip.

[0020] In some embodiments, the bottom chip is a logic chip, and the core chip and the top chip are storage chips.

[0021] In some embodiments, further comprising: a plastic encapsulation layer encapsulating the core chip group and the top chip group; a redistribution layer on the first back surface of the bottom chip; and micro solder bumps on the redistribution layer and electrically connected to the redistribution layer.

[0022] In some embodiments, further comprising: a conversion board or substrate, the micro solder bumps are soldered on the conversion board or substrate, and the bottom chip is electrically connected to the conversion board or substrate.

[0023] The beneficial effects of the present application are:

[0024] The three-dimensional stacked packaging structure provided by the application comprises a bottom chip, a core chip group on a first active surface of the bottom chip, and a top chip group on a top surface of the core chip group. The first hybrid bonding layer in the bottom chip and the third hybrid bonding layer on the second back surface of one core chip of the hybrid bonding unit in the bottom layer of the core chip group are hybrid bonded together. Compared with the micro-bump interconnection mode, the hybrid bonding mode reduces the interconnection distance between the bottom layer of the core chip group and the bottom chip, thereby reducing the overall thickness of the three-dimensional stacked packaging structure, and more layers of chips (core chips) can be stacked, thereby improving the performance of the three-dimensional stacked packaging structure (such as realizing a larger capacity HBM (High Bandwidth Memory) three-dimensional stacked packaging structure).

[0025] Furthermore, the core chip group comprises two core chips with active surfaces bonded together in each hybrid bonding unit. On the one hand, the hybrid bonding unit is formed by hybrid bonding of the two core chips with active surfaces arranged oppositely, and the hybrid bonding unit can be mass-produced by a specific wafer-level manufacturing process, thereby improving the manufacturing efficiency of the hybrid bonding unit. The hybrid bonding unit is hybrid bonded after alignment of the two second wafers, thereby realizing simultaneous hybrid bonding of a plurality of hybrid bonding units on the two second wafers, improving the bonding accuracy and yield, and improving the bonding efficiency. On the other hand, when the three-dimensional stacked packaging structure has the same number of core chips, the number of stacking is halved when the hybrid bonding unit is stacked (for example, when six core chips are stacked, six times of stacking are required, and when six core chips are stacked in the application, only three times of stacking are required). The reduction of the number of stacking improves the accuracy of stacking, thereby further improving the yield and efficiency of bonding. On the other hand, the hybrid bonding unit is hybrid bonded together between the upper and lower hybrid bonding units and between the bottom layer of the hybrid bonding unit and the bottom chip. Compared with the micro-bump interconnection mode, the hybrid bonding mode reduces the interconnection distance between the core chips and between the bottom layer of the core chip and the bottom chip, thereby reducing the overall thickness of the three-dimensional stacked packaging structure, and more layers of chips (core chips) can be stacked, thereby improving the performance of the three-dimensional stacked packaging structure (such as realizing a larger capacity HBM (High Bandwidth Memory) three-dimensional stacked packaging structure).

[0026] And the top chip set includes two top chips with active surfaces bonded together, on the one hand, the top chip set is formed by hybrid bonding of two top chips with active surfaces, which can be mass produced by a specific wafer level manufacturing process, improving the manufacturing efficiency of the top chip set, and the wafer level manufacturing process is hybrid bonded after alignment of two third wafers, that is, the hybrid bonding of several top chip sets on two third wafers is realized at the same time, which improves the bonding accuracy and bonding yield, and improves the bonding efficiency; on the other hand, the two top chips in the top chip set and the top chip in the top chip set and the top core chip in the core chip set are bonded together by hybrid bonding, compared with the micro-bump interconnection mode, the interconnection distance between the top chips and the top chip in the top chip set and the top core chip in the core chip set is reduced, thereby reducing the overall thickness of the three-dimensional stacked packaging structure, so that more layers of chips (core chips) can be stacked, thereby improving the performance of the three-dimensional stacked packaging structure (such as realizing a larger capacity HBM (High Bandwidth Memory) three-dimensional stacked packaging structure). BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 Structure diagram of a three-dimensional stacked packaging structure in some embodiments of the present application;

[0028] Figure 2 Structure diagram of a bottom chip in a three-dimensional stacked packaging structure in some embodiments of the present application;

[0029] Figure 3 Structure diagram of a hybrid bonding unit in a three-dimensional stacked packaging structure in some embodiments of the present application;

[0030] Figure 4 Structure diagram of a top chip set in a three-dimensional stacked packaging structure in some embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0032] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0033] A three-dimensional stacked packaging structure is provided in the embodiments of the present application. Figure 1 A structural schematic diagram of a three-dimensional stacked packaging structure in some embodiments of the present application is shown in the figure. Figure 2 A structural schematic diagram of a bottom chip in a three-dimensional stacked packaging structure in some embodiments of the present application is shown in the figure. Figure 3 A structural schematic diagram of a hybrid bonding unit in a three-dimensional stacked packaging structure in some embodiments of the present application is shown in the figure. Figure 4 A structural schematic diagram of a top chip group in a three-dimensional stacked packaging structure in some embodiments of the present application is shown in the figure.

[0034] Reference is made to Figure 1 , and in combination with reference Figures 2-4 , the three-dimensional stacked packaging structure comprises:

[0035] a bottom chip 100 (reference Figure 1 or Figure 2 ), the bottom chip 100 comprises a first active surface and a first back surface opposite to each other, and the first active surface is provided with a first hybrid bonding layer (106, 107);

[0036] a core chip group 20 located on the first active surface of the bottom chip 100, the core chip group 20 comprises a plurality of hybrid bonding units 21 (reference Figure 1 or Figure 3Each of the hybrid bonding units 21 includes two core chips 200 with their active surfaces bonded together. Each core chip 200 includes a second active surface and a second back surface. The second active surface has a second hybrid bonding layer (206, 207), and the second back surface has a third hybrid bonding layer (210, 211). The second hybrid bonding layers (206, 207) of the second active surfaces of the two core chips 200 in each hybrid bonding unit 21 are bonded together accordingly, and the upper layer of the core chip group 20... The third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the hybrid bonding unit 21 is bonded to the corresponding third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the lower hybrid bonding unit 21. The third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the lowest hybrid bonding unit 21 of the core chip group 20 is bonded to the first hybrid bonding layer (106, 107) on the first active surface of the bottom chip 100.

[0037] Top chipset 30 (reference) located on the top surface of the core chipset 20 Figure 1 or Figure 4 The top chipset 30 includes two top chips 300 with their active surfaces bonded together. Each of the two top chips 300 includes a third active surface and a third back surface. The third active surfaces of both top chips 300 have a fourth hybrid bonding layer (306, 307). The third back surface of one of the top chips 300 has a fifth hybrid bonding layer (310, 311). The fourth hybrid bonding layers (306, 307) on the third active surfaces of the two top chips 300 are bonded together. The fifth hybrid bonding layer (310, 311) on the third back surface of one of the top chips 300 in the top chipset 30 is bonded to the third hybrid bonding layer (210, 211) on the second back surface of one of the core chips 200 in the topmost hybrid bonding unit 21 of the core chipset 20.

[0038] Specifically, there is one bottom chip 100, and the size of the bottom chip 100 is equal to or greater than the size of the core chip 300 and the top chip 300.

[0039] In some embodiments, the bottom chip 100 can have different functions from the core chip 200 and the top chip 300, for example, the bottom chip 100 is a logic chip, and the core chip 200 and the top chip 300 are storage chips. The logic chip is used to control the data storage process of the storage chip, and can also be used to control the data transmission and / or communication process between the three-dimensional stacked package structure and other package structures, substrates or other chips outside. In other embodiments, the bottom chip 100 can have the same functions as the core chip 200 and the top chip 300, for example, the bottom chip 100, the core chip 200 and the top chip 300 can all be storage chips.

[0040] In some embodiments, the logic chip can include but is not limited to a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a micro processing unit (MPU), a micro controller unit (MCU), a logic integrated circuit (IC), an application processor (AP). The storage chip can include but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase change memory (PRAM), resistive random access memory (RRAM) or non-volatile storage chip (such as flash memory).

[0041] In some embodiments, the bottom chip 100 has a first integrated circuit (not shown in the figure, for example, the first integrated circuit can be a logic control circuit or a storage circuit) and a first through-hole interconnection structure 103. The first integrated circuit is electrically connected to the first through-hole interconnection structure 103. The first through-hole interconnection structure 103 includes opposite first and second ends. The second end of the first through-hole interconnection structure 103 is exposed on the first back surface of the bottom chip 100. The first active surface of the bottom chip 100 has a first pad 104, and the first pad 104 is electrically connected to the first end of the first through-hole interconnection structure 103.

[0042] In some embodiments, the bottom chip 100 may further include a first semiconductor substrate 101, a first interlayer dielectric layer 102 located on the upper surface of the first semiconductor substrate 101, and the first integrated circuit (not shown) may include a plurality of first semiconductor devices (not shown) located in and on the upper surface of the first semiconductor substrate 101, and a first circuit layer (not shown) located in the first interlayer dielectric layer 102 that electrically connects the plurality of first semiconductor devices. In some embodiments, the material of the first semiconductor substrate 101 may be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds. The first interlayer dielectric layer 102 can be a single-layer or multi-layer stacked structure. Specifically, the first interlayer dielectric layer 102 can be a single-layer structure formed by one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant material (K less than 2.5), or a multilayer structure formed by two or more materials from the group consisting of the above materials. The first circuit layer can include one or more of the following: metal circuits, metal plugs, and damask interconnect structures. Corresponding to the number of layers in the first interlayer dielectric layer 102, the first circuit layer can also be a single-layer or multi-layer stacked structure. The material of the first circuit layer can be one or more of the following: Al, Cu, W, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In some embodiments, the first semiconductor device may include a transistor or a memory cell, wherein the transistor may be one or more of a bipolar junction transistor (BJT), a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a Fin Field-Effect Transistor (FFET), an insulated-gate bipolar transistor (IGBT), or a nanowire transistor. In other embodiments, the first semiconductor device may further include a passive device, which may be one or more of a diode, a resistor, a capacitor, and an inductor.In some embodiments, the first pad 104 is located in the first interlayer dielectric layer 102, and the upper surface of the first interlayer dielectric layer 102 exposes the upper surface of the first pad 104. The first pad 104 is electrically connected to the first circuit layer. The first via interconnect structure 103 can be a through silicon via (TSV) interconnect structure. The first via interconnect structure 103 is formed in the first semiconductor substrate 101, or the first via interconnect structure 103 can be formed in the first semiconductor substrate 101 and a portion thereof may also be formed in the first interlayer dielectric layer 102. The materials of the first pad 104 and the first via interconnect structure 103 can be one or more of Al, Cu, W, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0043] The first hybrid bonding layer (106, 107) includes a first bonding dielectric layer 106 located on the first active surface of the bottom chip 100 and a first bonding metal layer 107 located in the first bonding dielectric layer 106. The first bonding dielectric layer 106 exposes the surface of the first bonding metal layer 107, and the first bonding metal layer 107 is electrically connected to the first pad 104. (It should be noted that, for ease of drawing, ...) Figure 1 and Figure 2 The first integrated circuit in the bottom chip 100 is not shown, and the first through-hole interconnect structure 103 and the first pad 104 are electrically connected to the first integrated circuit. Figure 1 and Figure 2 The diagram illustrates direct contact between the first through-hole interconnect structure 103 and the first pad 104. Furthermore, the drawing process for the core chip 200 and the top chip 300 is similar and will not be described further.

[0044] The first hybrid bonding layer (106, 107) in the bottom chip 100 is used to hybrid bond together with the third hybrid bonding layer (210, 211) on the second back side of a core chip 200 of the bottommost hybrid bonding unit 21 in the core chipset 20 during the formation of a three-dimensional stacked package structure. Specifically, the first bonding dielectric layer 106 and the first bonding metal layer 107 in the first hybrid bonding layer (106, 107) of the bottom chip 100 are hybrid bonded together with the third bonding layer (210, 211) on the second back side of a core chip 200 of the bottommost hybrid bonding unit 21 in the core chipset 20. The bonding dielectric layer 210 and the third bonding metal layer 211 are mixed-bonded (the mixed bonding includes at least the first bonding dielectric layer 106 being bonded to the third bonding dielectric layer 210, and the first bonding metal layer 107 being bonded to the third bonding metal layer 211). This mixed bonding method reduces the interconnection distance between the core chip 200 and the bottom chip 100 compared to the microbump interconnect method, thereby reducing the overall thickness of the three-dimensional stacked package structure. As a result, more layers of chips (core chips) can be stacked, thereby improving the performance of the three-dimensional stacked package structure (such as realizing a larger capacity HBM (High Bandwidth Memory) three-dimensional stacked package structure).

[0045] In some embodiments, the thickness of the first bonding dielectric layer 106 is 0.1 μm to 0.5 μm, the material of the first bonding dielectric layer 106 is one of silicon oxide (SiO2), titanium oxide (TiO2) or silicon carbide (SiCN), and the material of the first bonding metal layer 107 is one of copper (Cu) or titanium (Ti).

[0046] In some embodiments, a first sub-dielectric layer 105 is further provided between the first interlayer dielectric layer 103 and the first bonding dielectric layer 106. The first sub-dielectric layer 105 provides a flat surface for forming the first bonding dielectric layer 106, thereby making the formed first bonding dielectric layer 106 have a flat surface, which is beneficial to improving the bonding strength of the hybrid bonding. The material of the first sub-dielectric layer 105 can be silicon oxide or silicon nitride, and the thickness of the first sub-dielectric layer 105 can be 0.5 μm to 2 μm. The first bonding metal layer 107 is located not only in the first bonding dielectric layer 106, but also partially located in the first sub-dielectric layer 105.

[0047] In some embodiments, the device further includes: a redistribution layer on a first back surface of the bottom chip 100, the redistribution layer including a passivation layer 108 on the first back surface of the bottom chip 100 and metal wiring 109 in the passivation layer 108, the passivation layer 108 being made of an inorganic or organic material, and the metal wiring 109 being made of a metal; and micro-welding protrusions 110 located on the redistribution layer and electrically connected to the redistribution layer (electrically connected to the metal wiring 109 in the redistribution layer).

[0048] Continue to refer to Figure 1 In the core chipset 20, a plurality of hybrid bonding units 21 are stacked sequentially along a direction perpendicular to the first active surface of the bottom chip 100. Specifically, the number of hybrid bonding units 21 in the core chipset 20 is at least one or more. Figure 1 The three-dimensional stacked packaging structure is used as an example to illustrate the core chipset 20, which has three hybrid bonding units 21.

[0049] Continue to refer to Figure 1 In conjunction with references Figure 3Each of the hybrid bonding units 21 includes two core chips 200 with their active surfaces bonded together. Each core chip 200 includes a second active surface and a second back surface. The second active surface has a second hybrid bonding layer (206, 207), and the second back surface has a third hybrid bonding layer (210, 211). The second hybrid bonding layers (206, 207) of the second active surfaces of the two core chips 200 in each hybrid bonding unit 21 are bonded together accordingly. The core chip group 20... The third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the hybrid bonding unit 21 of the lower layer is bonded to the corresponding third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the hybrid bonding unit 21 of the lower layer. The third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the lowest layer of the hybrid bonding unit 21 of the core chip group 20 is bonded to the first hybrid bonding layer (106, 107) on the first active surface of the bottom chip 100. On the one hand, each of the aforementioned specific hybrid bonding units 21 is formed by hybrid bonding of two core chips 200 with their active surfaces facing each other. These hybrid bonding units 21 can be mass-produced using a specific wafer-level fabrication process (detailed later), improving the fabrication efficiency of the hybrid bonding units 21. Furthermore, the wafer-level fabrication process involves aligning two second wafers before hybrid bonding of the hybrid bonding units 21, achieving simultaneous hybrid bonding of several hybrid bonding units 21 on two second wafers. This improves bonding accuracy and yield while also increasing bonding efficiency. On the other hand, since the core chip group 20 is formed by sequentially stacking several hybrid bonding units 21 along a direction perpendicular to the first active surface of the bottom chip 100, when the three-dimensional stacked packaging structure has the same number of core chips, the use of hybrid bonding units 21 in this application... The number of stacking operations is halved (for example, stacking 6 core chips requires 6 stacking operations, while stacking 6 core chips in this application only requires 3 stacking operations). The reduction in the number of stacking operations improves the stacking accuracy, further improving the bonding yield and bonding efficiency. On the other hand, the hybrid bonding units 21 of the upper and lower layers, as well as the bottom layer hybrid bonding unit 21 and the bottom chip 100, are bonded together by hybrid bonding. Compared with the micro-bump interconnection method, this hybrid bonding method reduces the interconnection spacing between core chips 200 and between the bottom layer core chip 200 and the bottom chip 100, thereby reducing the overall thickness of the three-dimensional stacked package structure. Therefore, more layers of chips (core chips) can be stacked, thereby improving the performance of the three-dimensional stacked package structure (such as realizing a larger capacity HBM (High Bandwidth Memory) three-dimensional stacked package structure).

[0050] In some embodiments, each of the core chips 200 has a second integrated circuit (not shown in the figure, for example, the second integrated circuit can store circuits) and a second via interconnect structure 203. The second via interconnect structure 203 is electrically connected to the second integrated circuit. The second via interconnect structure 203 includes a first end and a second end opposite to each other. The second back side of the core chip 200 exposes the second end of the second via interconnect structure 203. The second active surface of the core chip 200 has a second pad 204. The second pad 204 is electrically connected to the first end of the second via interconnect structure 203.

[0051] In some embodiments, the core chip 200 may further include a second semiconductor substrate 201, a second interlayer dielectric layer 202 located on the upper surface of the second semiconductor substrate 201, and the second integrated circuit (not shown in the figure) may include a plurality of second semiconductor devices (not shown in the figure) located in and on the upper surface of the second semiconductor substrate 201, and a second circuit layer (not shown in the figure) located in the second interlayer dielectric layer 202 to electrically connect the plurality of second semiconductor devices. In some embodiments, the material of the second semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds. The second interlayer dielectric layer 202 can be a single-layer or multi-layer stacked structure. Specifically, the second interlayer dielectric layer 202 can be a single-layer structure formed by one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant material (K less than 2.5), or a multilayer structure formed by two or more materials from the group consisting of the above materials. The second circuit layer can include one or more of the following: metal circuits, metal plugs, and damask interconnect structures. Corresponding to the number of layers in the second interlayer dielectric layer 202, the second circuit layer can also be a single-layer or multi-layer stacked structure. The material of the second circuit layer can be one or more of the following: Al, Cu, W, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In some embodiments, the second semiconductor device can be a memory cell of a memory. In some embodiments, the second pad 204 is located in the second interlayer dielectric layer 202, and the upper surface of the second interlayer dielectric layer 202 exposes the upper surface of the second pad 204. The second pad 204 is electrically connected to the second circuit layer. The second via interconnect structure 203 can be a through silicon via (TSV) interconnect structure. The second via interconnect structure 203 is formed in the second semiconductor substrate 201, or in addition to being formed in the second semiconductor substrate 201, a portion of the second via interconnect structure 203 may also be formed in the second interlayer dielectric layer 202. The materials of the second pad 204 and the second via interconnect structure 203 can be one or more of Al, Cu, W, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0052] The second hybrid bonding layer (206, 207) includes a second bonding dielectric layer 206 located on the second active surface of the core chip 200 and a second bonding metal layer 207 located in the second bonding dielectric layer 206. The second bonding dielectric layer 206 exposes the surface of the second bonding metal layer 207, and the second bonding metal layer 207 is electrically connected to the second pad 204. The third hybrid bonding layer (210, 211) includes a third bonding dielectric layer 210 located on the second back surface of the core chip 200 and a third bonding metal layer 211 located in the third bonding dielectric layer 210. The third bonding dielectric layer 210 exposes the surface of the third bonding metal layer 211, and the third bonding metal layer 211 is electrically connected to the second end of the second via interconnect structure 203.

[0053] In some embodiments, the second hybrid bonding layers (206, 207) of the second active surfaces of the two core chips 200 in each hybrid bonding unit 21 are bonded together, including at least the following: in each hybrid bonding unit 21, the second bonding medium layer 206 of one core chip 200 is bonded together with the second bonding medium layer 206 of the other core chip 200, and the second bonding metal layer 207 of one core chip 200 is bonded together with the second bonding metal layer 207 of the other core chip 200.

[0054] In some embodiments, the bonding of the third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the upper hybrid bonding unit 21 of the core chipset 20 with the corresponding third hybrid bonding layer (210, 211) on the second back side of a core chip 200 in the lower hybrid bonding unit 21 includes at least the following: the third bonding medium layer 210 of the core chip 200 in the upper hybrid bonding unit 21 of the core chipset 20 is correspondingly bonded to the third bonding medium layer 210 of the core chip 200 in the lower hybrid bonding unit 21, and the third bonding metal layer 211 of the core chip 200 in the upper hybrid bonding unit 21 of the core chipset 20 is correspondingly bonded to the third bonding metal layer 211 of the core chip 200 in the lower hybrid bonding unit 21.

[0055] In some embodiments, the bonding of the third hybrid bonding layer (210, 211) on the second back side of a core chip 200 of the bottommost hybrid bonding unit 21 of the core chipset 20 to the first hybrid bonding layer (106, 107) on the first active surface of the bottom chip 100 includes at least the following: the third bonding dielectric layer 210 of the core chip 200 of the bottommost hybrid bonding unit 21 of the core chipset 20 is correspondingly bonded to the first bonding dielectric layer 106 of the bottom chip 100, and the triple bonding metal layer 211 in the third hybrid bonding layer (210, 211) on the second back side of the core chip 200 of the bottommost hybrid bonding unit 21 of the core chipset 20 is correspondingly bonded to the first bonding metal layer 107 of the bottom chip 100.

[0056] In some embodiments, the thickness of the second bonding dielectric layer 206 and the third bonding dielectric layer 210 is 0.1 μm to 0.5 μm, the material of the second bonding dielectric layer 206 and the third bonding dielectric layer 210 is one of silicon oxide (SiO2), titanium oxide (TiO2) or silicon carbide (SiCN), and the material of the third bonding metal layer 207 and the third bonding metal layer 211 is one of copper (Cu) or titanium (Ti).

[0057] In some embodiments, a third sub-dielectric layer 205 is further provided between the second interlayer dielectric layer 203 and the second bonding dielectric layer 206. The third sub-dielectric layer 205 provides a flat surface for forming the second bonding dielectric layer 206, thereby ensuring a flat surface in the formed second bonding dielectric layer 206, which is beneficial for improving the bonding strength of the mixed bonding. The material of the third sub-dielectric layer 205 can be silicon oxide or silicon nitride, and the thickness of the third sub-dielectric layer 205 can be 0.5 μm to 2 μm. The second bonding metal layer 207 is located not only in the second bonding dielectric layer 206 but also partially in the third sub-dielectric layer 205.

[0058] In some embodiments, a fifth sub-dielectric layer 209 is further provided between the second back surface of the core chip 200 and the third bonding dielectric layer 210. The fifth sub-dielectric layer 209 provides a flat surface for forming the third bonding dielectric layer 210, thereby making the formed third bonding dielectric layer 210 have a flat surface, which is beneficial to improving the bonding strength of the hybrid bonding. The material of the fifth sub-dielectric layer 209 can be silicon oxide or silicon nitride, and the thickness of the fifth sub-dielectric layer 209 can be 0.5µm to 2µm. The third bonding metal layer 211 is located not only in the third bonding dielectric layer 210 but also partially in the fifth sub-dielectric layer 209. In some embodiments, a passivation protection layer 208 may also be provided between the second back surface of the core chip 200 and the fifth sub-dielectric layer 209. The passivation protection layer 208 serves as a stop layer during the chemical mechanical polishing of the back surface of the second wafer when forming the core chip, so as to form a flat second back surface.

[0059] Continue to refer to Figure 1 and Figure 4The top chipset 30 is located on the top surface of the core chipset 20. The top chipset 30 includes two top chips 300 with their active surfaces bonded together. The number of top chipsets 30 is one. The top chipset 30 includes two top chips 300 with their active surfaces bonded together. Each of the two top chips 300 includes a third active surface and a third back surface. The third active surfaces of both top chips 300 have a fourth hybrid bonding layer (306, 307). The third back surface of one of the top chips 300 has a fifth hybrid bonding layer (310, 311). The fourth hybrid bonding layers (306, 307) on the third active surfaces of the two top chips 300 are bonded together. The fifth hybrid bonding layer (310, 311) on the third back surface of one of the top chips 300 in the top chipset 30 is bonded to the third hybrid bonding layer (210, 211) on the second back surface of one of the core chips 200 in the topmost hybrid bonding unit 21 of the core chipset 20. On the one hand, the top chip group 30 is formed by bonding two top chips 300 with their active surfaces facing each other. This top chip group 30 can be mass-produced using a specific wafer-level fabrication process (detailed later), improving the fabrication efficiency. Furthermore, the wafer-level fabrication process involves aligning and bonding two third wafers during the bonding process, achieving simultaneous bonding of multiple top chip groups 30 on two third wafers. This improves bonding accuracy and yield while also increasing bonding efficiency. On the other hand, the top chips 300 within the top chip group 30 are bonded together with each other. In the chipset 30, a top chip 300 is bonded to the top core chip 200 of the core chipset 20 using a hybrid bonding method. Compared to microbump interconnects, this hybrid bonding method reduces the interconnection spacing between the top chips 300 and between the top chip 300 in the top chipset 300 and the top core chip 200 in the core chipset 20, thereby reducing the overall thickness of the three-dimensional stacked package structure. This allows for the stacking of more layers of chips (core chips), thus improving the performance of the three-dimensional stacked package structure (e.g., enabling larger capacity HBM (High Bandwidth Memory) three-dimensional stacked package structures).

[0060] In some embodiments, both top chips 300 have a third integrated circuit (not shown in the figure, for example, the second integrated circuit can store circuits), and the second active surfaces of both top chips 300 have a third pad 304, which is electrically connected to the third integrated circuit. One of the top chips 300 also has a third via interconnect structure 303, which includes a first end and a second end opposite to each other. The first end of the third via interconnect structure 303 is electrically connected to the third integrated circuit in the top chip 300, and the second back side of the core chip 200 exposes the second end of the second via interconnect structure 203.

[0061] In some embodiments, the top chip 300 may further include a third semiconductor substrate 301, a third interlayer dielectric layer 302 located on the upper surface of the third semiconductor substrate 301, and the third integrated circuit (not shown) may include a plurality of third semiconductor devices (not shown) located in and on the upper surface of the third semiconductor substrate 301, and a third circuit layer (not shown) located in the third interlayer dielectric layer 302 electrically connecting the plurality of third semiconductor devices. In some embodiments, the third pad 304 is located in the third interlayer dielectric layer 302, and the upper surface of the third interlayer dielectric layer 302 exposes the upper surface of the third pad 304, and the third pad 304 is electrically connected to the third circuit layer. The third via interconnect structure 303 may be a through silicon via (TSV) interconnect structure, and the third via interconnect structure 303 may be formed in the third semiconductor substrate 301, or the third via interconnect structure 303 may be formed in the third semiconductor substrate 301 and a portion thereof in the third interlayer dielectric layer 302.

[0062] The fourth hybrid bonding layer (306, 307) includes a fourth bonding dielectric layer 306 located on the third active surface of the top chip 300 and a fourth bonding metal layer 307 located in the fourth bonding dielectric layer 306. The fourth bonding dielectric layer 306 exposes the surface of the fourth bonding metal layer 307, and the fourth bonding metal layer 307 is electrically connected to the third pad 304. The fifth hybrid bonding layer (310, 311) includes a fifth bonding dielectric layer 310 located on the third back surface of the top chip 300 and a fifth bonding metal layer 311 located in the fifth bonding dielectric layer 310. The fifth bonding dielectric layer 310 exposes the surface of the fifth bonding metal layer 311, and the fifth bonding metal layer 311 is electrically connected to the second end of the third via interconnect structure 303.

[0063] In some embodiments, the fourth hybrid bonding layers (306, 307) of the third active surfaces of the two top chips 300 of the top chipset 30 are bonded together, including at least the following: in the top chipset 30, the fourth bonding dielectric layer 306 of one top chip 300 is bonded together with the fourth bonding dielectric layer 306 of the other top chip 300, and the fourth bonding metal layer 307 of one top chip 300 is bonded together with the fourth bonding metal layer 307 of the other top chip 300.

[0064] In some embodiments, the bonding of the fifth hybrid bonding layer (310, 311) on the third back side of one of the top chips 300 in the top chipset 30 to the third hybrid bonding layer (210, 211) on the second back side of one of the core chips 200 in the top hybrid bonding unit 21 of the core chipset 20 includes at least the following: the fifth bonding medium layer 310 of one of the top chips 300 in the top chipset 30 is correspondingly bonded to the third bonding medium layer 210 of one of the core chips 200 in the top hybrid bonding unit 21 of the core chipset 20, and the fifth bonding metal layer 311 of one of the top chips 300 in the top chipset 30 is correspondingly bonded to the third bonding metal layer 211 of one of the core chips 200 in the top hybrid bonding unit 21 of the core chipset 20.

[0065] In some embodiments, the thickness of the fourth bonding dielectric layer 306 and the fifth bonding dielectric layer 310 is 0.1 μm to 0.5 μm, the material of the fourth bonding dielectric layer 306 and the fifth bonding dielectric layer 310 is one of silicon oxide (SiO2), titanium oxide (TiO2) or silicon carbide (SiCN), and the material of the fourth bonding metal layer 307 and the fourth bonding metal layer 311 is one of copper (Cu) or titanium (Ti).

[0066] In some embodiments, a seventh sub-dielectric layer 305 is further provided between the third interlayer dielectric layer 303 and the fourth bonding dielectric layer 306. The seventh sub-dielectric layer 305 provides a flat surface for forming the fourth bonding dielectric layer 306, thereby giving the formed fourth bonding dielectric layer 306 a flat surface, which is beneficial for improving the bonding strength of the mixed bonding. The material of the seventh sub-dielectric layer 305 can be silicon oxide or silicon nitride, and the thickness of the seventh sub-dielectric layer 305 can be 0.5µm to 2µm. The fourth bonding metal layer 307 is located not only in the fourth bonding dielectric layer 306 but also partially in the seventh sub-dielectric layer 305.

[0067] In some embodiments, one of the top chips 300 (such as...) Figure 4A ninth sub-dielectric layer 309 is further provided between the second back side of the top chip 300 (below) and the fifth bonding dielectric layer 310. The ninth sub-dielectric layer 309 provides a flat surface for forming the fifth bonding dielectric layer 310, thereby making the formed fifth bonding dielectric layer 310 have a flat surface, which is beneficial to improving the bonding strength of the mixed bonding. The material of the ninth sub-dielectric layer 309 can be silicon oxide or silicon nitride, and the thickness of the ninth sub-dielectric layer 309 can be 0.5um to 2um. The fifth bonding metal layer 311 is located not only in the fifth bonding dielectric layer 310, but also partially in the ninth sub-dielectric layer 309. In some embodiments, a passivation protection layer 308 may also be provided between the third back side of the top chip 300 and the ninth sub-dielectric layer 309. The passivation protection layer 308 serves as a stop layer when chemically mechanically polishing the back side of the third wafer during the formation of the top chip 300, so as to form a flat third back side.

[0068] In one embodiment, reference continues Figure 1 The three-dimensional stacked packaging structure further includes a molding compound 118 covering the core chipset 200 and the top chipset 300 to protect the core chip 200 and the top chip 300. The molding compound 118 may or may not expose the upper surface of the top chipset 30. In some embodiments, the material of the molding compound 118 may be a filler-containing epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin; or it may be a filler-containing polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol. In some embodiments, the filler may be an inorganic filler or an organic filler. In some embodiments, the process of forming the molding compound 118 includes compression molding or transfer molding.

[0069] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A three-dimensional stacked packaging structure, characterized in that, include: A bottom chip, the bottom chip including a first active surface and a first back surface opposite to each other, the first active surface having a first hybrid bonding layer; A core chip group located on the first active surface of the bottom chip includes a plurality of hybrid bonding units stacked sequentially along a direction perpendicular to the first active surface of the bottom chip. Each hybrid bonding unit includes two core chips with their active surfaces bonded together. Each core chip includes a second active surface and a second back surface with opposite surfaces. The second active surface has a second hybrid bonding layer, and the second back surface has a third hybrid bonding layer. The second hybrid bonding layers of the second active surfaces of the two core chips in each hybrid bonding unit are bonded together accordingly. Furthermore, the third hybrid bonding layer of the second back surface of one core chip in the upper hybrid bonding unit of the core chip group is bonded together with the corresponding third hybrid bonding layer of the second back surface of one core chip in the lower hybrid bonding unit. The third hybrid bonding layer of the second back surface of one core chip in the lowest hybrid bonding unit of the core chip group is bonded together with the first hybrid bonding layer of the first active surface of the bottom chip. A top chipset located on the top surface of the core chipset includes two top chips with their active surfaces bonded together. Each of the two top chips includes a third active surface and a third back surface. Both top chips have a fourth hybrid bonding layer on their third active surfaces, and one of the top chips has a fifth hybrid bonding layer on its third back surface. The fourth hybrid bonding layers on the third active surfaces of the two top chips are bonded together accordingly, and the fifth hybrid bonding layer on the third back surface of one of the top chips in the top chipset is bonded to the third hybrid bonding layer on the second back surface of one of the core chips in the topmost hybrid bonding unit of the core chipset.

2. The three-dimensional stacked packaging structure according to claim 1, characterized in that, The bottom chip has a first integrated circuit and a first through-hole interconnect structure. The first through-hole interconnect structure is electrically connected to the first integrated circuit. The first through-hole interconnect structure includes a first end and a second end opposite to each other. The second end of the first through-hole interconnect structure is exposed on the first back side of the bottom chip. The first active surface of the bottom chip has a first pad. The first pad is electrically connected to the first end of the first through-hole interconnect structure. The first hybrid bonding layer includes a first bonding dielectric layer located on the first active surface of the bottom chip and a first bonding metal layer located in the first bonding dielectric layer. The first bonding dielectric layer exposes the surface of the first bonding metal layer. The first bonding metal layer is electrically connected to the first pad.

3. The three-dimensional stacked packaging structure according to claim 2, characterized in that, Each of the core chips has a second integrated circuit and a second via interconnect structure. A first end of the second via interconnect structure is electrically connected to the second integrated circuit. The second via interconnect structure includes a first end and a second end opposite to each other. The second back side of the core chip exposes the second end of the second via interconnect structure. The second active surface of the core chip has a second pad, which is electrically connected to the first end of the second via interconnect structure. The second hybrid bonding layer includes a second bonding dielectric layer located on the second active surface of the core chip and a second bonding metal layer located within the second bonding dielectric layer. The second bonding dielectric layer exposes the surface of the second bonding metal layer, and the second bonding metal layer is electrically connected to the second pad. The third hybrid bonding layer includes a third bonding dielectric layer located on the second back side of the core chip and a third bonding metal layer located within the third bonding dielectric layer. The third bonding dielectric layer exposes the surface of the third bonding metal layer, and the third bonding metal layer is electrically connected to the second end of the second via interconnect structure.

4. The three-dimensional stacked packaging structure according to claim 3, characterized in that, The second hybrid bonding layers of the second active surfaces of the two core chips in each hybrid bonding unit are bonded together, including at least the following: in each hybrid bonding unit, the second bonding medium layer of one core chip is bonded together with the second bonding medium layer of another core chip, and the second bonding metal layer of one core chip is bonded together with the second bonding metal layer of another core chip.

5. The three-dimensional stacked packaging structure according to claim 3, characterized in that, The bonding of the third hybrid bonding layer on the second back side of a core chip in the upper hybrid bonding unit of the core chipset to the corresponding third hybrid bonding layer on the second back side of a core chip in the lower hybrid bonding unit includes at least the following: the third bonding medium layer of a core chip in the upper hybrid bonding unit of the core chipset is correspondingly bonded to the third bonding medium layer of a core chip in the lower hybrid bonding unit, and the third bonding metal layer of a core chip in the upper hybrid bonding unit of the core chipset is correspondingly bonded to the third bonding metal layer of a core chip in the lower hybrid bonding unit.

6. The three-dimensional stacked packaging structure according to claim 3, characterized in that, The bonding of the third hybrid bonding layer on the second back side of a core chip of the lowest hybrid bonding unit in the core chipset to the first hybrid bonding layer on the first active surface of the bottom chip includes at least the following: the third bonding dielectric layer of the core chip of the lowest hybrid bonding unit in the core chipset is correspondingly bonded to the first bonding dielectric layer in the first hybrid bonding layer on the first active surface of the bottom chip, and the third bonding metal layer of the core chip of the lowest hybrid bonding unit in the core chipset is correspondingly bonded to the first bonding metal layer of the bottom chip.

7. The three-dimensional stacked packaging structure according to claim 3, characterized in that, Both top chips have a third integrated circuit, and both top chips have a third pad on their second active surface. The third pad is electrically connected to the third integrated circuit. One of the top chips also has a third via interconnect structure, which includes a first end and a second end. The first end of the third via interconnect structure is electrically connected to the third integrated circuit in the top chip, and the second end of the second via interconnect structure is exposed on the second back side of the core chip. The fourth hybrid bonding layer includes a fourth bonding dielectric layer on the third active surface of the top chip and a fourth bonding metal layer in the fourth bonding dielectric layer. The fourth bonding dielectric layer exposes the surface of the fourth bonding metal layer, and the fourth bonding metal layer is electrically connected to the third pad. The fifth hybrid bonding layer includes a fifth bonding dielectric layer on the third back side of the top chip and a fifth bonding metal layer in the fifth bonding dielectric layer. The fifth bonding dielectric layer exposes the surface of the fifth bonding metal layer, and the fifth bonding metal layer is electrically connected to the second end of the third via interconnect structure.

8. The three-dimensional stacked packaging structure according to claim 7, characterized in that, The fourth hybrid bonding layers of the third active surfaces of the two top chips in the top chipset are bonded together, including at least the following: in the top chipset, the fourth bonding dielectric layer of one top chip is bonded together with the corresponding fourth bonding dielectric layer of the other top chip, and the fourth bonding metal layer of one top chip is bonded together with the corresponding fourth bonding metal layer of the other top chip.

9. The three-dimensional stacked packaging structure according to claim 7, characterized in that, The bonding of the fifth hybrid bonding layer on the third back side of one of the top chips in the top chipset to the third hybrid bonding layer on the second back side of one of the core chips in the top hybrid bonding unit of the core chipset includes at least the following: the fifth bonding dielectric layer of one of the top chips in the top chipset is correspondingly bonded to the third bonding dielectric layer of one of the core chips in the top hybrid bonding unit of the core chipset, and the fifth bonding metal layer of one of the top chips in the top chipset is correspondingly bonded to the third bonding metal layer of one of the core chips in the top hybrid bonding unit of the core chipset.

10. The three-dimensional stacked packaging structure according to claim 7, characterized in that, The materials of the first bonding dielectric layer, the second bonding dielectric layer, the third bonding dielectric layer, the fourth bonding dielectric layer, and the fifth bonding dielectric layer are silicon oxide, titanium oxide, or silicon carbide, and the materials of the first bonding metal layer, the second bonding metal layer, the third bonding metal layer, the fourth bonding metal layer, and the fifth bonding metal layer are copper or titanium.

11. The three-dimensional stacked packaging structure according to claim 1, characterized in that, The core chipset contains at least one hybrid bonding unit.

12. The three-dimensional stacked packaging structure according to claim 1, characterized in that, The bottom chip may have the same or different functions as the core chip and the top chip.

13. The three-dimensional stacked packaging structure according to claim 12, characterized in that, The bottom chip is a logic chip, and the core chip and the top chip are memory chips.

14. The three-dimensional stacked packaging structure according to claim 1, characterized in that, Also includes: A molding layer covering the core chipset and the top chipset; A redistribution layer located on the first back side of the bottom chip; Micro-welding protrusions located on and electrically connected to the redistribution layer.

15. The three-dimensional stacked packaging structure according to claim 14, characterized in that, Also includes: An adapter board or substrate, wherein the micro-welding protrusions are welded to the adapter board or substrate, and the bottom chip is electrically connected to the adapter board or substrate.

Images