Packaging structure and packaging method for correcting exposed position of vertical wire bonding
By employing a stepped chip stacking and trapezoidal interconnect bump packaging method in multi-chip packaging, the problem of vertical wire bonding position offset is solved, and the design flexibility and soldering reliability of interconnect bumps are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-13
AI Technical Summary
In multi-chip packaging, the positional accuracy of vertical wire bonding is difficult to control, especially under the impact of plastic encapsulation, which can easily lead to misalignment and open interconnection problems.
The packaging structure and method adopts a correction method for the exposed position of vertical wire bonding. By setting a stepped stacked chip group on the substrate, vertical wires are used to bond to the substrate. After wire bonding, the copper and nickel-tin-silver interconnect bumps with trapezoidal structure are formed by molding, grinding and electroplating. The packaging is completed by combining SMT technology.
It improves the design flexibility of interconnect bumps, reduces bridging short-circuit anomalies in subsequent welding processes, and achieves higher positioning accuracy and reliability.
Smart Images
Figure CN121666154A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, specifically to a packaging structure and method for correcting the exposed position of vertical wire bonding. Background Technology
[0002] In the existing multi-chip packaging technology system, although the introduction of vertical wire bonding process to replace electroplated copper pillars can greatly reduce process complexity and cost, the problem faced by wire bonding is that the spatial position accuracy of the metal wire is difficult to control, especially under the subsequent molding impact, the final position offset of the metal wire will increase.
[0003] Generally, under ideal conditions in terms of both process and materials, the exposed metal offset is typically controlled within ±25µm. This offset-induced open circuit can then be overcome by increasing the size of the interconnect bumps. Figure 1 As shown. Summary of the Invention
[0004] To overcome the shortcomings of the prior art, this invention provides a packaging structure and method for correcting the exposed position of vertical bonding wires, which greatly improves the design flexibility of interconnect bumps compared with the prior art.
[0005] To achieve the above objectives, a packaging structure for correcting the exposed position of vertical wire bonding is designed, comprising a substrate, characterized in that: the substrate is provided with a plurality of packaging units, each packaging unit including a stepped stacked chip group, each chip group being bonded to the substrate via a vertical lead; the end of the vertical lead near the substrate is connected to a bump.
[0006] The protrusions include protrusions and bumps. The protrusions are trapezoidal in shape, with one end connected to the vertical lead wire and the other end connected to the bump.
[0007] The protrusions are electroplated copper.
[0008] The bump is a rectangular structure plated with nickel and tin silver, and the other end of the bump is perpendicular to the other end of the protrusion.
[0009] A packaging method for correcting the exposed position of the vertical wire bonding in the packaging structure, the specific method is as follows: S1. Prepare a flat carrier plate with vertical continuity, and apply a layer of light-transmitting heat-sliding disassembly temporary bonding adhesive to the carrier plate. S2, with the functional side of the chip facing up, and referring to the alignment reference marks on the carrier board, stack and mount several chips onto the carrier board in a staggered manner; S3, vertical wire bonding is performed at the step position exposed on the functional surface of the chip; S4. After the wire bonding operation is completed, the entire multi-chipset is encapsulated, and the encapsulation height is higher than the wire height. S5. After the molding process is completed, use high-precision grinding equipment to horizontally grind the molded surface until all wire ends are exposed. S6, prepare trapezoidal copper structures on the polished molding surface and subsequently grow nickel and tin-silver; S7, use a hot slide bonder to remove the carrier board and clean the plastic-encapsulated wafer with hot slide adhesive; S8, cut the molded body into pieces to obtain the final wire bonding module; S9, the wire bonding module is mounted on the substrate by SMT to form a mounting module; S10, The mounting module is encapsulated to form a plastic-encapsulated module; S11 involves balling the plastic-encapsulated module and finally dicing it to form the product.
[0010] In step S1, the thermal sliding disassembly temperature is controlled at 200℃.
[0011] The specific process of step S6 is as follows: S61, first sputtering of the metal seed layer, then coating with positive photoresist; S62 utilizes adjustments to exposure energy and development time to achieve a photoresist structure with an inverted trapezoidal bottom and a nearly vertical upper section. S63, then copper plating is used to fill the inverted trapezoidal area, followed by nickel and tin-silver plating to fill the upper and middle vertical structures. S64, after removing the photoresist and metal seed layer, finally reflows to form interconnect bumps.
[0012] In step S61, the positive photoresist includes an upper photoresist and a lower photoresist. The lower photoresist is used to accelerate lateral etching to form an undercut, and the upper photoresist is used to define the pattern position. The thickness of the upper and lower photoresist layers is adjusted according to the circuit and tin-silver thickness. The thickness of the lower photoresist layer is in the range of 5~10um, and the thickness of the upper photoresist layer is in the range of 10~20um.
[0013] The defined shape is one or more combinations of trapezoids, rectangles, circles, and ellipses.
[0014] In step S9, SMT stands for Surface Mount Technology. The SMT process includes placement, reflow, and underfill.
[0015] Compared with the prior art, the present invention provides a packaging structure and packaging method for correcting the exposed position of vertical wire bonding. Interconnect bumps are grown in situ at the exposed position of the wire bonding metal. Based on a single patterning process, the bump size can be flexibly adjusted by the photomask, which can effectively improve the bridging and short circuit abnormalities in the subsequent soldering process. Attached Figure Description
[0016] Figure 1 A schematic diagram of the product structure utilizing existing technology.
[0017] Figure 2 This is a schematic diagram of a product structure utilizing the packaging method of the present invention.
[0018] Figure 3 This is a flowchart of the encapsulation method of the present invention.
[0019] Figure 4 This is a flowchart of step S6 in the present invention.
[0020] Figure 5 This is a schematic diagram of another embodiment of the present invention. Detailed Implementation
[0021] The present invention will now be further described with reference to the accompanying drawings.
[0022] like Figure 2 As shown, a packaging structure for correcting the exposed position of vertical wire bonding is provided. A plurality of packaging units are provided on the substrate 1. Each packaging unit includes a chip group 2 stacked in a stepped manner. Each chip group 2 is bonded to the substrate 1 through a vertical lead 3. The vertical lead 3 is connected to a bump at one end near the substrate 1.
[0023] The bumps include protrusions and bumps. Protrusion 4 has a trapezoidal structure. One end of protrusion 4 is connected to the vertical lead 3, and the other end of protrusion 5 is connected to the bump 6.
[0024] Protrusion 4 is made of electroplated copper.
[0025] The bump 6 is a rectangular structure plated with nickel and tin silver, and the other end of the bump 6 is perpendicular to the other end of the protrusion 4.
[0026] Because one end of the vertical wire bonding is suspended, the position of the subsequent exposed point is greatly affected by process conditions. For a vertical wire with a diameter of 25µm and a height of 700µm, it is currently very difficult to control the offset to within 20µm. This makes it impossible to directly and effectively rewire the solder points at the set exposed positions. Therefore, it is necessary to correct the position offset by using a large-area bottom connection and a small-area top connection.
[0027] This invention uses a circle with a lower area controlled at a diameter of 60 μm and an upper area restored to a circle with a diameter of 25 μm to complete the correction.
[0028] like Figure 3 As shown, a packaging method for correcting the exposed position of the vertical wire bonding in the packaging structure is as follows: S1. Prepare a flat carrier plate with vertical continuity, and apply a layer of light-transmitting heat-sliding disassembly temporary bonding adhesive to the carrier plate. S2, with the functional side of the chip facing up, and referring to the alignment reference marks on the carrier board, stack and mount several chips onto the carrier board in a staggered manner; S3, vertical wire bonding is performed at the step position exposed on the functional surface of the chip; S4. After the wire bonding operation is completed, the entire multi-chipset is encapsulated, and the encapsulation height is higher than the wire height. S5. After the molding process is completed, use high-precision grinding equipment to horizontally grind the molded surface until all wire ends are exposed. S6, prepare trapezoidal copper structures on the polished molding surface and subsequently grow nickel and tin-silver; S7, use a hot slide bonder to remove the carrier board and clean the plastic-encapsulated wafer with hot slide adhesive; S8, cut the molded body into pieces to obtain the final wire bonding module; S9, the wire bonding module is mounted on the substrate by SMT to form a mounting module; S10, The mounting module is encapsulated to form a plastic-encapsulated module; S11 involves balling the plastic-encapsulated module and finally dicing it to form the product.
[0029] In step S1, the thermal sliding disassembly temperature is controlled at 200℃.
[0030] like Figure 4 As shown, the specific process of step S6 is as follows: S61, first sputtering of the metal seed layer, then coating with positive photoresist; S62 utilizes adjustments to exposure energy and development time to achieve a photoresist structure with an inverted trapezoidal bottom and a nearly vertical upper section. S63, then copper plating is used to fill the inverted trapezoidal area, followed by nickel and tin-silver plating to fill the upper and middle vertical structures. S64, after removing the photoresist and metal seed layer, finally reflows to form interconnect bumps.
[0031] In step S61, the positive photoresist includes an upper photoresist and a lower photoresist. The lower photoresist is used to accelerate lateral etching to form an undercut, and the upper photoresist is used to define the pattern position. The thickness of the upper and lower photoresist layers is adjusted according to the circuit and tin-silver thickness. The thickness of the lower photoresist layer is in the range of 5~10um, and the thickness of the upper photoresist layer is in the range of 10~20um.
[0032] The shape is defined as one or more combinations of trapezoids, rectangles, circles, and ellipses.
[0033] SMT is an abbreviation for Surface Mount Technology, a technology that directly mounts electronic components onto the surface of a printed circuit board (PCB). It is widely used in the manufacturing of various electronic products, including mobile phones, computers, televisions, and automotive electronics. The SMT process flow includes solder paste printing, mounting, reflow soldering, inspection, rework, cleaning, packaging, and shipping.
[0034] The present invention finally fabricates interconnect bumps through an electroplating process, which includes metal seed layer deposition, photoresist coating, exposure and development, electroplating to form bumps, and removal of photoresist and metal seed layer. The photoresist used is a liftoff process photoresist; overexposure is employed during exposure to create an inverted trapezoidal (under-cut) cross-section that is narrower at the top and wider at the bottom; and the wetting time during development must be sufficient to fully dissolve the underlying photoresist.
[0035] In the case of non-in-situ grown interconnect bumps, multiple patterning processes are typically used to implement the RDL. However, this invention can reduce the patterning process to achieve non-in-situ grown interconnect bumps, such as... Figure 5 As shown.
Claims
1. A packaging structure for correcting the exposed position of vertical wire bonding, comprising a substrate, characterized in that: The substrate (1) is provided with several packaging units, each packaging unit includes a stacked chip group (2) in a stepped manner, and each chip group (2) is bonded to the substrate (1) by a vertical lead (3); the vertical lead (3) is connected to a bump at one end near the substrate (1).
2. The packaging structure for correcting the exposed position of vertical bonding wires according to claim 1, characterized in that: The protrusions include protrusions and bumps. The protrusion (4) has a trapezoidal structure. One end of the protrusion (4) is connected to the vertical lead (3), and the other end of the protrusion (5) is connected to the bump (6).
3. The packaging structure for correcting the exposed position of vertical bonding wires according to claim 2, characterized in that: The protrusion (4) is electroplated copper.
4. The packaging structure for correcting the exposed position of vertical bonding wires according to claim 2, characterized in that: The bump (6) is a rectangular structure plated with nickel and tin silver, and the other end of the bump (6) is perpendicular to the other end of the protrusion (4).
5. A packaging method for correcting the exposed position of the vertical bonding wire in a packaging structure, characterized in that: The specific method is as follows: S1. Prepare a flat carrier plate with vertical continuity, and apply a layer of light-transmitting heat-sliding disassembly temporary bonding adhesive to the carrier plate. S2, with the functional side of the chip facing up, and referring to the alignment reference marks on the carrier board, stack and mount several chips onto the carrier board in a staggered manner; S3, vertical wire bonding is performed at the step position exposed on the functional surface of the chip; S4. After the wire bonding operation is completed, the entire multi-chipset is encapsulated, and the encapsulation height is higher than the wire height. S5. After the molding process is completed, use high-precision grinding equipment to horizontally grind the molded surface until all wire ends are exposed. S6, prepare trapezoidal copper structures on the polished molding surface and subsequently grow nickel and tin-silver; S7, use a hot slide bonder to remove the carrier board and clean the plastic-encapsulated wafer with hot slide adhesive; S8, cut the molded body into pieces to obtain the final wire bonding module; S9, the wire bonding module is mounted on the substrate by SMT to form a mounting module; S10, The mounting module is encapsulated to form a plastic-encapsulated module; S11 involves balling the plastic-encapsulated module and finally dicing it to form the product.
6. The packaging method for correcting the exposed position of the vertical bonding wire in the packaging structure according to claim 5, characterized in that: In step S1, the thermal sliding disassembly temperature is controlled at 200℃.
7. The packaging method for correcting the exposed position of the vertical bonding wire in the packaging structure according to claim 5, characterized in that: The specific process of step S6 is as follows: S61, first sputtering of the metal seed layer, then coating with positive photoresist; S62 utilizes adjustments to exposure energy and development time to achieve a photoresist structure with an inverted trapezoidal bottom and a nearly vertical upper section. S63, then copper is electroplated to fill the inverted trapezoidal area, and then nickel and tin silver are electroplated to fill the upper vertical structure. S64, after removing the photoresist and metal seed layer, finally reflows to form interconnect bumps.
8. The packaging method for correcting the exposed position of the vertical bonding wire in the packaging structure according to claim 7, characterized in that: In step S61, the positive photoresist includes an upper photoresist and a lower photoresist. The lower photoresist is used to accelerate lateral etching to form an undercut, and the upper photoresist is used to define the pattern position. The thickness of the upper and lower photoresist layers is adjusted according to the circuit and tin-silver thickness. The thickness of the lower photoresist layer is in the range of 5~10um, and the thickness of the upper photoresist layer is in the range of 10~20um.
9. The packaging method for correcting the exposed position of the vertical bonding wire in a packaging structure according to claim 8, characterized in that: The defined shape is one or more combinations of trapezoids, rectangles, circles, and ellipses.
10. The packaging method for correcting the exposed position of the vertical bonding wire in a packaging structure according to claim 5, characterized in that: In step S9, SMT stands for Surface Mount Technology. The SMT process includes placement, reflow, and underfill.